CVS log for src/sys/arch/evbarm/iq80310/iq80310_machdep.c

Up to [cvs.NetBSD.org] / src / sys / arch / evbarm / iq80310

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

Fix format specifier for physmem from %d to 0x%"PRIxPSIZE" in multiple places.

Should fix VERBOSE_INIT_ARM for various evbarm kernel configs.
Also add 0x prefix in few previously fixed places to improve readability.

Pull up following revision(s) (requested by skrll in ticket #411):

	sys/arch/evbarm/nslu2/nslu2_machdep.c: revision 1.41
	sys/arch/evbarm/gumstix/gumstix_machdep.c: revision 1.75
	sys/arch/evbarm/iq80321/iq80321_machdep.c: revision 1.66
	sys/arch/iyonix/iyonix/iyonix_machdep.c: revision 1.34
	sys/arch/zaurus/zaurus/machdep.c: revision 1.52
	sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c: revision 1.41
	sys/arch/hpcarm/hpcarm/pxa2x0_hpc_machdep.c: revision 1.33
	sys/arch/evbarm/iq80310/iq80310_machdep.c: revision 1.96
	sys/arch/evbarm/adi_brh/brh_machdep.c: revision 1.53
	sys/arch/arm/include/arm32/pmap.h: revision 1.177
	sys/arch/evbarm/viper/viper_machdep.c: revision 1.34
	sys/arch/evbarm/iyonix/iyonix_machdep.c: revision 1.5
	sys/arch/evbarm/npwr_fc/npwr_fc_machdep.c: revision 1.30
	sys/arch/evbarm/hdl_g/hdlg_machdep.c: revision 1.35
	sys/arch/arm/arm32/pmap.c: revision 1.440
	sys/arch/evbarm/lubbock/lubbock_machdep.c: revision 1.45
	sys/arch/evbarm/ixdp425/ixdp425_machdep.c: revision 1.47

Fix non-DIAGNOSTIC builds

Fix non-DIAGNOSTIC builds

Provide a shared pmap_devmap implementation and convert all pmap_devmap
arrays to use DEVMAP_ENTRY{,_END}

fix multiplei repetitive typos in comments, messages and documentation. mainly because copy paste code big amount of files are affected.

Sync with HEAD

Sync with HEAD

PMAP_DEBUG has been deleted on arm

Trailing whitespace

Mostly merge changes from HEAD upto 20200411

Consistently use vaddr_t as initarm and friends return type.

Makes no difference to binaries except for aarch64 where it's required

Sync with HEAD

- Almost all ppbreg.h's definitions are also in pcireg.h. Remove duplicated
  definitions from ppbreg.h and move some definitions from ppbreg.h to
  pcireg.h.
- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status
  and Discard Timer SERR# Enable bit in pci_subr.c.
- PCI_BRIDGE_PREFETCHBASE32_REG and PCI_BRIDGE_PREFETCHLIMIT32_REG are
  "upper" 32bit registers, rename to *UP32_REG to avoid confusion.
- Use macro.

Sync with HEAD, resolve a couple of conflicts

Fix a commit

Ssync with HEAD

Centralise defparam CONSADDR, CONSPEED, CONMODE and CONADDR into
opt_console.h and adjust.

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

Sprinkle #include "opt_arm_debug.h" where VERBOSE_INIT_ARM is used

update from HEAD

Sync with HEAD

Sync with HEAD.  (Note that most of these changes are simply $NetBSD$
tag issues.)

switch all ports to use uvm_init.c:uvm_md_init()

uvm_setpagesize() is now subsumed within this funciton.

Replace more vm_offset_t, vm_size_t with vaddr_t, vsize_t
Use paddr_t for msgbufphys

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

<arm/locore.h> fallout (fixes some include ordering errors)

Resync to 2012-11-19 00:00:00 UTC

sync with head

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed.  Default cortex to pmap_needs_fixup = 1.  But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

Move the standard definitions of the {UND,IRQ,FIQ,ABT}_STACK_SIZE to
<arm32/machdep.h>
Move the extern for cpu_reset_address to the same file.
Add cpu_reset_address_paddr.
Kill cpu_reset_v4_MMU_disable.
if cpu_reset_address is NULL, then the MMU will be disabled.

Fix more -fno-common fallout.
Move more variables to common locations.

#include <sys/bus.h> instead of <machine/bus.h>.

dependant -> dependent

sync with head

Use cpu_* prefix to call cpu_* functions (setttb() -> cpu_setttb()); no
functional changes.

Garbage collect an unused global, vm_offset_t pagetables_start.

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places.  Reduce sys/user.h inclusions.

Kill proc0paddr.  Use lwp0.l_addr instead.

sync with head.

Remove all declarations of physmem from sys/arch.  Add an include of
<sys/systm.h> to the one file that did not already contain it.
This now means that physmem can be changed by updating systm.h and uvm_page.c
(excluding fixing printfs)

sync with head.

Sync with HEAD.

Sync with HEAD.

Update haad-dm branch to haad-dm-base2.

As discussed on tech-kern: mutex_init is too heavyweight for early bootstrap
phases, so move the initialization of the ksyms mutex back into main via
a function called ksyms_init. Rename the existing (but quite different)
ksyms_init* variations into ksyms_addsyms_elf() and ksyms_addsyms_explicit()
and adapt machdep code accordingly.

Remove LKMs and switch to the module framework, pass 1.

Proposed on tech-kern@.

It is not appropriate to call pmf_system_shutdown(9) from
doshutdownhooks(9): shutdown hooks registered by shutdownhook_establish(9)
expect to be called with interrupts disabled, but shutdown hooks
registered with pmf_device_register1(9) expect to be called with
interrupts enabled.  So I have made two changes:

1 Do not call pmf_system_shutdown() from doshutdownhooks().  Instead,
change every call to doshutdownhooks() to a call to doshutdownhooks()
followed by a call to pmf_system_shutdown().  No functional change
is intended by this change.

2 Make i386 re-enable interrupts briefly while it calls
pmf_system_shutdown().  I leave it to others either to fix the
other ports, or to factor out some MI shutdown code, as joerg@
suggests, and fix that.  Note that a functional change *is* intended
by this change.

I hope that this patch will stop us from flip-flopping between
calling doshutdownhooks() and pmf_system_shutdown() sometimes with
and sometimes without interrupts enabled.

Sync with HEAD.

sync with head.

sync with head.

Merge kernel changes in matt-armv6 to HEAD.

sync with HEAD

Sync with HEAD.

Sync with HEAD.

sync with head

Sync with HEAD

Remove arm support for IPKDB.

It hasn't worked since arm was broken out from arm32 in Jan 2001, and
no-one has noticed or cared to fix it.

Make all the evbarm kernels build again.  Fix lossage from rebase.

Sync with head.

sync with head.

sync with head.

s/independant/independent/, from Zafer.

sync with head

sync with head.

Sync with head.

Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.

sync with head.

in initarm(), initialise kernel_l1pt.pv_va as well as kernel_l1pt.pv_pa.

merge ktrace-lwp.

Sync with HEAD.

Fix comments regarding configration bounaries

Fix comments slighly

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Uppercase CPU, plural is CPUs.

Bump initial kernel PTs to 4.

__KERNEL_RCSID()

Use the new pmap_devmap facility in the on-board device mapping code.

Replace the ad-hoc "section mapping table" for static device mappings
with a more generic "devmap" structure that can also handle mappings
made with large and small pages.  Add new pmap routines to enter these
mappings during bootstrap (and "remember" the devmap), and routines to
look up the static mappings once the kernel is running.

Also pass a type argument to comcnattach() and com_kgdb_attach().
comspeed() (and thus cominit()) may need this information.

Move KERNEL_VM_SIZE into the C files where its used.

Move KERNEL_VM_BASE inside where it is used (it won't be there for long).

Decrease the verbosity level unless VERBOSE_INIT_ARM is defiend.

Don't expose KERNEL_TEXT_BASE outside of board-specific code.  This gives
individual board start-up code more flexibility about where the kernel
starts in the kernel address space.

Reduce differences between ARM32_NEW_VM_LAYOUT and not; always pass
the start and end of the kernel managed virtual address space to
pmap_bootstrap() in the new pmap.

Remove old pmap support for platforms which have fully switched over.

Eliminate PTE_BASE and the PT-PT completely in the ARM32_PMAP_NEW case.
Also in the ARM32_PMAP_NEW case, reclaim the USPACE-bytes of wasted space
at the top of the user address that hasn't been needed for a very very
long time.

Call ksyms_init() instead of ddb_init() in case of
	NKSYMS || defined(DDB) || defined(LKM)

Use high vectors on IQ80321 and IQ80310.

Adapt to ARM32_PMAP_NEW.

Use PAGE_SIZE rather than NBPG.

Revert pull-up of revision 1.43 (requested by rearnsha in ticket #1170):
  Revert cached memory access to L1 tables, this causes instability
  on the release branch.

Merge the nathanw_sa branch.

Sync with HEAD.

Pull up revision 1.43 (requested by thorpej in ticket #712):
  Do cached memory access to L1 tables, making sure to
  write-back the cache after any L1 table modifications.

Catch up to -current.

sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work

remove trailing \n in panic().  approved perry.

sync kqueue branch with HEAD

catch up with -current.

Sync with -current.

Enable caching on kernel and user page tables.  This saves having
to do uncached memory access during VM operations (which can be
quite expensive on some CPUs).

We currently write-back PTEs as soon as they're modified; there is
some room for optimization (to write them back in larger chunks).
For PTEs in the APTE space (i.e. PTEs for pmaps that describe another
process's address space), PTEs must also be evicted from the cache
complete (PTEs in PTE space will be evicted durint a context switch).

Do cached memory access to L1 tables, making sure to write-back the
cache after any L1 table modifications.

Catch up to -current.

Move the calls to uvm_page_physload() out of pmap_bootstrap() and
into platform-specific initialization code, giving platform-specific
code control over which free list a given chunk of memory gets put
onto.

Changes are essentially mechanical.  Test compiled for all ARM
platforms, test booted on Intel IQ80321 and Shark.

Discussed some time ago on port-arm.

Move the uvm_setpagesize() call to platform-dependent code in preparation
for other changes to pmap_bootstrap().

Curproc->curlwp renaming.

Change uses of "curproc->l_proc" back to "curproc", which is more like the
original use. Bare uses of "curproc" are now "curlwp".

"curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL)
so that it is always safe to reference curproc (*de*referencing curproc
is another story, but that's always been true).

catch up with -current on kqueue branch

Catch up to -current.

* Add the ability to display .'s on the 7seg display.
* Display . . when halted.

Remove exception for CONSPEED on NPWR -- current redboot uses 115200, too.

* Move the code that cleans the XScale mini-data cache into its
  own function.
* Add a new function which sets up the mini-data cache clean area
  properly.

* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
  Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h.  While
  doing this, two bugs (as a result of typos) were fixed in

	arm/arm32/bus_dma.c
	evbarm/integrator/int_bus_dma.c

Clean up handling of the vector page on 32-bit ARM systems:
* Don't refer to VA 0, instead refer to a new variable: vector_page
* Delete the old zero_page_*() functions, replacing them with a new
  one: vector_page_setprot().
* When manipulating vector page mappings in user pmaps, only do so if
  the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the
  vector page is mapped by the kernel pmap).
* Add a new function, arm32_vector_init(), which takes the virtual
  address of the vector page (which MUST be valid when the function
  is called) and a bitmask of vectors the kernel is going to take
  over, and performs all vector page initialization, including setting
  the V bit in the CPU Control register ("relocate vectors to high
  address"), if necessary.

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

* Fix use of pmap_curmaxkvaddr.
* Use the PTP hint in the pmap.

* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE
* Rename ALT_PAGE_TBLS_BASE -> APTE_BASE
* Garbage-collect PAGE_TABLE_SPACE_START

Catch up with -current.

* Add support for running the IQ80310 kernel where KERNEL_BASE !=
  physical memory start.  Garbage-collect some cruft while here.
* Move the kernel up to 0xc0000000, giving a 1G/3G kernel/user split.
* Adjust the Integrator startup code accordingly.

Implement pmap_growkernel for arm32 based ports.
Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats.
Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.

Catch up to -current.

Add some nops after we enable the MMU, for good measure (enough for
the nops to be the prefetch'd insns when the MMU switch occurs).

Make sure the MMU is enabled after we switch to the new kernel
page tables (gzboot disables the MMU before it does its work).

Fix the "va" argument to pmap_map_entry() when mapping kernel_ptpt.
This happened to work in the IOP310 because the kernel runs VA==PA.

Change pmap_map_entry() to work like pmap_map_chunk(): take a pointer
to the L1 table and a virtual address, and no pointer to the L2 table.
The L2 table will be looked up by pmap_map_entry(), which will panic
if the there is no L2 table for the requested VA.

NOTE: IT IS EXTREMELY IMPORTANT THAT THE CORRECT VIRTUAL ADDRESS
BE PROVIDED TO pmap_map_entry()!  Notably, the code that mapped
the kernel L2 tables into the kernel PT mapping L2 table were not
passing actual virtual addresses, but rather offsets into the range
mapped by the L2 table.  I have fixed up all of these call sites,
and tested the resulting kernel on both an IQ80310 and a Shark.
Other portmasters should examine their pmap_map_entry() calls if
their new kernels fail.

Keep track of which kernel PTs are available during bootstrap,
and let pmap_map_chunk() lookup the correct one to use for the
current VA.  Eliminate the "l2table" argument to pmap_map_chunk().

Add a second L2 table for mapping kernel text/data/bss on the
IQ80310 (fixes booting kernels with ramdisks).

Always pass the L1 table to pmap_map_chunk().  This allows pmap_map_chunk()
to perform some error checking.

map_chunk() -> pmap_map_chunk(), and move it to pmap.c

Fix typo in comment.

map_pagetable() -> pmap_link_l2pt(), and move it to pmap.c

Collapse map_entry{,ro,nc}() into a single pmap_map_entry() that
takes a prot and a "cacheable" indicator.

Rename map_section() to pmap_map_section(), move it to pmap.c, and give it
an extra argument (prot - specifies protection of the mapping).

Sync w/ -current.

file iq80310_machdep.c was added on branch kqueue on 2002-02-11 20:07:45 +0000

Default the console to the correct speed on the Npwr (so that
it doesn't have to be set in the kernel config file).

Don't hard-code the console address in error messages.

irq_init() -> iq80310_intr_init()

Overhaul of the ARM cache code.  This is mostly a simplification
pass.  Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:

	icache_sync_all         Synchronize I-cache
	icache_sync_range       Synchronize I-cache range

	dcache_wbinv_all        Write-back and Invalidate D-cache
	dcache_wbinv_range      Write-back and Invalidate D-cache range
	dcache_inv_range        Invalidate D-cache range
	dcache_wb_range         Write-back D-cache range

	idcache_wbinv_all       Write-back and Invalidate D-cache,
				Invalidate I-cache
	idcache_wbinv_range     Write-back and Invalidate D-cache,
				Invalidate I-cache range

Note: This does not yet include an overhaul of the actual asm files
that implement the primitives.  Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.

Some prototype cleanup.

Allow the console unit to be overridden with the CONUNIT configuration
option.

When mapping the kernel text/data/bss:
* Round the text size up the next page, don't truncate it.
* Pass the kernel L1 table to map_chunk() so that it can try
  to use section mappings.

More catchup.

Catch up to -current.

If we're attaching UART2, then use UART2 in failure-case panic()s.

Update copyright notice.

Don't need to include <machine/irqhandler.h>

Use <arm/undefined.h> instead of <machine/undefined.h>.

No need to pull in <machine/pte.h> directly.

Sync the thorpej-mips-cache branch with -current.

file iq80310_machdep.c was added on branch nathanw_sa on 2002-01-08 00:24:28 +0000

Allocate the appropriate space for the XScale global cache clean code.

Add some rudimentary support for ELF symbols in DDB on the ARM ports.
On platforms which load the kernel sans symbols directly from firmware
(possibly in e.g. S-Record format), call ddb_init() with empty arguments,
so that it will search any compiled in SYMTAB_SPACE.  On all other platforms,
if __ELF__, also call ddb_init() with empty arguments until ELF bootloaders
which pass symbol information are ready.

Remove unneeded declarations of the db_machine_init() function.  The
ARM ports are the only ones that actually have one, and it is about
to change.

Remove unnecessary prototypes for zero_page_read{only,write}().

Correct a comment.

* Define fixed virtual addresses for the Primary and Secondary
  PCI I/O spaces, as well as the i80312 PMMRs.  Map these regions
  in early bootstrap along with the on-board device address space.
* Adjust call to i80312_sdram_bounds() for the new way the PMMRs
  are defined in i80312reg.h
* Word around some serious braindamage in RedBoot -- RedBoot uses
  the on-board Ethernet to TFTP the kernel image.  However, it does
  not stop the Ethernet before transferring control to the loaded
  program.  This means that if it happens to receive another packet
  (broadcast/multicast/unicast), it will happily scribble over the
  memory of the new running program.  Work around this problem by
  performing a secondary-bus-reset on the i80312's PPB.  XXX This
  could be problematic if we ever encounter an application where
  the i80312's PPB is actually used as a passthrough PPB.

Rework and fleshing out of Intel IQ80310 XScale eval board support.
More work to do -- this is a snapshot of work-in-progress.

more evbarm files (very incomplete).