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Annotation of src/sys/arch/evbarm/integrator/intmmu.S, Revision 1.5.6.1

1.5.6.1 ! skrll       1: /*     $NetBSD: intmmu.S,v 1.6 2004/02/13 11:36:12 wiz Exp $ */
1.1       rearnsha    2:
                      3: /*
                      4:  * Copyright (c) 2001 ARM Ltd
                      5:  * All rights reserved.
                      6:  *
                      7:  * Redistribution and use in source and binary forms, with or without
                      8:  * modification, are permitted provided that the following conditions
                      9:  * are met:
                     10:  * 1. Redistributions of source code must retain the above copyright
                     11:  *    notice, this list of conditions and the following disclaimer.
                     12:  * 2. Redistributions in binary form must reproduce the above copyright
                     13:  *    notice, this list of conditions and the following disclaimer in the
                     14:  *    documentation and/or other materials provided with the distribution.
                     15:  * 3. The name of the company may not be used to endorse or promote
                     16:  *    products derived from this software without specific prior written
                     17:  *    permission.
                     18:  *
                     19:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
                     20:  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
                     21:  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
                     22:  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
                     23:  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
                     24:  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
                     25:  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
                     26:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
                     27:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
                     28:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
                     29:  * SUCH DAMAGE.
                     30:  */
1.2       thorpej    31:
1.1       rearnsha   32: #include "assym.h"
                     33: #include <machine/asm.h>
                     34: #include <arm/armreg.h>
1.2       thorpej    35: #include <arm/arm32/pte.h>
1.1       rearnsha   36:
1.5       rearnsha   37:        .section .start,"ax",%progbits
1.1       rearnsha   38:
                     39: ASENTRY_NP(integrator_start)
                     40:        mov     r6, #0x16000000         /* UART0 Physical base*/
                     41:        mov     r3, #'A'
                     42:        str     r3, [r6]                /* Let the world know we are alive */
                     43:
                     44: /*
                     45:  * At this time the MMU is off.
                     46:  * We build up an initial memory map at 0x8000 that we can use to get
                     47:  * the kernel running from the top of memory.  All mappings in this table
                     48:  * use L1 section maps.
                     49:  */
                     50:
                     51: /*
                     52:  * Set Virtual == Physical
                     53:  */
1.4       thorpej    54:        mov     r3, #(L1_S_AP(AP_KRW))
                     55:        add     r3, r3, #(L1_TYPE_S)
1.1       rearnsha   56:        mov     r2, #0x100000           /* advance by 1MB */
                     57:        mov     r1, #0x8000             /* page table start */
                     58:        mov     r0, #0x1000             /* page table size */
                     59:
                     60: Lflat:
                     61:        str     r3, [r1], #0x0004
                     62:        add     r3, r3, r2
                     63:        subs    r0, r0, #1
                     64:        bgt     Lflat
                     65:
                     66: /*
1.5       rearnsha   67:  * Map VA 0xc0000000->0xc03fffff to PA 0x00000000->0x003fffff
1.1       rearnsha   68:  */
1.4       thorpej    69:        mov     r3, #(L1_S_AP(AP_KRW))
                     70:        add     r3, r3, #(L1_TYPE_S)
1.1       rearnsha   71:        mov     r1, #0x8000             /* page table start */
1.3       thorpej    72:        add     r1, r1, #(0xc00 * 4)    /* offset to 0xc00xxxxx */
1.5       rearnsha   73: #      add     r1, r1, #(0x001 * 4)    /* offset to 0xc01xxxxx */
                     74:        mov     r0, #63
1.1       rearnsha   75: Lkern:
1.5       rearnsha   76:        str     r3, [r1], #0x0004       /* 0xc000000-0xc03fffff */
1.1       rearnsha   77:        add     r3, r3, r2
                     78:        subs    r0, r0, #1
                     79:        bgt     Lkern
                     80: /*
                     81:  * Mapping the peripheral register region (0x10000000->0x1fffffff) linearly
                     82:  * would require 256MB of virtual memory (as much space as the entire kernel
                     83:  * virtual space).  So we map the first 1M of each 16MB sub-space into the
                     84:  * region VA 0xfd000000->0xfdffffff; this should map enough of the peripheral
                     85:  * space to at least get us up and running.
                     86:  */
1.4       thorpej    87:        mov     r3, #(L1_S_AP(AP_KRW))
                     88:        add     r3, r3, #L1_TYPE_S
1.1       rearnsha   89:        add     r3, r3, #0x10000000     /* Peripherals base */
                     90:        mov     r1, #0x8000             /* page table start */
                     91:        add     r1, r1, #(0xfd0 * 4)
                     92:        mov     r2, #0x01000000         /* 16MB increment.  */
                     93:        mov     r0, #16
                     94: Lperiph:
                     95:        str     r3, [r1], #4            /* 0xfd000000-0xfdffffff */
                     96:        add     r3, r3, r2
                     97:        subs    r0, r0, #1
                     98:        bgt     Lperiph
                     99:
                    100: /*
                    101:  * We now have our page table ready, so load it up and light the blue
                    102:  * touch paper.
                    103:  */
                    104:
                    105:        /* set the location of the L1 page table */
                    106:        mov     r1, #0x8000
                    107:        mcr     p15, 0, r1, c2, c0, 0
                    108:
                    109:        /* Flush the old TLBs (just in case) */
                    110:        mcr     p15, 0, r1, c8, c7, 0
                    111:        mov     r2, #'B'
                    112:        strb    r2, [r6]
                    113:
                    114:        /* Set the Domain Access register.  Very important! */
                    115:        mov     r1, #1
                    116:        mcr     p15, 0, r1, c3, c0, 0
                    117:
                    118:        /*
                    119:         * set mmu bit (don't set anything else for now, we don't know
                    120:         * what sort of CPU we have yet.
                    121:         */
                    122:        mov     r1, #CPU_CONTROL_MMU_ENABLE
                    123:
                    124: /*
1.5.6.1 ! skrll     125:  * This is where it might all start to go wrong if the CPU fitted to your
1.1       rearnsha  126:  * integrator does not have an MMU.
                    127:  */
                    128:        /* fetch current control state */
                    129:        mrc     p15, 0, r2, c1, c0, 0
                    130:        orr     r2, r2, r1
                    131:
                    132:        /* set new control state */
                    133:        mcr     p15, 0, r2, c1, c0, 0
                    134:
                    135:        mov     r0, r0
                    136:        mov     r0, r0
                    137:        mov     r0, r0
                    138:
                    139:        /* emit a char.  Uart is now at 0xfd600000 */
                    140:        mov     r6, #0xfd000000
                    141:        add     r6, r6, #0x00600000
                    142:        mov     r2, #'C'
                    143:        strb    r2, [r6]
                    144:
                    145:        /* jump to kernel space */
                    146:        mov     r0, #0x0200
                    147:
                    148:        /* Switch to kernel VM and really set the ball rolling.  */
                    149:        ldr     pc, Lstart
                    150:
                    151: Lstart:        .long   start

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