Annotation of src/sys/arch/bebox/stand/boot/io.c, Revision 1.8
1.8 ! riastrad 1: /* $NetBSD: io.c,v 1.7 2010/10/14 05:52:01 kiyohara Exp $ */
1.1 sakamoto 2:
3: /*-
4: * Copyright (C) 1995-1997 Gary Thomas (gdt@linuxppc.org)
5: * All rights reserved.
6: *
7: * PCI/ISA I/O support
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions and the following disclaimer.
14: * 2. Redistributions in binary form must reproduce the above copyright
15: * notice, this list of conditions and the following disclaimer in the
16: * documentation and/or other materials provided with the distribution.
17: * 3. All advertising materials mentioning features or use of this software
18: * must display the following acknowledgement:
19: * This product includes software developed by Gary Thomas.
20: * 4. The name of the author may not be used to endorse or promote products
21: * derived from this software without specific prior written permission.
22: *
23: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33: */
34:
1.4 junyoung 35: #include <lib/libsa/stand.h>
1.3 sakamoto 36: #include "boot.h"
37:
1.7 kiyohara 38: volatile u_char *PCI_mem = (u_char *)0xc0000000;
1.3 sakamoto 39: volatile u_char *ISA_io = (u_char *)0x80000000;
1.7 kiyohara 40: volatile u_char *ISA_mem = (u_char *)0xc0000000;
41:
42: static int dcache_line_size = 32;
1.1 sakamoto 43:
44: void
1.7 kiyohara 45: outb(int port, u_char val)
1.1 sakamoto 46: {
1.6 kiyohara 47:
1.1 sakamoto 48: ISA_io[port] = val;
49: }
50:
1.6 kiyohara 51: void
52: outw(int port, u_short val)
53: {
54:
55: outb(port, val >> 8);
56: outb(port + 1, val);
57: }
58:
1.3 sakamoto 59: u_char
1.6 kiyohara 60: inb(int port)
1.1 sakamoto 61: {
1.6 kiyohara 62:
63: return ISA_io[port];
1.1 sakamoto 64: }
65:
1.7 kiyohara 66: u_short
67: inw(int port)
68: {
69:
70: return *((volatile uint16_t *)(&ISA_io[port]));
71: }
72:
73: u_short
74: inwrb(int port)
75: {
76:
77: return le16toh(*((volatile uint16_t *)(&ISA_io[port])));
78: }
79:
80: void
81: writeb(u_long addr, u_char val)
82: {
83:
84: PCI_mem[addr] = val;
85: }
86:
87: void
88: writel(u_long addr, u_long val)
89: {
90:
91: *((u_long *)&PCI_mem[addr]) = htole32(val);
92: }
93:
94: u_char
95: readb(u_long addr)
96: {
97:
98: return PCI_mem[addr];
99: }
100:
101: u_short
102: readw(u_long addr)
103: {
104:
105: return le16toh(*((u_short *)&PCI_mem[addr]));
106: }
107:
108: u_long
109: readl(u_long addr)
110: {
111:
112: return le32toh(*((u_long *)&PCI_mem[addr]));
113: }
114:
1.3 sakamoto 115: u_long
1.6 kiyohara 116: local_to_PCI(u_long addr)
1.1 sakamoto 117: {
1.6 kiyohara 118:
119: return (addr & 0x7FFFFFFF) | 0x80000000;
1.1 sakamoto 120: }
1.7 kiyohara 121:
122: void
123: _wbinv(uint32_t adr, uint32_t siz)
124: {
125: uint32_t bnd;
126:
1.8 ! riastrad 127: asm volatile("eieio" ::: "memory");
1.7 kiyohara 128: for (bnd = adr + siz; adr < bnd; adr += dcache_line_size)
1.8 ! riastrad 129: asm volatile("dcbf 0,%0" :: "r"(adr) : "memory");
! 130: asm volatile("sync" ::: "memory");
1.7 kiyohara 131: }
132:
133: void
134: _inv(uint32_t adr, uint32_t siz)
135: {
136: uint32_t bnd, off;
137:
138: off = adr & (dcache_line_size - 1);
139: adr -= off;
140: siz += off;
1.8 ! riastrad 141: asm volatile("eieio" ::: "memory");
1.7 kiyohara 142: if (off != 0) {
143: /* wbinv() leading unaligned dcache line */
1.8 ! riastrad 144: asm volatile("dcbf 0,%0" :: "r"(adr) : "memory");
1.7 kiyohara 145: if (siz < dcache_line_size)
146: goto done;
147: adr += dcache_line_size;
148: siz -= dcache_line_size;
149: }
150: bnd = adr + siz;
151: off = bnd & (dcache_line_size - 1);
152: if (off != 0) {
153: /* wbinv() trailing unaligned dcache line */
1.8 ! riastrad 154: asm volatile("dcbf 0,%0" :: "r"(bnd) : "memory"); /* it's OK */
1.7 kiyohara 155: if (siz < dcache_line_size)
156: goto done;
157: siz -= off;
158: }
159: for (bnd = adr + siz; adr < bnd; adr += dcache_line_size) {
160: /* inv() intermediate dcache lines if ever */
1.8 ! riastrad 161: asm volatile("dcbi 0,%0" :: "r"(adr) : "memory");
1.7 kiyohara 162: }
163: done:
1.8 ! riastrad 164: asm volatile("sync" ::: "memory");
1.7 kiyohara 165: }
CVSweb <webmaster@jp.NetBSD.org>
![[BACK]](/icons/back.gif){kind=icon}
Return to io.c CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [cvs.NetBSD.org] / src / sys / arch / bebox / stand / boot