CVS log for src/sys/arch/arm/xscale/i80321_pci.c

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Keyword substitution: kv
Default branch: MAIN

Remove unnecessary sys/malloc.h include

Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
  Provide a new resource provider API:

  ==> pciconf_resource_init() -- Initialize a PCI configuration resources
      container.
  ==> pciconf_resource_add() -- Add a PCI configuration resource to the
      container (I/O, MEM, or prefetchable MEM).  Multiple resources of
      each type may be added.
  ==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
      container once the bus has been configured.

  This is much easier to use than the previous method of providing an
  extent map for each kind of resource, and works better for e.g. ACPI
  platforms that provide potentially multiple PCI resources in tables
  provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
  rather than extent maps.

replace EX_NOWAIT with EX_WAITOK in device attach methods.
remove checks for failures that can no longer occur.

update from HEAD

Sync with HEAD (as of 26th Dec)

PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
  if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
  Currently the following extended capabilities are decoded:
   - Advanced Error Reporting
   - Virtual Channel
   - Device Serial Number
   - Power Budgeting
   - Root Complex Link Declaration
   - Root Complex Event Collector Association
   - Access Control Services
   - Alternative Routing-ID Interpretation
   - Address Translation Services
   - Single Root IO Virtualization
   - Page Request
   - TPH Requester
   - Latency Tolerance Reporting
   - Secondary PCI Express
   - Process Address Space ID
   - LN Requester
   - L1 PM Substates
  The following extended capabilities are not decoded yet:
   - Root Complex Internal Link Control
   - Multi-Function Virtual Channel
   - RCRB Header
   - Vendor Unique
   - Configuration Access Correction
   - Multiple Root IO Virtualization
   - Multicast
   - Resizable BAR
   - Dynamic Power Allocation
   - Protocol Multiplexing
   - Downstream Port Containment
   - Precision Time Management
   - M-PCIe
   - Function Reading Status Queueing
   - Readiness Time Reporting
   - Designated Vendor-Specific

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

<arm/locore.h> fallout (fixes some include ordering errors)

Resync to 2012-11-19 00:00:00 UTC

sync with head

struct device * -> device_t for IXP4xx (and nslu2).
Tested with my NSLU2.

Fix more pci_conf_interrupt/pci_conf_hook problems

sync with head

merge to -current.

Change old-stlye-defintions to C89 prototypes.
Switch to CFATTACH_DECL_NEW/device_t/cfdata_t
Defer attaching interrupt evcnts.

Approved by releng.

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

#include <sys/bus.h> instead of <machine/bus.h>.

Sync with HEAD.

sync with HEAD

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

sync with head.

Sync with head.

Sync with head.

Update to HEAD.

sync with head.

Implement ATU Direct Window in order to increase available PCI address
space.

sync with head.

Add an offset to the I/O port translations.  This allows IQ80321
and others to avoid providing PCI I/O space at address 0.
Iyonix, however, needs to provide PCI I/O space at 0.
The others require I/O space to be offset in part due to a bug
work-around in wm(4) which requires that I/O space access be used
to reset the controllers.  If I/O space is mapped at zero, the card
claims, but ignores, the transactions, and the controller doesn't
get reset properly and can't then be used.

merge ktrace-lwp.

Pull up revision 1.5 (requested by briggs in ticket #1092):
Start I/O range at base+0x1000 to avoid 0.

Sync with HEAD.

Start I/O range at base+0x1000 to avoid 0.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

__KERNEL_RCSID()

PCI-X requires that that devices updated their PCIXSR on every
config write with the device number specified in AD[15:11].  If
we don't set this field when issuing a Type 0 cycle, each device
could end of thinking it is at device 0, which can cause a number
of problems.  Doing this unconditionally should be OK when only
PCI devices are present.

Use aprint*().

catch up with -current on kqueue branch

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

file i80321_pci.c was added on branch kqueue on 2002-06-23 17:34:58 +0000

file i80321_pci.c was added on branch nathanw_sa on 2002-04-01 07:39:16 +0000

Basic support for the Intel i80321 I/O Processor (Xscale core).

Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.