version 1.14, 2020/03/23 10:26:07 |
version 1.15, 2020/03/24 03:08:02 |
Line 396 ave_fdt_attach(device_t parent, device_t |
|
Line 396 ave_fdt_attach(device_t parent, device_t |
|
sc->sc_model, hwver >> 8, hwver & 0xff, phy_mode); |
sc->sc_model, hwver >> 8, hwver & 0xff, phy_mode); |
aprint_normal_dev(self, "interrupt on %s\n", intrstr); |
aprint_normal_dev(self, "interrupt on %s\n", intrstr); |
|
|
sc->sc_100mii = (strcmp(phy_mode, "rgmii") == 0) ? CFG_MII : 0; |
sc->sc_100mii = (strcmp(phy_mode, "rgmii") != 0); |
sc->sc_desops = (sc->sc_model == 64) ? &ave64ops : &ave32ops; |
sc->sc_desops = (sc->sc_model == 64) ? &ave64ops : &ave32ops; |
|
|
CSR_WRITE(sc, AVEGR, GR_GRST | GR_PHYRST); |
CSR_WRITE(sc, AVEGR, GR_GRST | GR_PHYRST); |
Line 522 ave_reset(struct ave_softc *sc) |
|
Line 522 ave_reset(struct ave_softc *sc) |
|
|
|
CSR_WRITE(sc, AVERXC, 0); /* stop Rx first */ |
CSR_WRITE(sc, AVERXC, 0); /* stop Rx first */ |
CSR_WRITE(sc, AVEDESCC, 0); /* stop Tx/Rx descriptor engine */ |
CSR_WRITE(sc, AVEDESCC, 0); /* stop Tx/Rx descriptor engine */ |
if (sc->sc_100mii & CFG_MII) { |
if (sc->sc_100mii) { |
csr = CSR_READ(sc, AVERMIIC); |
csr = CSR_READ(sc, AVERMIIC); |
CSR_WRITE(sc, AVERMIIC, csr &~ RMIIC_RST); |
CSR_WRITE(sc, AVERMIIC, csr &~ RMIIC_RST); |
DELAY(10); |
DELAY(10); |