Annotation of src/sys/arch/arm/samsung/exynos4_reg.h, Revision 1.3
1.1 matt 1: /* $NetBSD */
2: /*-
3: * Copyright (c) 2014 The NetBSD Foundation, Inc.
4: * All rights reserved.
5: *
6: * This code is derived from software contributed to The NetBSD Foundation
7: * by Reinoud Zandijk.
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions and the following disclaimer.
14: * 2. Redistributions in binary form must reproduce the above copyright
15: * notice, this list of conditions and the following disclaimer in the
16: * documentation and/or other materials provided with the distribution.
17: *
18: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28: * POSSIBILITY OF SUCH DAMAGE.
29: */
30:
31: #ifndef _ARM_SAMSUNG_EXYNOS4_REG_H_
32: #define _ARM_SAMSUNG_EXYNOS4_REG_H_
33:
34: /*
35: * Physical memory layout of Exynos SoCs as per documentation
36: *
37: * Base Address Limit Address Size Description
38: * 0x00000000 0x00010000 64 KB iROM
39: * 0x02000000 0x02010000 64 KB iROM (mirror of 0x0 to 0x10000)
40: * 0x02020000 0x02060000 256 KB iRAM
41: * 0x03000000 0x03020000 128 KB Data memory or general purpose of Samsung
42: * Reconfigurable Processor SRP.
43: * 0x03020000 0x03030000 64 KB I-cache or general purpose of SRP.
44: * 0x03030000 0x03039000 36 KB Configuration memory (write only) of SRP
45: * 0x03810000 0x03830000 AudioSS's SFR region
46: * 0x04000000 0x05000000 16 MB Bank0 of Static ROM Controller (SMC)
47: * (16-bit only)
48: * 0x05000000 0x06000000 16 MB Bank1 of SMC
49: * 0x06000000 0x07000000 16 MB Bank2 of SMC
50: * 0x07000000 0x08000000 16 MB Bank3 of SMC
51: * 0x08000000 0x0C000000 64 MB Reserved
52: * 0x0C000000 0x0CD00000 Reserved
53: * 0x0CE00000 0x0D000000 SFR region of Nand Flash Contr. (NFCON)
54: * 0x10000000 0x14000000 SFR region
55: * 0x40000000 0xA0000000 1.5 GB Memory of Dynamic Memory Contr. (DMC)-0
56: * 0xA0000000 0x00000000 1.5 GB Memory of DMC-1
57: */
58:
59: /*
60: *
61: * The exynos can boot from its iROM or from an external Nand memory. Since
62: * these are normally hardly used they are excluded from the normal register
63: * space here.
64: *
65: * XXX What about the audio subsystem region. Where are the docs?
66: *
67: * EXYNOS_CORE_PBASE points to the main SFR region.
68: *
69: * Notes:
70: *
71: * SFR Special Function Register
72: * ISP In-System Programming, like a JTAG
73: * ACP Accelerator Coherency Port
74: * SSS Security Sub System
75: * GIC Generic Interurrupt Controller
76: * PMU Power Management Unit
77: * DMC 2D Graphics engine
78: * LEFTBUS Data bus / Peripheral bus
79: * RIGHTBUS ,,
80: * G3D 3D Graphics engine
81: * MFC Multi-Format Codec
82: * LCD0 LCD display
83: * MCT Multi Core Timer
84: * CMU Clock Management Unit
85: * TMU Thermal Management Unit
86: * PPMU Pin Parametric Measurement Unit (?)
87: * MMU Memory Management Unit
88: * MCTimer ?
89: * WDT Watch Dog Timer
90: * RTC Real Time Clock
91: * KEYIF Keypad interface
92: * SECKEY ?
93: * TZPC TrustZone Protection Controller
94: * UART Universal asynchronous receiver/transmitter
95: * I2C Inter IC Connect
96: * SPI Serial Peripheral Interface Bus
97: * I2S Inter-IC Sound, Integrated Interchip Sound, or IIS
98: * PCM Pulse-code modulation, audio stream at set fixed rate
99: * SPDIF Sony/Philips Digital Interface Format
100: * Slimbus Serial Low-power Inter-chip Media Bus
101: * SMMU System mmu. No idea as how its programmed (or not)
102: * PERI-L UART, I2C, SPI, I2S, PCM, SPDIF, PWM, I2CHDMI, Slimbus
103: * PERI-R CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, MCTimer, WDT, RTC, KEYIF,
104: * SECKEY, TZPC
105: */
106:
107: /*
108: * Note that this table is not 80-char friendly, this is done to allow more
109: * elaborate comments to clarify the register offsets use
110: */
111:
112: #define EXYNOS4_CORE_SIZE 0x04000000
113: #define EXYNOS4_SDRAM_PBASE 0x40000000
114:
115: #define EXYNOS4_SYSREG_OFFSET 0x00010000
116: #define EXYNOS4_PMU_OFFSET 0x00020000 /* Power Management Unit */
117: #define EXYNOS4_CMU_TOP_PART_OFFSET 0x00030000 /* XXX unknown XXX */
118: #define EXYNOS4_CMU_CORE_ISP_PART_OFFSET 0x00040000 /* XXX unknown XXX */
119: #define EXYNOS4_MCT_OFFSET 0x00050000 /* Multi Core Timer */
120: #define EXYNOS4_WDT_OFFSET 0x00060000 /* Watch Dog Timer */
121: #define EXYNOS4_RTC_OFFSET 0x00070000 /* Real Time Clock */
122: #define EXYNOS4_KEYIF_OFFSET 0x000A0000 /* Keypad interface */
123: #define EXYNOS4_HDMI_CEC_OFFSET 0x000B0000 /* HDMI Consumer Electronic Control */
124: #define EXYNOS4_TMU_OFFSET 0x000C0000 /* Thermal Managment */
125: #define EXYNOS4_SECKEY_OFFSET 0x00100000 /* XXX unknown XXX */
126: #define EXYNOS4_TZPC0_OFFSET 0x00110000 /* ARM Trusted Zone Protection Controller */
127: #define EXYNOS4_TZPC1_OFFSET 0x00120000
128: #define EXYNOS4_TZPC2_OFFSET 0x00130000
129: #define EXYNOS4_TZPC3_OFFSET 0x00140000
130: #define EXYNOS4_TZPC4_OFFSET 0x00150000
131: #define EXYNOS4_TZPC5_OFFSET 0x00160000
132: #define EXYNOS4_INTCOMBINER_OFFSET 0x00440000 /* combines first 32 interrupt sources */
133: #define EXYNOS4_GIC_CNTR_OFFSET 0x00480000 /* generic interrupt controller offset */
134: #define EXYNOS4_GIC_DISTRIBUTOR_OFFSET 0x00490000
135: #define EXYNOS4_AP_C2C_OFFSET 0x00540000 /* Chip 2 Chip XXX doc? XXX */
136: #define EXYNOS4_CP_C2C_MODEM_OFFSET 0x00580000
137: #define EXYNOS4_DMC0_OFFSET 0x00600000 /* Dynamic Memory Controller */
138: #define EXYNOS4_DMC1_OFFSET 0x00610000
139: #define EXYNOS4_PPMU_DMC_L_OFFSET 0x006A0000 /* event counters XXX ? */
140: #define EXYNOS4_PPMU_DMC_R_OFFSET 0x006B0000
141: #define EXYNOS4_PPMU_CPU_OFFSET 0x006C0000
142: #define EXYNOS4_GPIO_C2C_OFFSET 0x006E0000
143: #define EXYNOS4_TZASC_LR_OFFSET 0x00700000 /* trust zone access control */
144: #define EXYNOS4_TZASC_LW_OFFSET 0x00710000
145: #define EXYNOS4_TZASC_RR_OFFSET 0x00720000
146: #define EXYNOS4_TZASC_RW_OFFSET 0x00730000
147: #define EXYNOS4_G2D_ACP_OFFSET 0x00800000 /* 2D graphics engine */
148: #define EXYNOS4_SSS_OFFSET 0x00830000 /* Security Sub System */
149: #define EXYNOS4_CORESIGHT_1_OFFSET 0x00880000 /* 1st region */
150: #define EXYNOS4_CORESIGHT_2_OFFSET 0x00890000 /* 2nd region */
151: #define EXYNOS4_CORESIGHT_3_OFFSET 0x008B0000 /* 3rd region */
152: #define EXYNOS4_SMMUG2D_ACP_OFFSET 0x00A40000 /* system mmu for 2D graphics engine */
153: #define EXYNOS4_SMMUSSS_OFFSET 0x00A50000 /* system mmu for SSS */
154: #define EXYNOS4_GPIO_RIGHT_OFFSET 0x01000000
155: #define EXYNOS4_GPIO_LEFT_OFFSET 0x01400000
156: #define EXYNOS4_FIMC0_OFFSET 0x01800000 /* image for display */
157: #define EXYNOS4_FIMC1_OFFSET 0x01810000
158: #define EXYNOS4_FIMC2_OFFSET 0x01820000
159: #define EXYNOS4_FIMC3_OFFSET 0x01830000
160: #define EXYNOS4_JPEG_OFFSET 0x01840000 /* JPEG Codec */
161: #define EXYNOS4_MIPI_CSI0_OFFSET 0x01880000 /* MIPI-Slim bus Interface */
162: #define EXYNOS4_MIPI_CSI1_OFFSET 0x01890000
163: #define EXYNOS4_SMMUFIMC0_OFFSET 0x01A20000 /* system mmus */
164: #define EXYNOS4_SMMUFIMC1_OFFSET 0x01A30000
165: #define EXYNOS4_SMMUFIMC2_OFFSET 0x01A40000
166: #define EXYNOS4_SMMUFIMC3_OFFSET 0x01A50000
167: #define EXYNOS4_SMMUJPEG_OFFSET 0x01A60000
168: #define EXYNOS4_FIMD0_OFFSET 0x01C00000 /* LCD0 */
169: #define EXYNOS4_MIPI_DSI0_OFFSET 0x01C80000 /* LCD0 */
170: #define EXYNOS4_SMMUFIMD0_OFFSET 0x01E20000 /* system mmus */
171: #define EXYNOS4_FIMC_ISP_OFFSET 0x02000000 /* (digital) camera video input */
172: #define EXYNOS4_FIMC_DRC_TOP_OFFSET 0x02010000
173: #define EXYNOS4_FIMC_FD_TOP_OFFSET 0x02040000
174: #define EXYNOS4_MPWM_ISP_OFFSET 0x02110000 /* (specialised?) PWM */
175: #define EXYNOS4_I2C0_ISP_OFFSET 0x02130000 /* I2C bus */
176: #define EXYNOS4_I2C1_ISP_OFFSET 0x02140000
177: #define EXYNOS4_MTCADC_ISP_OFFSET 0x02150000 /* (specialised?) AD Converter */
178: #define EXYNOS4_PWM_ISP_OFFSET 0x02160000 /* PWM */
179: #define EXYNOS4_WDT_ISP_OFFSET 0x02170000 /* Watch Dog Timer */
180: #define EXYNOS4_MCUCTL_ISP_OFFSET 0x02180000 /* XXX micro controller control unit? */
181: #define EXYNOS4_UART_ISP_OFFSET 0x02190000 /* uart base clock */
182: #define EXYNOS4_SPI0_ISP_OFFSET 0x021A0000
183: #define EXYNOS4_SPI1_ISP_OFFSET 0x021B0000
184: #define EXYNOS4_GIC_C_ISP_OFFSET 0x021E0000
185: #define EXYNOS4_GIC_D_ISP_OFFSET 0x021F0000
186: #define EXYNOS4_SYSMMU_FIMC_ISP_OFFSET 0x02260000
187: #define EXYNOS4_SYSMMU_FIMC_DRC_OFFSET 0x02270000
188: #define EXYNOS4_SYSMMU_FIMC_FD_OFFSET 0x022A0000
189: #define EXYNOS4_SYSMMU_ISPCPU_OFFSET 0x022B0000
190: #define EXYNOS4_FIMC_LITE0_OFFSET 0x02390000 /* external image input? */
191: #define EXYNOS4_FIMC_LITE1_OFFSET 0x023A0000
192: #define EXYNOS4_SYSMMU_FIMC_LITE0_OFFSET 0x023B0000
193: #define EXYNOS4_SYSMMU_FIMC_LITE1_OFFSET 0x023C0000
194: #define EXYNOS4_USBDEV0_OFFSET 0x02480000 /* XXX unknown XXX */
195: #define EXYNOS4_USBDEV0_1_OFFSET 0x02480000
196: #define EXYNOS4_USBDEV0_2_OFFSET 0x02490000
197: #define EXYNOS4_USBDEV0_3_OFFSET 0x024A0000
198: #define EXYNOS4_USBDEV0_4_OFFSET 0x024B0000
199: #define EXYNOS4_TSI_OFFSET 0x02500000 /* Transport Stream Interface */
200: #define EXYNOS4_SDMMC0_OFFSET 0x02510000 /* SD card interface */
201: #define EXYNOS4_SDMMC1_OFFSET 0x02520000
202: #define EXYNOS4_SDMMC2_OFFSET 0x02530000
203: #define EXYNOS4_SDMMC3_OFFSET 0x02540000
204: #define EXYNOS4_SDMMC4_OFFSET 0x02550000
205: #define EXYNOS4_MIPI_HSI_OFFSET 0x02560000 /* LCD0 */
206: #define EXYNOS4_SROMC_OFFSET 0x02570000
1.2 reinoud 207: #define EXYNOS4_USBHOST0_OFFSET 0x02580000 /* USB EHCI */
208: #define EXYNOS4_USBHOST1_OFFSET 0x02590000 /* USB OHCI companion to EHCI (paired) */
1.1 matt 209: #define EXYNOS4_USBOTG1_OFFSET 0x025B0000 /* USB On The Go interface */
210: #define EXYNOS4_PDMA0_OFFSET 0x02680000 /* Peripheral DMA */
211: #define EXYNOS4_PDMA1_OFFSET 0x02690000
212: #define EXYNOS4_GADC_OFFSET 0x026C0000 /* General AD Converter */
213: #define EXYNOS4_ROTATOR_OFFSET 0x02810000 /* Image rotator for video output */
214: #define EXYNOS4_SMDMA_OFFSET 0x02840000 /* (s) Memory DMA */
215: #define EXYNOS4_NSMDMA_OFFSET 0x02850000 /* (ns) Memory DMA */
216: #define EXYNOS4_SMMUROTATOR_OFFSET 0x02A30000 /* system mmu for rotator */
217: #define EXYNOS4_SMMUMDMA_OFFSET 0x02A40000
218: #define EXYNOS4_VP_OFFSET 0x02C00000 /* Video Processor */
219: #define EXYNOS4_MIXER_OFFSET 0x02C10000 /* Video mixer */
220: #define EXYNOS4_HDMI0_OFFSET 0x02D00000
221: #define EXYNOS4_HDMI1_OFFSET 0x02D10000
222: #define EXYNOS4_HDMI2_OFFSET 0x02D20000
223: #define EXYNOS4_HDMI3_OFFSET 0x02D30000
224: #define EXYNOS4_HDMI4_OFFSET 0x02D40000
225: #define EXYNOS4_HDMI5_OFFSET 0x02D50000
226: #define EXYNOS4_HDMI6_OFFSET 0x02D60000
227: #define EXYNOS4_SMMUTV_OFFSET 0x02E20000
228: #define EXYNOS4_G3D_OFFSET 0x03000000 /* 3D Graphics Accelerator */
229: #define EXYNOS4_PPMU_3D_OFFSET 0x03220000
230: #define EXYNOS4_MFC_OFFSET 0x03400000 /* Multi Format Codec */
231: #define EXYNOS4_SMMUMFC_L_OFFSET 0x03620000
232: #define EXYNOS4_SMMUMFC_R_OFFSET 0x03630000
233: #define EXYNOS4_PMMU_MFC_L_OFFSET 0x03660000 /* ? */
234: #define EXYNOS4_PMMU_MFC_R_OFFSET 0x03670000 /* ? */
235: #define EXYNOS4_UART0_OFFSET 0x03800000 /* serial port 0 */
236: #define EXYNOS4_UART1_OFFSET 0x03810000 /* serial port 1 */
237: #define EXYNOS4_UART2_OFFSET 0x03820000 /* serial port 2 */
238: #define EXYNOS4_UART3_OFFSET 0x03830000 /* serial port 3 */
239: #define EXYNOS4_UART4_OFFSET 0x03840000 /* serial port 4 */
1.3 ! reinoud 240: #define EXYNOS4_GPIO_I2C0_OFFSET 0x03860000 /* Inter Integrated Circuit (I2C) */
1.1 matt 241: #define EXYNOS4_I2C1_OFFSET 0x03870000 /* Inter Integrated Circuit (I2C) */
242: #define EXYNOS4_I2C2_OFFSET 0x03880000 /* Inter Integrated Circuit (I2C) */
243: #define EXYNOS4_I2C3_OFFSET 0x03890000 /* Inter Integrated Circuit (I2C) */
244: #define EXYNOS4_I2C4_OFFSET 0x038A0000 /* Inter Integrated Circuit (I2C) */
245: #define EXYNOS4_I2C5_OFFSET 0x038B0000 /* Inter Integrated Circuit (I2C) */
246: #define EXYNOS4_I2C6_OFFSET 0x038C0000 /* Inter Integrated Circuit (I2C) */
247: #define EXYNOS4_I2C7_OFFSET 0x038D0000 /* Inter Integrated Circuit (I2C) */
248: #define EXYNOS4_I2CHDMI_OFFSET 0x038E0000 /* I2C for HDMI */
249: #define EXYNOS4_SPI0_OFFSET 0x03920000 /* Serial Peripheral Interface0 */
250: #define EXYNOS4_SPI1_OFFSET 0x03930000 /* Serial Peripheral Interface0 */
251: #define EXYNOS4_SPI2_OFFSET 0x03940000 /* Serial Peripheral Interface0 */
252: #define EXYNOS4_I2S1_OFFSET 0x03960000 /* sound */
253: #define EXYNOS4_I2S2_OFFSET 0x03970000 /* sound */
254: #define EXYNOS4_PCM1_OFFSET 0x03980000 /* sound */
255: #define EXYNOS4_PCM2_OFFSET 0x03990000 /* sound */
256: #define EXYNOS4_AC97_OFFSET 0x039A0000 /* AC97 audio codec sound */
257: #define EXYNOS4_SPDIF_OFFSET 0x039B0000 /* SPDIF sound */
258: #define EXYNOS4_PWMTIMER_OFFSET 0x039D0000
259:
260: /* standard frequency settings */
261: #define EXYNOS4_ACLK_REF_FREQ (200*1000*1000) /* 200 Mhz */
262: #define EXYNOS4_UART_FREQ (109*1000*1000) /* should be EXYNOS_ACLK_REF_FREQ! */
263:
264: #endif /* _ARM_SAMSUNG_EXYNOS5_REG_H_ */
265:
CVSweb <webmaster@jp.NetBSD.org>
![[BACK]](/icons/back.gif){kind=icon}
Return to exynos4_reg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [cvs.NetBSD.org] / src / sys / arch / arm / samsung