CVS log for src/sys/arch/arm/sa11x0/sa11x0_irq.S

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Keyword substitution: kv
Default branch: MAIN

irq_entry(): Do not clobber fp (= r11), in order not to confuse DDB.

Use r10 instead; no need to preserve saipic_base, previous content of
r10, throughout this function, except for the case of INTR_DEBUG.

For INTR_DEBUG, load saipic_base to scratch register every time it
becomes necessary. This is no performance penalty compared with
subsequent printf() calls.

XXX
Rewrite this function by C. There seems no particular reason to
use assembler, and no major performance regression is expected.

Sync w/ HEAD.

Adjust egister usage so that r4 and r5 are preserved as cur{cpu,lwp}
respectively as required by the change to make ASTs operate per-LWP
rather than per-CPU.  DO_AST_AND_RESTORE_ALIGNMENT_FAULTS expects this.

Remove the call to dosoftints while I'm here as it's dont in DO_AST...

XXX untested

Trailing whitespace

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Don't use cpsr_all/spsr_all with mrs, it doesn't take a mask.

sync with head

Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

sync with head

Avoid using r7 (which is being reserved for a different purpose).

sync with head

Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits.  Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

sync with head.

Sync with HEAD.

Sync w/ -current. 34 merge conflicts to follow.

Sync with head.

sync with head.

Let hpcarm kernels boot again after the merge of the armv6 branch.  Fixes
PR port-hpcarm/38591

XXX: There is still a hard hang that I've seen on both shark and hpcarm in
the process exit path; I don't know much beyond that yet.

Sync with HEAD.

sync with head.

sync with head.

Merge kernel changes in matt-armv6 to HEAD.

Sync with HEAD.

Sync with HEAD.

Given the that there are only 4 IPLs (ignoring soft IPLs), a number of
cleanups can be done:
Remove _SPL_* aliases.
Don't store irqmasks in ci_cpl, just make it an ipl level.
Add fast softint switching support.

sync with head

Sync to HEAD.

sync with HEAD

Sync with HEAD

As of this commit, all arm32 kernel now build.

Truly kill current_intr_depth once and for all.

Make all the evbarm kernels build again.  Fix lossage from rebase.

sync with head.

Remove _lock_cas() in favor of atomic_cas_32().

Sync with HEAD.

Rewrite the ARM mutex implementation to be of the simple-mutex variety.
Because pre-v6 ARM lacks support for an atomic compare-and-swap, we
implement _lock_cas() as a restartable atomic squence that is checked
in the IRQ handler right before AST processing.  (This is safe because,
for all practical purposes, there are no SMP pre-v6 ARM systems.)

This can serve as a model for other non-MP platforms that lack the
necessary atomic operations for mutexes (SuperH, for example).

Upshots of this change:
- kmutex_t is now down to 8 bytes on ARM; about as good as we can get.
- ARM2 systems don't have to trap and emulate SWP or SWPB for mutexes.

The acorn26 port is not updated by this commit to do the LOCK_CAS_CHECK.
That is left as an exercise for the port maintainer.

Reviewed and tested by Matt Thomas.

sync with head

sync with head.

Sync with head.

Prefix dbg_str with "L".

file sa11x0_irq.S was added on branch yamt-pdpolicy on 2006-03-05 11:30:59 +0000

Prefix dbg_str with "L".

merge ktrace-lwp.

Sync with HEAD. Here we go again...

sync with head

Fix some typos.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Enable/Restore alignment fault state on interrupt handler entry/exit.

Fix for PR arm/17971.  Used patch as provided

Compiled, but no hardware to test on.

Catch up to -current.

Continue the " - . - 8" purge.  Specifically:

add	rd, pc, #foo - . - 8		->	adr	rd, foo
ldr	rd, [pc, #foo - . - 8]		->	ldr	rd, foo

Also, when saving the return address for a function pointer call, use
"mov lr, pc" just before the call unless the return address is somewhere
other than just after the call site.

Finally, a few obvious little micro-optimisations like using LDR directly
rather than ADR followed by LDR, and loading directly into PC rather than
bouncing via R0.

sync kqueue branch with HEAD

Catch up to -current.

catch up with -current.

change include path

catch up with -current on kqueue branch

Catch up to -current.

Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel.  What
  you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
  on which ARM architecture versions are configured (based on CPU_*
  options).  Also defines ARM_NARCH to determins how many architecture
  versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
  which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
  to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.

file sa11x0_irq.S was added on branch nathanw_sa on 2002-04-17 00:02:35 +0000

Initial copy of SA11x0 support from hpcarm.