CVS log for src/sys/arch/arm/rockchip/rk_cru.h

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Add initial support for RK3588 SoC (CRU and IOMUX)

- change struct rk_cru_arm and RK_CPU macros to allow mux and div registers to be specified independently.
  Allow more div-regs to be specified in the future.
- commonize RK*_PLL() macro.

Make .reg1 and .reg2 of struct rk_cru_cpu_rate into array, and change the type of those to bus_size_t and uint32_t.
Array size may increase in the future.

arm: rockchip: Add support for RK3288 SoC.

The Rockchip RK3288 is a quad core Cortex-A17 SoC.

Mostly merge changes from HEAD upto 20200411

Pull up following revision(s) (requested by jmcneill in ticket #427):

	sys/dev/ic/dw_hdmi_phy.c: revision 1.2
	sys/dev/ic/dw_hdmi.c: revision 1.4
	sys/dev/fdt/ausoc.c: revision 1.5
	sys/dev/ic/dw_hdmi.h: revision 1.2
	sys/dev/ic/dw_hdmi.h: revision 1.3
	sys/dev/ic/dw_hdmi.h: revision 1.4
	sys/conf/files: revision 1.1242
	sys/dev/fdt/fdtvar.h: revision 1.57
	sys/arch/arm/rockchip/rk3399_cru.c: revision 1.11
	sys/arch/arm/rockchip/rk3399_cru.c: revision 1.12
	sys/arch/arm/rockchip/rk3399_cru.c: revision 1.13
	sys/arch/evbarm/conf/GENERIC64: revision 1.110
	sys/arch/arm/rockchip/rk_drm.c: revision 1.1
	sys/arch/arm/rockchip/rk_drm.c: revision 1.2
	sys/arch/evbarm/conf/GENERIC64: revision 1.112
	sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.1
	sys/dev/fdt/fdt_clock.c: revision 1.10
	sys/arch/evbarm/conf/GENERIC64: revision 1.113
	sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.2
	sys/arch/arm/rockchip/rk_drm.h: revision 1.1
	sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.3
	sys/arch/arm/rockchip/rk_fb.c: revision 1.1
	sys/arch/arm/dts/rk3399-rockpro64.dts: revision 1.9
	sys/arch/arm/rockchip/rk_vop.c: revision 1.1
	sys/arch/arm/rockchip/rk_vop.c: revision 1.2
	sys/arch/arm/rockchip/rk_i2c.c: revision 1.6
	sys/arch/arm/rockchip/rk_cru.h: revision 1.6
	sys/arch/arm/rockchip/rk_cru.h: revision 1.7
	sys/arch/arm/rockchip/rk_cru_composite.c: revision 1.4
	sys/arch/arm/rockchip/rk_cru_composite.c: revision 1.5
	sys/arch/arm/rockchip/files.rockchip: revision 1.21
	sys/arch/arm/rockchip/rk_i2s.c: revision 1.1
	sys/arch/arm/rockchip/files.rockchip: revision 1.22
	sys/dev/ic/dw_hdmi.c: revision 1.2
	sys/dev/ic/dw_hdmi_phy.c: revision 1.1
	sys/dev/ic/dw_hdmi.c: revision 1.3

Support reads of more than 32 bytes in a single xfer.

Add support for internal DesignWare HDMI PHYs

Add fdtbus_clock_enable and fdtbus_clock_enable_index shortcuts

Add HDMI and VOP clocks

WIP display driver for Rockchip RK3399

Add (commented out) Rockchip display support

Select the correct MPLL and PHY settings for the requested pixel clock
Force DCLK_VOP0/1 dividers to 1 and select closest match when setting PLL
rates.

Fix typo in phy config table

Fix a few swapped fields

Remove debug output

Enable Rockchip display support

Set sysclk rate at set_format time, so the link set_format callback can read the new sysclk

Add I2S audio input support.
Add software volume controls.
Add support for I2S clocks.
Add driver for Rockchip I2S/PCM controller.
Enable HDMI audio on ROCKPro64
Add rki2s
Add audio support

Add support for I2S clocks.

Force DCLK_VOP0/1 dividers to 1 and select closest match when setting PLL
rates.

rk3399: add definition for the watchdog timer clock gate

The watchdog timer clock gate is a bit special because it's a secure
gate that can only be accessed from EL3. We still need a dummy gate
definition for it so that dwcwdt(4) can infer the frequency via the
parent clock. The gate is enabled by default by U-Boot.

Sync with HEAD

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

Add support for RK3399 CPU clocks.

Add support for Rockchip RK3399 SoC.

Sync with HEAD

Use syscon API.

Sync with HEAD

file rk_cru.h was added on branch pgoyette-compat on 2018-06-25 07:25:39 +0000

Add initial support for Rockchip RK3328 SoC.