CVS log for src/sys/arch/arm/nvidia/tegra124_car.c

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tegra124_car(4): Attach rndsource synchronously.

It looks like the original motivation for deferring to
config_interrupts was to wait until softint_establish worked.  But
this no longer needs to use softints to deliver the entropy, so
that's moot.

Doing this synchronously gives us a better chance for more entropy
earlier.

tegra124_car(4): No need for rnd lock -- delete it.

This only ever reads from a single device register, so no need to
serialize access.

XXX This should really have a hardware-specific health test, but I
can't find any documentation on the underlying physical entropy
source.

Sync with HEAD.

Rename of_match_compat_data() to of_compatible_match().  Similarly,
rename of_search_compatible() to of_compatible_lookup().

Standardize on of_compatible_match() for driver matching, and adapt
all call sites.

Add CEC clock

rnd_attach_source calls the callback itself now.

No need for every driver to explicitly call it to prime the pool.

Eliminate now-unused <sys/rndpool.h>.

Mostly merge changes from HEAD upto 20200411

Restore %# for PRIxBUSADDR

Use PRIxBUSADDR

Sync with HEAD

Add Tegra124 "mselect" clock and two PCIe-related clocks it sources.

With mainline u-boot (not starting the pci subsystem in the firmware):
Gets to a root prompt instead of hanging during tegrapcie attach, but
PCIe remains non-functional without a modern "xusbpad" phy driver for
Tegra124 (needed to configure the lane map).

Ssync with HEAD

Register clocks with clk_attach

Pass clock provider's phandle to fdtbus_clock_controller_func.decode()
and update callers.

This allows to accomodate clock managers whose clocks are identified
directly by a clock instead of a pair (clock provider, index).

ok jmcneill@ on port-arm

update from HEAD

Sync with HEAD

file tegra124_car.c was added on branch tls-maxphys on 2017-12-03 11:35:54 +0000

Add support for NVIDIA Tegra X1.

Sync with HEAD - tag prg-localcount2-base1

add APB-DMA clock gate

Sync with HEAD

Set host1x parent to pll_p_out0

Fix fractional divider calculations and round down for sdmmc clocks.

Sync with HEAD

Add support for multiple clock domains in clk API.

Add GPU gating clock

Sync with HEAD

Sync with HEAD

fix off by one.

ok riastradh

Sync with HEAD.  (Note that most of these changes are simply $NetBSD$
tag issues.)

Simplify bcm2835, tegra, and am335x hardware RNG drivers.

Tested by nick@.

Sync with HEAD

Add Tegra124 CAR bits to support the XUSB xHCI core.

Source of pll_p_out5 is not div_pllp_out5 but div_pll_p_out5.

Complete implementation of clocks for SPI controllers in tegra124_car.

Fix I2C clock calculations.  Previously I2C clocks were half what was
requested.  The I2C clock registers have a LSB of one-half rather than
one-whole like the rest of them.

Sync with HEAD (as of 26th Dec)

file tegra124_car.c was added on branch nick-nhusb on 2015-12-27 12:09:31 +0000

fix divider calculations for hdmi, and treat clock ID 211 as pll_p_out0 instead of directly pll_p

Switch Tegra over to fdt based clocks and reset controls.