version 1.2, 2002/01/08 21:00:12 |
version 1.3, 2003/12/31 14:40:32 |
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#define IOMD_DMA_SIZE 24 |
#define IOMD_DMA_SIZE 24 |
#define IOMD_DMA_SPACING 32 |
#define IOMD_DMA_SPACING 32 |
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/* Each DMA channel has the same set of registers. */ |
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#define IOMD_DMAEND_STOP 0x80000000 |
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#define IOMD_DMAEND_LAST 0x40000000 |
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#define IOMD_DMAEND_OFFSET 0x00000fff |
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#define IOMD_DMACR_CLEAR 0x80 |
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#define IOMD_DMACR_DIR 0x40 |
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#define IOMD_DMACR_ENABLE 0x20 |
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#define IOMD_DMACR_BYTE 0x01 |
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#define IOMD_DMACR_HALFWORD 0x02 |
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#define IOMD_DMACR_WORD 0x04 |
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#define IOMD_DMACR_QUADWORD 0x10 |
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#define IOMD_DMAST_OVERRUN 0x04 |
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#define IOMD_DMAST_INT 0x02 |
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#define IOMD_DMAST_BANKB 0x01 |
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#define IOMD_DMAST_BANKA 0x00 |
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#define IOMD_IO0CURA 0x00000040 |
#define IOMD_IO0CURA 0x00000040 |
#define IOMD_IO0ENDA 0x00000041 |
#define IOMD_IO0ENDA 0x00000041 |
#define IOMD_IO0CURB 0x00000042 |
#define IOMD_IO0CURB 0x00000042 |