version 1.40.16.2, 2008/02/28 21:47:43 |
version 1.41, 2007/09/15 09:25:22 |
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#include <sys/types.h> |
#include <sys/types.h> |
#include <arm/cpuconf.h> |
#include <arm/cpuconf.h> |
#include <arm/armreg.h> |
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struct cpu_functions { |
struct cpu_functions { |
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Line 156 extern struct cpu_functions cpufuncs; |
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Line 155 extern struct cpu_functions cpufuncs; |
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extern u_int cputype; |
extern u_int cputype; |
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#define cpu_id() cpufuncs.cf_id() |
#define cpu_id() cpufuncs.cf_id() |
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#define cpu_cpwait() cpufuncs.cf_cpwait() |
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#define cpu_control(c, e) cpufuncs.cf_control(c, e) |
#define cpu_control(c, e) cpufuncs.cf_control(c, e) |
#define cpu_domains(d) cpufuncs.cf_domains(d) |
#define cpu_domains(d) cpufuncs.cf_domains(d) |
Line 426 void ixp12x0_setup (char *); |
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Line 426 void ixp12x0_setup (char *); |
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#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ |
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ |
defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) |
defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) |
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void xscale_cpwait (void); |
void xscale_cpwait (void); |
#define cpu_cpwait() cpufuncs.cf_cpwait() |
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void xscale_cpu_sleep (int); |
void xscale_cpu_sleep (int); |
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Line 471 void xscale_setup (char *); |
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Line 469 void xscale_setup (char *); |
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#define setttb cpu_setttb |
#define setttb cpu_setttb |
#define drain_writebuf cpu_drain_writebuf |
#define drain_writebuf cpu_drain_writebuf |
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#ifndef cpu_cpwait |
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#define cpu_cpwait() |
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#endif |
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/* |
/* |
* Macros for manipulating CPU interrupts |
* Macros for manipulating CPU interrupts |
*/ |
*/ |
#ifdef __PROG32 |
#ifdef __PROG32 |
static __inline u_int32_t __set_cpsr_c(uint32_t bic, uint32_t eor) __attribute__((__unused__)); |
static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); |
static __inline u_int32_t disable_interrupts(uint32_t mask) __attribute__((__unused__)); |
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static __inline u_int32_t enable_interrupts(uint32_t mask) __attribute__((__unused__)); |
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static __inline uint32_t |
static __inline u_int32_t |
__set_cpsr_c(uint32_t bic, uint32_t eor) |
__set_cpsr_c(u_int bic, u_int eor) |
{ |
{ |
uint32_t tmp, ret; |
u_int32_t tmp, ret; |
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__asm volatile( |
__asm volatile( |
"mrs %0, cpsr\n" /* Get the CPSR */ |
"mrs %0, cpsr\n" /* Get the CPSR */ |
Line 499 __set_cpsr_c(uint32_t bic, uint32_t eor) |
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Line 491 __set_cpsr_c(uint32_t bic, uint32_t eor) |
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return ret; |
return ret; |
} |
} |
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static __inline uint32_t |
#define disable_interrupts(mask) \ |
disable_interrupts(uint32_t mask) |
(__set_cpsr_c((mask) & (I32_bit | F32_bit), \ |
{ |
(mask) & (I32_bit | F32_bit))) |
uint32_t tmp, ret; |
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mask &= (I32_bit | F32_bit); |
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__asm volatile( |
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"mrs %0, cpsr\n" /* Get the CPSR */ |
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"orr %1, %0, %2\n" /* set bits */ |
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"msr cpsr_c, %1\n" /* Set the control field of CPSR */ |
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: "=&r" (ret), "=&r" (tmp) |
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: "r" (mask) |
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: "memory"); |
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return ret; |
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} |
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static __inline uint32_t |
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enable_interrupts(uint32_t mask) |
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{ |
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uint32_t ret, tmp; |
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mask &= (I32_bit | F32_bit); |
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__asm volatile( |
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"mrs %0, cpsr\n" /* Get the CPSR */ |
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"bic %1, %0, %2\n" /* Clear bits */ |
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"msr cpsr_c, %1\n" /* Set the control field of CPSR */ |
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: "=&r" (ret), "=&r" (tmp) |
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: "r" (mask) |
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: "memory"); |
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return ret; |
#define enable_interrupts(mask) \ |
} |
(__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) |
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#define restore_interrupts(old_cpsr) \ |
#define restore_interrupts(old_cpsr) \ |
(__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) |
(__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) |