CVS log for src/sys/arch/arm/include/cpufunc.h

Up to [cvs.NetBSD.org] / src / sys / arch / arm / include

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Keyword substitution: kv
Default branch: MAIN

G/C

Move arm_cache_info from cpufunc.h to cpu.h

Sync with HEAD.

Add DISABLE_INTERRUPT_SAVE(), like DISABLE_INTERRUPT() but also returns
the previous state.

Use DISABLE_INTERRUPT_SAVE()/ENABLE_INTERRUPT() in pic_splfuncs instead
of cpsid()/cpsie(). The difference here is the caller no longer specifies
which bits to disable and enable; on arm32 we continue to use I32_bit and
on aarch64 we now consistently toggle both IRQ and FIQ state.

Add ENABLE_INTERRUPT() / DISABLE_INTERRUPT() macros for compatibility
with aarch64.

Sync w/ HEAD.

Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.

Fix armv6 builds by providing an armv6 is macro

Fix RPI (armv6) build

Define isb(), dsb(option), and dmb(option)

Catch up with vchiq upstream to allow this.

Sync with HEAD

Sync with HEAD, resolve a few conflicts

Don't exclude code from rump kernel build.

Sync with HEAD, resolve a couple of conflicts

Clean up around cpu_ttb and fix a bunch of builds

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

Whitespace

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

Remove port-acorn26

OK core@

update from HEAD

Sync with HEAD

Sync with HEAD

apply some #if (ARM_MMU_V6 + ARM_MMU_V7) != 0.
now this builds on pre v6-only.

Sync with HEAD

Rename the cpu_id() define to cpu_idnum() so that it does not conflict with
dtrace and friends.

Sync with HEAD (as of 26th Dec)

remove tlb_flush define and change callers to use cpu_tlb_flushID directly, ok matt@

Rebase to HEAD as of a few days ago.

Rebase.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

include cpufunc_proto.h since things need it.

Move xscale cpu_cpwait back from cpufunc_proto.ht to cpufunc.h

Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.

Declare armv7 routines if CPU_ARMV7 is defined.
Rearrange in less random manner.

cortex doesn't need xscale_setup
use arm11_setttb for arm11x6.

Use cpsie/cpsid if possible.
change cache_type to uint8_t
more ARM_MMU_EXTENDED support (ASID)

Add way_size to arm_cache_info
Fix arm67_tlb_purge prototype

Keep track of what each cache is (VIVT/VIPT/PIPT).

cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache

Make the tlb_flush*SE take a vaddr_t, not a u_int.

Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.

Make multiple inclusion symbols always start with _ARM_ (not _ARM32_ or
_MACHINE_).

resync from head

Nuke cpu_pfr, just use the armreg_pfr?_read inlines

Make PJ4B support code compilable.

Obtained from Marvell, Semihalf.

sync with (a bit old) head

Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.

Resync to 2012-11-19 00:00:00 UTC

C99 types

sync with head

Add armv7_drain_writebuf (which is just a dsb).

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed.  Default cortex to pmap_needs_fixup = 1.  But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

Add secondary cache range ops

Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

Pull up revisions:
  src/sys/arch/evbarm/dev/plcomreg.h revisions 1.2,1.3,1.4
  src/sys/arch/evbarm/conf/INTEGRATOR revision 1.65
  src/sys/arch/evbarm/dev/plcom.c revisions 1.34,1.35,1.36,1.37,1.38,1.39,1.40
  src/sys/arch/evbarm/ifpga/plcom_ifpga.c revisions 1.12,1.13,1.14
  src/sys/arch/evbarm/dev/plcomvar.h revisions 1.9,1.10,1.11
  src/sys/arch/evbarm/ifpga/plcom_ifpgavar.h revision 1.2
  src/sys/arch/arm/arm/cpufunc.c revisions 1.105,1.108
  src/sys/arch/arm/arm32/cpu.c revision 1.79
  src/sys/arch/arm/include/armreg.h revisions 1.49,1.54
  src/sys/arch/arm/arm32/pmap.c revision 1.229
  src/sys/arch/arm/arm32/arm32_machdep.c revision 1.77
  src/sys/arch/arm/include/cpu.h revision 1.64
  src/sys/arch/arm/arm/cpufunc_asm_arm1136.S revision 1.3
  src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S revision 1.1
  src/sys/arch/arm/conf/files.arm revision 1.106
  src/sys/arch/arm/include/cpufunc.h revision 1.57
  src/sys/dev/sdmmc/sdhc.c revisions 1.14,1.24
  src/sys/dev/sdmmc/sdhcvar.h revisions 1.7,1.8
  src/sys/arch/evbarm/ifpga/ifpgareg.h revision 1.4
  src/sys/arch/evbarm/integrator/integrator_machdep.c revision 1.69
  src/sys/arch/arm/broadcom/bcm2835_dma.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_emmc.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_intr.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_intr.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_obio.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_plcom.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_pm.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_pmvar.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_space.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_tmr.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835reg.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835var.h revision 1.1
  src/sys/arch/arm/broadcom/bcm_amba.h revision 1.1
  src/sys/arch/arm/broadcom/files.bcm2835 revision 1.1
  src/sys/arch/evbarm/Makefile revision 1.9
  src/sys/arch/evbarm/conf/RPI revision 1.1
  src/sys/arch/evbarm/conf/files.rpi revision 1.1
  src/sys/arch/evbarm/conf/mk.rpi revision 1.1
  src/sys/arch/evbarm/conf/std.rpi revision 1.1
  src/sys/arch/evbarm/rpi/genassym.cf revision 1.1
  src/sys/arch/evbarm/rpi/rpi.h revision 1.1
  src/sys/arch/evbarm/rpi/rpi_machdep.c revision 1.1
  src/sys/arch/evbarm/rpi/rpi_start.S revision 1.1,1.2
  src/etc/etc.evbarm/Makefile.inc revision 1.28
(requested by skrll in ticket #454).

don't mix #define<TAB> and #define<SPACE> in a file.

avoid warning with options PLCOM_DEBUG for INTEGRATOR.

Rename register values. No functional change - same code before and after.

Existing names are prefixed with PL01X_ where they're common between the
PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're
found only on the respective chips.

Replace the simple_lock with a kmutex_t.  Update the locking to match
com(4) in the few places it didn't already.

DOH.  Replace a line that got accidently deleted in the last commit.

device_t/softc split
struct device * -> device_t
struct cfdata * -> cfdata_t

Add the 'Z' to the 1176 cpu product name.

ok matt@

Fix locking botch introduced in 1.36.

Fix a KASSERT. From/OK'ed by matt@

Fix racy softint dispatch that lead to KASSERT(si->si_active) in
softint_execute

Discussed with matt@. "Looks good to me"

Add the documented ARM11[37]6 Auxiliary control register defines.

Add support for the ARM1176JZS

Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that).

Provide a method for attachments to specify capabilites.

Add support for the PL011 to plcom. Pull across a bunch of fixes from
com(4) while I'm here and do some other tidyup.

Tested on a RaspberryPi.

PL010 not tested.

Initial commit of support for the RaspberryPI (www.raspberrypi.org)

This is enough for serial console via the gpio header pins and to get to
multiuser.

A huge thank you to Matt Thomas for all his help.

Add RPI to KERNEL_SETS

Remove #if 0 code.

Add support for the ARM1176JZS

Support cpu_sleep() on Sheeva CPUs.

sync with head

merge to -current.

expose functions needed to compute stack traces to kmemuser

Require arm3_cache_flush for ARM2/ARM250.

Sync with HEAD.

sync with head

Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.

sync with head

Sync with HEAD (-D20101022).

sync with head

Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
  Discovery Innovation not yet.

Sync with HEAD.

sync with head.

sync with head

Cleanup the armv7 changes.  Add ARM_ARCH_7.   Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well.  Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

sync with head.

Sync with HEAD.

Update haad-dm branch to haad-dm-base2.

Use #ifdef, not #if

Sync with HEAD.

use generic enable_interrupts() and disable_interrupts() instead of
armv6-specific interrupt control ops when _ARM_ARCH_6 not defined

Add fa526_flush_prefetchbuf

Add FA526 support (compile tested only)

Sync with HEAD.

sync with head.

sync with head.

Merge kernel changes in matt-armv6 to HEAD.

Sync with HEAD.

sync with head.

sync with HEAD

Sync with head.

Sync with HEAD.

sync with head.

we need I32_bit, so #include <arm/armreg.h>

Micro-optimizations for arm.

Make enable and disable interrupts one instruction shorter.

Make cpu_cpwait() do nothing on anything other than an xscale, where it
will still call via the cpufuncs table.

This avoids loading a function from cpufuncs and then branching into it. On
older hardware the function does nothing, so this is just a waste of CPU
cycles.

Sync to HEAD.

Sync with HEAD.

Add AT91 support from Sami Kantoluoto
Add TI OMAP2430 support from Marty Fouts @ Danger Inc

sync with -HEAD

sync with HEAD

Sync with HEAD.

sync with head.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Import TI OMAP 2430 and ARM11/ARMv6 support.  Now on ARMv6, the cache is
no longer purged on context switches.

Sync with head.

Sync with HEAD

Sync with HEAD.

ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged
as its cache/tlb management smarts relied too heavily on pre-merge context-
switch behaviour. See PR kern/36548 for one manifestation of the breakage.

To address this:
 - Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate)
   as it was too easy for them to get out of sync with the pmap.
 - Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C.
   It's only slightly less efficient, but is much more readable/maintainable.
 - Document cpufuncs.cf_context_switch() as being C-callable.
 - pmap_activate() becomes a no-op if the lwp's vmspace is already active.
   (Good performance win, since pmap_activate() is now invoked on every
   context-switch, even though ARM's cpu_switchto() already does all the
   grunt work)

XXX: Some CPU-specific armXX_context_switch() implementations (arm67,
arm7tdmi, arm8) always flush the I+D caches. This should not be necessary.
Someone with access to hardware (acorn32?) needs to deal with this.

sync with head.

Make arm11 use the armv6 cpufuncs.

Sync with HEAD.

Finally make cpufuncs work properly on acorn26, since something seems to be
using it.  This entailed adding support for ARM2 and ARM2as, and allowing
for getting CPU IDs other than from CP15, since ARM2(as) doesn't have CP15.

Un-__P.

sync with head.

Pull up following revision(s) (requested by matt in ticket #457):
	sys/arch/arm/include/cpufunc.h: revision 1.38
	sys/arch/arm/arm/cpufunc.c: revision 1.78
	sys/arch/arm/arm/cpufunc_asm_arm10.S: revision 1.6
	sys/arch/arm/include/armreg.h: revision 1.37
	sys/arch/arm/arm32/cpu.c: revision 1.64
	sys/arch/arm/arm/cpufunc_asm_armv5.S: revision 1.3
	sys/arch/arm/include/cpuconf.h: revision 1.13
	sys/arch/arm/conf/files.arm: revision 1.82
	sys/arch/arm/arm/cpufunc_asm_armv5_ec.S: revision 1.1
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E

Sync with head.

Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E

sync with head.

inline -> __inline

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

The first step to support Intel PXA270.

kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270.  If both of them are defined,
CPU is determined run-time.

Very basic support for the ARM1136.

This code takes no advantage of any 'new' features provided by
architecture 6 devices (such as physically tagged caches or new
MMU features), and basically runs the chip in a 'legacy v5' mode.

Drop parameter names from prototypes to avoid shadowing warnings.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD.

Changing the interrupt mask is a scheduling barrier.

Sync with HEAD

Switch the ARM9 to using the Dcache in write-back mode.  Avoid an
unknown problem with dcache_inv_range by using a wbinv for now
(similarly for ARM10).

When setting the ARM9 system control register, use the computed
cpuctrlmask value (not 0xffffffff) so that the clocking-mode bits are
not reset to FastBus mode (which isn't very fast).

Add processor-specific declarations for ARM10 class processors.

Fix declarations of primary cache variables, so that they are
declarations, not definitions.

support IXP425 Intel Network Processor
 running on BigEndian

Pull up revision 1.26 (requested by thorpej in ticket #682):
  Garbage-collect some unused routines.

sync kqueue branch with HEAD

catch up with -current.

Partial (ARM only) sync with trunk -- significant performance improvements
for XScale-based systems.

Garbage-collect some unused routines.

Inline SetCPSR calls where it seems prudent to do so.  This avoids two
branches and allows the compiler to better utilize registers around
calls to disable/enable/restore_interrupts().

Catch up to -current.

catch up with -current.

add support for ixp12x0

catch up with -current on kqueue branch

Catch up to -current.

Use processor specific versions of ARM cache control functions for SA1100
and SA1110 instead of using SA110 ones.

Rename common StrongARM functions from sa110_* to sa1_*.

Reviewed by Jason Thorpe.

Add support for the Intel PXA210 and PXA250.  From Hiroyuki Bessho, PR 16617.

Catch up to -current.

Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel.  What
  you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
  on which ARM architecture versions are configured (based on CPU_*
  options).  Also defines ARM_NARCH to determins how many architecture
  versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
  which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
  to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.

* Move the code that cleans the XScale mini-data cache into its
  own function.
* Add a new function which sets up the mini-data cache clean area
  properly.

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
  CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
  options, and don't let them both be defined at the same time.
  XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
  <arm/xscale/xscalereg.h>.
* Rename a few existing functions.

Catch up to -current.

Sync w/ -current.

Add prototype for sa11x0_cpu_sleep().

Overhaul of the ARM cache code.  This is mostly a simplification
pass.  Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:

	icache_sync_all         Synchronize I-cache
	icache_sync_range       Synchronize I-cache range

	dcache_wbinv_all        Write-back and Invalidate D-cache
	dcache_wbinv_range      Write-back and Invalidate D-cache range
	dcache_inv_range        Invalidate D-cache range
	dcache_wb_range         Write-back D-cache range

	idcache_wbinv_all       Write-back and Invalidate D-cache,
				Invalidate I-cache
	idcache_wbinv_range     Write-back and Invalidate D-cache,
				Invalidate I-cache range

Note: This does not yet include an overhaul of the actual asm files
that implement the primitives.  Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.

Two changes for XScale:
	1) Add defparam XSCALE_CCLKCFG to define a parameter for the
	   CCLKCFG register.  Default it to '9' on the IQ80310.
	2) Add a sleep call to the xscale CPU function vector (replacing
	   the nullop) which should drop the CPU into "idle" mode when
	   cpu_switch finds nothing on the run queues.

Sync kqueue branch with -current.

Catch up to -current.

* Share a common vector page between arm26 and arm32.
* Use a common set of exception handlers for all arm32 platforms.
* New FIQ framework based on discussions with Ben Harris, shared
  between arm26 and arm32.

Fetch cache info from the Cache Type register on ARM7TDMI and "greater"
processors.  Report this when the processor is attached.

Add prototypes for new XScale write-through cache routines.

Add a "cpwait" cpufunc, currently a nullop on all but XScale.
"cpwait" ensures that all coprocessor operations have completed
before returning.

file cpufunc.h was added on branch nathanw_sa on 2002-01-08 00:23:11 +0000

* Give the XScale its own cpu_control() entry point; we have to flush
  the Branch Target Buffer of the BPRD bit changes.
* Enable Branch Prediction on the XScale by default.
* Don't invalidate the Branch Target Buffer explicitly. the i80200
  manual (section 5.1, Branch Target Buffer Operation) notes that
  manual software management of the BTB is unnecessary; it is flushed
  implicitly when:
     * processor resets
     * FCSE process ID is written
     * I-cache is invalidated

Add support calls for ARM9.

Where ARM9, StrongARM and XScale share the same function, rename it
as armv4_XXX.

Make the declaration of get_pc_str_offset() into a prototype.

Update the kqueue branch to HEAD.

Add xscale cpu functions

Merge Aug 24 -current into the kqueue branch.

Fix typo in comment (suceed).

Catch up to -current.

Add get_pc_str_offset(), which returns the offset between the address of an
instruction that stores the program counter and the value of PC that's stored.
This can vary between ARM implementations, but is guaranteed to be constant on
a given one.

Add support for ARM7TDMI, as provided in a patch from John Fremlin to port-arm32.

Shouldn't effect any currently in tree ports.

Replace arm6_dataabt_fixup() and arm7_dataabt_fixup() with early_abort_fixup()
and late_abort_fixup(), based on the abort model in use, rather than the CPU
type.  This cleans up the code and makes it smaller.  Only tested on an
ARM6 -- I can't find my ARM710a card right now.

Initial cpufunc operations for ARM3.  Not actually used yet.

Catch up with -current.

Sync with HEAD.

file cpufunc.h was added on branch thorpej_scsipi on 2001-03-12 13:27:21 +0000

Create cpufunc_null_fixup() to replace all the CPU-specific abort-fixup
routines that did nothing.

Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.