CVS log for src/sys/arch/arm/include/cpu.h

Up to [cvs.NetBSD.org] / src / sys / arch / arm / include

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

Pull up following revision(s) (requested by maya in ticket #316):

	sys/arch/m68k/include/mutex.h: revision 1.13
	sys/arch/arm/include/cpu.h: revision 1.125
	sys/arch/sun68k/include/intr.h: revision 1.21
	sys/arch/arm/include/mutex.h: revision 1.28
	sys/sys/rwlock.h: revision 1.18
	sys/arch/powerpc/include/mutex.h: revision 1.7
	sys/arch/arm/include/mutex.h: revision 1.29
	sys/arch/powerpc/include/mutex.h: revision 1.8
	sys/uvm/uvm_param.h: revision 1.42
	sys/sys/ksem.h: revision 1.16
	sys/arch/x86/include/mutex.h: revision 1.10
	sys/sys/proc.h: revision 1.372
	sys/sys/ksem.h: revision 1.17
	sys/arch/ia64/include/mutex.h: revision 1.8
	sys/arch/evbarm/include/intr.h: revision 1.29
	sys/sys/lua.h: revision 1.9
	sys/arch/next68k/include/intr.h: revision 1.23
	sys/arch/ia64/include/mutex.h: revision 1.9
	sys/arch/hp300/include/intr.h: revision 1.35
	sys/arch/hp300/include/intr.h: revision 1.36
	sys/arch/sparc/include/cpu.h: revision 1.111
	sys/arch/hppa/include/mutex.h: revision 1.16
	sys/arch/vax/include/intr.h: revision 1.31
	sys/arch/hppa/include/mutex.h: revision 1.17
	sys/arch/news68k/include/intr.h: revision 1.28
	sys/arch/hppa/include/mutex.h: revision 1.18
	sys/arch/hppa/include/intr.h: revision 1.3
	sys/arch/hppa/include/mutex.h: revision 1.19
	sys/arch/hppa/include/intr.h: revision 1.4
	sys/sys/sched.h: revision 1.92
	sys/opencrypto/cryptodev.h: revision 1.51
	sys/arch/vax/include/mutex.h: revision 1.20
	sys/arch/sparc64/include/mutex.h: revision 1.10
	sys/arch/ia64/include/sapicvar.h: revision 1.2
	sys/arch/riscv/include/mutex.h: revision 1.5
	sys/arch/amiga/dev/grfabs_cc.c: revision 1.39
	sys/external/bsd/drm2/include/linux/idr.h: revision 1.11
	sys/arch/riscv/include/mutex.h: revision 1.6
	sys/ddb/files.ddb: revision 1.16
	sys/arch/mac68k/include/intr.h: revision 1.32
	share/man/man4/ddb.4: revision 1.203
	sys/ddb/db_command.c: revision 1.183
	sys/arch/mips/include/mutex.h: revision 1.10
	sys/ddb/db_command.c: revision 1.184
	sys/arch/x68k/include/intr.h: revision 1.22
	sys/arch/sparc/include/psl.h: revision 1.51
	sys/arch/or1k/include/mutex.h: revision 1.4
	sys/arch/mips/include/mutex.h: revision 1.11
	sys/arch/arm/xscale/pxa2x0_intr.h: revision 1.16
	sys/arch/sparc64/include/cpu.h: revision 1.134
	sys/arch/sparc/include/psl.h: revision 1.52
	sys/arch/or1k/include/mutex.h: revision 1.5
	sys/arch/mvme68k/include/intr.h: revision 1.22
	sys/arch/luna68k/include/intr.h: revision 1.16
	external/cddl/osnet/sys/sys/kcondvar.h: revision 1.6
	sys/arch/sparc/include/mutex.h: revision 1.12
	sys/arch/sparc/include/mutex.h: revision 1.13
	sys/arch/usermode/include/mutex.h: revision 1.5
	sys/arch/usermode/include/mutex.h: revision 1.6
	sys/kern/kern_core.c: revision 1.38
	usr.sbin/crash/Makefile: revision 1.49
	sys/arch/amiga/include/intr.h: revision 1.23
	sys/arch/alpha/include/mutex.h: revision 1.12
	sys/arch/alpha/include/mutex.h: revision 1.13
	sys/arch/evbarm/lubbock/sacc_obio.c: revision 1.16
	sys/ddb/ddb.h: revision 1.6
	sys/arch/sparc64/include/mutex.h: revision 1.8
	sys/arch/sh3/include/mutex.h: revision 1.12
	sys/arch/evbarm/lubbock/sacc_obio.c: revision 1.17
	sys/ddb/db_syncobj.c: revision 1.1
	sys/arch/vax/include/mutex.h: revision 1.18
	sys/arch/sparc64/include/psl.h: revision 1.63
	sys/arch/sparc64/include/mutex.h: revision 1.9
	sys/arch/sh3/include/mutex.h: revision 1.13
	sys/arch/evbarm/lubbock/obio.c: revision 1.13
	sys/arch/atari/include/intr.h: revision 1.23
	sys/ddb/db_syncobj.c: revision 1.2
	sys/arch/vax/include/mutex.h: revision 1.19
	sys/arch/evbarm/g42xxeb/obio.c: revision 1.14
	sys/arch/evbarm/g42xxeb/obio.c: revision 1.15
	sys/arch/cesfic/include/intr.h: revision 1.14
	sys/ddb/db_syncobj.h: revision 1.1
	sys/arch/x86/include/cpu.h: revision 1.134
	sys/arch/evbarm/g42xxeb/obio.c: revision 1.16
	sys/arch/cesfic/include/intr.h: revision 1.15
	sys/arch/arm/xscale/pxa2x0_intr.c: revision 1.26
	sys/sys/cpu_data.h: revision 1.54
	sys/arch/m68k/include/mutex.h: revision 1.12
	sys/arch/ia64/acpi/madt.c: revision 1.6

sys/rwlock.h: Make this more self-contained for bool.

machine/mutex.h: Sprinkle includes so this can be used by crash(8).

ddb: New `show all tstiles' command.
Shows who's waiting for which locks and what the owner is up to.

Include psl.h for ipl_cookie_t if __MUTEX_PRIVATE

sys: Rip <sys/resourcevar.h> out of <uvm/uvm_param.h>.

And thus out of <sys/param.h>, which is exceedingly overused and
fragile and delenda est.

Should fix (some) issues with the recent inclusion of machine/lock.h
in various machine/mutex.h files.

arm/mutex.h: Need machine/intr.h, machine/lock.h.

For ipl_cookie_t and __cpu_simple_lock_t.
evbarm/intr.h: Define ipl_cookie_t before including ARM_INTR_IMPL.

Otherwise arm/mutex.h doesn't work, due to a cyclic dependency which
should really be fixed.
opencrypto/cryptodev.h: Fix includes.
- Move sys/condvar.h under #ifdef _KERNEL.
- Add some other necessary includes and forward declarations.
- Sort.

hp300/intr.h: Fix missing includes.
linux/idr.h: Need <sys/mutex.h> for kmutex_t.
amiga/intr.h: Don't define spl*() functions if !_KERNEL.

This is used by crash(8) now, and what's important is ipl_cookie_t.
cesfic/intr.h: Expose ipl_cookie_t to userland for crash(8).
cesfic/intr.h: Expose ipl_cookie_t to userland only with _KMEMUSER.

Probably not necessary but let's be a little more cautious about
this.

atari/intr.h: Expose ipl_cookie_t with _KMEMUSER for crash(8).

arm/cpu.h: Need sys/param.h for COHERENCY_UNIT.

Nix machine/param.h -- not meant to be used directly, pulled in by
sys/param.h.

Move the definition of ipl_cookie_t out of the kernel-only sections,
some _KMEMUSER applications need it.

ddb: Cast pointer to uintptr_t first before db_expr_t.

hppa/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

luna68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

mvme68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

news68k/intr.h: Fix includes.  Put some definitions under _KERNEL.

next68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

sys/ksem.h: Hack around fstat(8) abuse of _KERNEL.

sun68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

vax/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).

x68k/intr.h: Put functions under _KERNEL so crash(8) can use this.

Make ipl_cookie_t visible for _KMEMUSER userland applications.

fix editor mishap in previous

Explicitly include <sys/mutex.h> for kmutex_t.

Replace kmutex_t * (which may be undefined here) with struct kmutex *,
suggested by Taylor.

hp300/intr.h: Put most of this under #ifdef _KERNEL.
Only ipl_cookie_t really needs to be exposed now, for crash(8).

mac68k/intr.h: Expose ipl_cookie_t to _KMEMUSER for crash(8).
Make inclusion of sys/intr.h explicit for spl*.

fix hppa and vax builds.

machine/lock.h isn't necessary for __cpu_simple_lock_t, it's in
sys/types.h.  avoids cpu_data.h vs sched.h include order issues.

move the hppa ipl_t typedef with the moved usage of it.
machine/mutex.h: Sprinkle sys/types.h, omit machine/lock.h.

Turns out machine/lock.h is not needed for __cpu_simple_lock_t, which
always comes from sys/types.h.  And, really, sys/types.h (or at least
sys/stdint.h) is needed for uintN_t and uintptr_t.

ddb: Cast pointer to uintptr_t, then to db_expr_t.
Avoids warnings about conversion between pointer and integer of
different size on some architectures.

re-fix hppa builds.

this file uses __cpu_simple_lock(), not just the underlying type,
so it does need machine/lock.h.

Break cycle by using `struct kmutex *' instead of `kmutex_t *'.
sys/sched.h included sys/mutex.h
which includes sys/intr.h
which includes machine/intr.h
which on cats includes arm/footbridge/footbridge_intr.h
which includes arm/cpu.h
which includes sys/cpu_data.h
which includes sys/sched.h

But there was never any real need for sys/mutex.h in sys/sched.h,
because it only uses pointers to the opaque struct kmutex.  Cycle
broken by using `struct kmutex *' instead of pulling in sys/mutex.h
for the definition of kmutex_t.

Side effect: This revealed that sys/cpu_data.h needed sys/intr.h
(which was pulled in accidentally by sys/mutex.h via sys/sched.h) for
SOFTINT_COUNT.  Also revealed some other machine/cpu.h header files
were missing includes of sys/mutex.h for kmutex_t.

ia64: Need sys/types.h for u_int, vaddr_t; sys/mutex.h for kmutex_t.

explicitly include no longer implicitly included sys/mutex.h.

arm/xscale: Use sys/bitops.h fls32 - 1 instead of 31 - __builtin_clz.
Sidesteps namespace collision with `#define bits ...' in net/zlib.c.

complete the previous - there were two calls to find_first_bit() to fix.

arm/xscale: Missed a spot with previous find_first_bit commit.

evbarm/g42xxeb: Fix off-by-one in previous.

The original find_first_bit(x) was 31 - __builtin_clz((uint32_t)x),
which is equivalent to fls32(x) - 1, not to fls32(x).

Note that fls32 is 1-based and returns 0 for x=0.

arm/cpu.h: Need sys/param.h for COHERENCY_UNIT.

Nix machine/param.h -- not meant to be used directly, pulled in by
sys/param.h.

G/C an unused struct cpu_info member

pic: Update ci_cpl in pic_set_priority callback.

Not all ICs need interrupts disabled to update the priority. DAIF accesses
are not cheap, so push the update of ci_cpl from pic_set_priority to the
IC's pic_set_priority callback, and let the IC driver determine whether
or not it needs interrupts disabled.

arm: Forward-declare `struct proc' before using in prototype.

Move arm_cache_info from cpufunc.h to cpu.h

Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
   diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3

Improved the performance of kernel profiling on MULTIPROCESSOR, and possible to get profiling data for each CPU.

In the current implementation, locks are acquired at the entrance of the mcount
internal function, so the higher the number of cores, the more lock conflict
occurs, making profiling performance in a MULTIPROCESSOR environment unusable
and slow. Profiling buffers has been changed to be reserved for each CPU,
improving profiling performance in MP by several to several dozen times.

- Eliminated cpu_simple_lock in mcount internal function, using per-CPU buffers.
- Add ci_gmon member to struct cpu_info of each MP arch.
- Add kern.profiling.percpu node in sysctl tree.
- Add new -c <cpuid> option to kgmon(8) to specify the cpuid, like openbsd.
  For compatibility, if the -c option is not specified, the entire system can be
  operated as before, and the -p option will get the total profiling data for
  all CPUs.

Re-apply

Move 'struct pic_pending' from percpu to struct cpu_info. Saves a few
instructions in splx.

There is(/was) no need to use atomic operations on the percpu / cpu_info
members, so don't.

Finally removng the use of percpu should help avoid problems with "late"
attaching cpus.

Sync with HEAD.

Sync with HEAD.

Revert recent pic optimizations until I have more time to work on this.

Keep current hardware priority value in struct cpu_info and use it instead
of reading icc_pmr_el1 in gicv3_set_priority.

Move 'struct pic_pending' from percpu to struct cpu_info. Saves a few
instructions in splx.

swap sys/param.h for machine/param.h.  this still obtains the
wanted COHERENCY_UNIT, while avoiding have a cascade of
failures where sys/mutex.h ends up including arm/cpu.h which
ends up including sys/resourcevar.h and then sys/mutex.h,
but as the first includer of sys/mutex.h has defined the
idempotent header define, the second one is empty, and as
kmutex_t isn't defined by the first attempt yet the kmutex_t
used in resourcevar.h generates an error.

should fix evbarm v5/v5eb, hpcarm, iyonix and zaurus builds.

tested building iyonix, zaurus and evbarmv7hf.

G/C MP_CPU_INFO_MEMBERS

Mirror the changes to aarch64 and

- Switch to TPIDRPRW_IS_CURLWP, because curlwp is accessed much more often
  by MI code.  It also makes curlwp preemption safe,

- Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs
  can see spurious ASTs (which doesn't cause a problem, it just means some
  time may be wasted).

- Make sure ASTs are always set on the same CPU as the target LWP, and
  delivered via IPI if posted from a remote CPU so that they are resolved
  quickly.

- Add some cache line padding to struct cpu_info.

- Add a memory barrier in a couple of places where ci_curlwp is set.  This
  is needed whenever an LWP that is resuming on the CPU could hold an
  adaptive mutex.  The barrier needs to drain the CPU's store buffer, so
  that the update to ci_curlwp becomes globally visible before the LWP can
  resume and call mutex_exit().

Implement fpu_kern_enter/leave for arm32.

Mostly merge changes from HEAD upto 20200411

Provide a curpcb

Don't expose curproc/curlwp and other random kernel macros/functions/variables
du-jour.

Sync with head.

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
  drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
  - a static cpu_info_store array
  - the same arm_cpu_{hatched,mbox}

Sync with head.

#ifdef whack-a-mole for the pmap_maxproc_set functionality

s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pages
change

Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by
creating a new pool l1ttpl for the userland L1 translation table which
needs to be 8KB and 8KB aligned.

Limit the pool to maxproc and add hooks to allow the sysctl changing of
maxproc to adjust the pool.

This comes at a 5% performance penalty for build.sh -j8 kernel on a
Tegra TK1.

Sync with head.

port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system.  tested
on rockpro64 and pinebook pro.

Fix false sharing problems with cpu_info.  Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
  the IPI bitmask and ci_want_resched.

mi_userret(): take care of calling preempt(), set spc_curpriority directly,
and remove MD code that does the same.

Pull up following revision(s) (requested by jmcneill in ticket #359):

	sys/arch/aarch64/aarch64/locore.S: revision 1.42
	sys/arch/aarch64/aarch64/locore.S: revision 1.43
	sys/arch/aarch64/aarch64/locore.S: revision 1.44
	sys/arch/arm/fdt/cpu_fdt.c: revision 1.28
	sys/arch/aarch64/include/cpu.h: revision 1.14
	sys/arch/aarch64/include/param.h: revision 1.12
	sys/arch/arm/arm32/cpu.c: revision 1.133
	sys/arch/arm/arm32/cpu.c: revision 1.134
	sys/arch/arm/include/cpu.h: revision 1.101
	sys/arch/arm/acpi/cpu_acpi.c: revision 1.7
	sys/arch/aarch64/aarch64/cpu.c: revision 1.23
	sys/arch/aarch64/aarch64/cpu.c: revision 1.24
	sys/arch/aarch64/aarch64/cpu.c: revision 1.25

Increase aarch64 MAXCPUS to 256.

 -

Invalidate dcache before polling AP hatched status

 -

Avoid overlap between BP and last AP stack. AP stacks are now in order of
increasing address order.

Spotted by and idea from mlelstv.

 -

Use separate cacheline aligned arrays for mbox and hatched as before.

 -

cpu_hatched_p only for MULTIPROCESSOR

Increase aarch64 MAXCPUS to 256.

Sync with HEAD

Synch with HEAD

Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)
to map MPIDRs to an index for each CPU.

Towards big.LITTLE support.

Sync with HEAD, resolve a couple of conflicts

Align struct cpu_info member names. NFC.

Sync with head

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors.  AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested.  Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

- Cleanup for dynamic sysctl:
  - Remove unused *_NAMES macros for sysctl.
  - Remove unused *_MAXID for sysctls.
- Move CTL_MACHDEP sysctl definitions for m68k into m68k/include/cpu.h and
  use them on all m68k machines.

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

Pull up following revision(s) (requested by skrll in ticket #566):
	sys/arch/arm/include/cpu.h: 1.94
	sys/arch/mips/include/cpu.h: 1.122
	sys/arch/powerpc/include/cpu.h: 1.103
	sys/sys/cpu.h: 1.42
CPU_INFO_FOREACH() must always iterate at least the boot cpu.
document this in sys/cpu.h and fix the arm and mips versions
to check ncpu is non zero before using it as an iterator max.
this should fix the new assert in init_main.c.
--
apply the same change for powerpc as mrg did for arm and mips:
CPU_INFO_FOREACH() must always iterate at least the boot cpu.
document this in sys/cpu.h and fix the arm and mips versions
to check ncpu is non zero before using it as an iterator max.
this should fix the new assert in init_main.c.

Remove port-acorn26

OK core@

CPU_INFO_FOREACH() must always iterate at least the boot cpu.
document this in sys/cpu.h and fix the arm and mips versions
to check ncpu is non zero before using it as an iterator max.

this should fix the new assert in init_main.c.

update from HEAD

Sync with HEAD

Sync with HEAD

Sync with HEAD

Fix rcs tag.

Expose correct cpu_number(), CPU_IS_PRIMARY() and CPU_INFO_FOREACH() for
modules so that the dtrace module works on an MP system.

Sync with HEAD

Trailing whitespace

Sync with HEAD

Make setsoftast take a cpu_info *

__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Make sure TPIDRPRw_IS_CURLWP is being used when __HAVE_PREEEMPTION is defined.

Add basic support for __HAVE_PREEMPTION.
Use atomic ops for ci_astpending if __HAVE_PREEMPTION is defined.

Add an agnostic version of curlwp and curcpu() for modules since they won't
know if the kernel was built with TPIDRPRW_IS_CUR{LWP,CPU} or not.

Sync with HEAD

Allow TPIDRPRW_IS_CURLWP to be used with MULTIPROCESSOR kernels

Pull up following revision(s) (requested by skrll in ticket #582):
	distrib/utils/embedded/conf/rpi.conf: revision 1.27
	etc/etc.evbarm/Makefile.inc: revision 1.70
	sys/arch/arm/broadcom/bcm2835_intr.c: revision 1.5-1.7
	sys/arch/arm/broadcom/bcm2835_obio.c: revision 1.23, 1.24
	sys/arch/arm/broadcom/bcm2835_space.c: revision 1.8
	sys/arch/arm/broadcom/bcm2835reg.h: revision 1.14
	sys/arch/arm/broadcom/bcm2835var.h: revision 1.2
	sys/arch/arm/broadcom/files.bcm2835: revision 1.24
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.30
	sys/arch/arm/cortex/armperiph.c: revision 1.8, 1.9
	sys/arch/arm/cortex/gtmr.c: revision 1.9
	sys/arch/arm/cortex/gtmr_var.h: revision 1.5
	sys/arch/arm/cortex/mpcore_var.h: revision 1.3
	sys/arch/arm/include/cpu.h: revision 1.84
	sys/arch/evbarm/conf/RPI2: revision 1.1, 1.2
	sys/arch/evbarm/conf/RPI2_INSTALL: revision 1.1
	sys/arch/evbarm/conf/RPI: revision 1.59, 1.60
	sys/arch/evbarm/conf/mk.rpi: revision 1.4
	sys/arch/evbarm/conf/std.rpi: revisions 1.16-1.19 via patch
	sys/arch/evbarm/rpi/genassym.cf: revision 1.2
	sys/arch/evbarm/rpi/rpi.h: revision 1.4
	sys/arch/evbarm/rpi/rpi2_start.S: revision 1.1
	sys/arch/evbarm/rpi/rpi_machdep.c: revision 1.57, 1.58 via patch
	sys/arch/evbarm/rpi/rpi_start.S: revision 1.13
Move some options into std.rpi
--
Add __HAVE_MM_MD_CACHE_ALIASING
Pull up following revision(s) (requested by skrll in ticket #582):
Fix TPIDRPRW_IS_CURLWP builds.
--
A MULTIPROCESSOR kernel requires TPIDRPRW_IS_CURCPU.
--
Use TPIDRPRW_IS_CURLWP as it's a slight code reduction and performance
improvement.
Initial RPI2 support - it doesn't work yet. The generic timer gets messed
up somehow.
This commit changes the KVA layout of the RPI.
--
Make this compile where gtmr isn't used.
--
Spin up the non-boot CPUs, but don't allow cpu_boot_secondary_processors
to see them for now.
RPI2 nows works well with only the boot cpu.
--
Appease a KASSERT - will be remove when MULTIPROCESSOR RPI2 is fixed.
--
Add RPI2 to kernels build for both earmv[67].
Use the earmv6 built kernels to create an image that can be used on both
RPI and RPI2
--
Add an RPI2_INSTALL

Fix TPIDRPRW_IS_CURLWP builds.

A MULTIPROCESSOR kernel requires TPIDRPRW_IS_CURCPU.

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Make ddb_regs, undefined & vfp evcnt's per cpu.

Move some static/global variables to here.

Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.

use cii

sync with head

Fix CLKF_INTR for EABI to (void) its argument so it isn't mark unused by the
optimizer.

<arm/locore.h> fallout (fixes some include ordering errors)

If _KMEMUSER, include <sys/intr.h>

There are only 16 faults.

Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

resync with head

Add a machdep.fpu_present sysctl for ld.elf_so to use in ld.so.conf to load
libc_vfp.so.

sync with head

Add vfp_kernel_acquire and vfp_kernel_release prototypes.

Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.

sync with head

Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

Don't use locations in .data to store exception temporaries, use decidicated
space in cpu_info instead.  This also moves undefined_handler_address into
cpu_info as well.
Use the new armreg* inlines for getting TPIDRPRW register.
Add MULTIPROCESSOR version of CPU_INFO_FOREACH

Remove undeeded struct device;

Use new armv7 CP15 register to print out cache types.
If the cpu_cc_freq is set, report it.
Add macros to make inlines for reading/writing co-processor registers.

Rename ARM options PROCESS_ID_IS_CUR{CPU,LWP} to TPIDRPRW_IS_CUR{CPU,LWP}
since TPIDRPRW is the cp15 register name.
Initialize it early in start along with CI_ARM_CPUID.
Remove other initializations.
We alays have ci_curlwp.
Enable TIPRPRW_IS_CURCPU in std.beagle.
[tested on a beaglboard (cortex-a8)]

small rototill.
pcb_flags is dead.  PCB_NOALIGNFLT is now in stored l_md.md_flags as
MDLWP_NOALIGNFLT.  This avoids a few loads of the PCB in exception handling.
pcb_tf has been moved to l_md.md_tf.  Again this avoids a lot of pcb
references just to access or set this.  It also means that pcb doesn't
need to accessed by MI code.
Move pcb_onfault to after the pcb union.
Add pcb_sp macro to make code prettier.
Add lwp_settrapframe(l, tf) to set the l_md.md_tf field.
Use lwp_trapframe to access it (was process_frame but that name was changed
in a previous commit).
Kill off curpcb in acorn26.
Kill the checks for curlwp being NULL.
Move TRAP_USERMODE from arm32/fault.c to frame.h and a __PROG26 version.
Replace tests for usermode with that macro.

Kill curpcb/ci_curpcb.  Use device_t in cpu_info.
Add ci_softc (where ci_curpcb was so cpu_info doesn't change).

Rework VFP support to use PCU.
Add emulation of instruction which save/restore the VFP FPSCR.
Add a sysarch hook to VFP FPSCR manipulation.

[The emulation will be used by libc to store/fetch exception modes and
rounding mode on a per-thread basis.]

Pull up revisions:
  src/sys/arch/evbarm/dev/plcomreg.h revisions 1.2,1.3,1.4
  src/sys/arch/evbarm/conf/INTEGRATOR revision 1.65
  src/sys/arch/evbarm/dev/plcom.c revisions 1.34,1.35,1.36,1.37,1.38,1.39,1.40
  src/sys/arch/evbarm/ifpga/plcom_ifpga.c revisions 1.12,1.13,1.14
  src/sys/arch/evbarm/dev/plcomvar.h revisions 1.9,1.10,1.11
  src/sys/arch/evbarm/ifpga/plcom_ifpgavar.h revision 1.2
  src/sys/arch/arm/arm/cpufunc.c revisions 1.105,1.108
  src/sys/arch/arm/arm32/cpu.c revision 1.79
  src/sys/arch/arm/include/armreg.h revisions 1.49,1.54
  src/sys/arch/arm/arm32/pmap.c revision 1.229
  src/sys/arch/arm/arm32/arm32_machdep.c revision 1.77
  src/sys/arch/arm/include/cpu.h revision 1.64
  src/sys/arch/arm/arm/cpufunc_asm_arm1136.S revision 1.3
  src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S revision 1.1
  src/sys/arch/arm/conf/files.arm revision 1.106
  src/sys/arch/arm/include/cpufunc.h revision 1.57
  src/sys/dev/sdmmc/sdhc.c revisions 1.14,1.24
  src/sys/dev/sdmmc/sdhcvar.h revisions 1.7,1.8
  src/sys/arch/evbarm/ifpga/ifpgareg.h revision 1.4
  src/sys/arch/evbarm/integrator/integrator_machdep.c revision 1.69
  src/sys/arch/arm/broadcom/bcm2835_dma.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_emmc.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_intr.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_intr.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_obio.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_plcom.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_pm.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_pmvar.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_space.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_tmr.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835reg.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835var.h revision 1.1
  src/sys/arch/arm/broadcom/bcm_amba.h revision 1.1
  src/sys/arch/arm/broadcom/files.bcm2835 revision 1.1
  src/sys/arch/evbarm/Makefile revision 1.9
  src/sys/arch/evbarm/conf/RPI revision 1.1
  src/sys/arch/evbarm/conf/files.rpi revision 1.1
  src/sys/arch/evbarm/conf/mk.rpi revision 1.1
  src/sys/arch/evbarm/conf/std.rpi revision 1.1
  src/sys/arch/evbarm/rpi/genassym.cf revision 1.1
  src/sys/arch/evbarm/rpi/rpi.h revision 1.1
  src/sys/arch/evbarm/rpi/rpi_machdep.c revision 1.1
  src/sys/arch/evbarm/rpi/rpi_start.S revision 1.1,1.2
  src/etc/etc.evbarm/Makefile.inc revision 1.28
(requested by skrll in ticket #454).

don't mix #define<TAB> and #define<SPACE> in a file.

avoid warning with options PLCOM_DEBUG for INTEGRATOR.

Rename register values. No functional change - same code before and after.

Existing names are prefixed with PL01X_ where they're common between the
PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're
found only on the respective chips.

Replace the simple_lock with a kmutex_t.  Update the locking to match
com(4) in the few places it didn't already.

DOH.  Replace a line that got accidently deleted in the last commit.

device_t/softc split
struct device * -> device_t
struct cfdata * -> cfdata_t

Add the 'Z' to the 1176 cpu product name.

ok matt@

Fix locking botch introduced in 1.36.

Fix a KASSERT. From/OK'ed by matt@

Fix racy softint dispatch that lead to KASSERT(si->si_active) in
softint_execute

Discussed with matt@. "Looks good to me"

Add the documented ARM11[37]6 Auxiliary control register defines.

Add support for the ARM1176JZS

Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that).

Provide a method for attachments to specify capabilites.

Add support for the PL011 to plcom. Pull across a bunch of fixes from
com(4) while I'm here and do some other tidyup.

Tested on a RaspberryPi.

PL010 not tested.

Initial commit of support for the RaspberryPI (www.raspberrypi.org)

This is enough for serial console via the gpio header pins and to get to
multiuser.

A huge thank you to Matt Thomas for all his help.

Add RPI to KERNEL_SETS

Remove #if 0 code.

Remove irqframe and replace with identical trapframe.

Fix racy softint dispatch that lead to KASSERT(si->si_active) in
softint_execute

Discussed with matt@. "Looks good to me"

sync with head

merge to -current.

expose cpu structures to kmemuser and prevent opt_*.h from being included
if kmemuser

sync with head

Include sys/device_if.h instead of sys/device.h.  machine/cpu.h is
one of the lower-most definitions.  Relying on the huge sys/device.h
is not a good idea.

Include sys/evcnt.h for struct evcnt.

Sync with HEAD.

sync with head.

implement ucas_* for arm.

sync with head

Rename L_ADDR to L_PCB and amend some comments accordingly.

Use lwp_getpcb() on ARM (and acorn26/32), clean from struct user usage.

sync with head.

Sync with HEAD.

Define a version of GET_CURCPU, GET_CURLWP, and GET_CURPCB for use on
old uniprocessor ARMs, and re-arrange the ifdefs so that it gets
used on 26-bit systems as well.  This allows us to uniformly use these
macros everywhere.

Sync with HEAD.

Sync with HEAD.

Sync with wrstuden-revivesa-base-2.

Only call dosoftints() is ci_intr_depth == 0

Do fast softint processing in DO_AST_AND_RESTORE_ALIGNMENT_FAULTS.
Redo the softint mask so ci_softints >> ci_cpl != 0 becomes an easy
test for work to be done.

Sync with HEAD.

sync with head.

sync with head.

Merge kernel changes in matt-armv6 to HEAD.

Sync with HEAD.

sync with head.

sync with HEAD

Sync with head.

sync with head.

VFP support.

Sync with HEAD.

Remove CTL_MACHDEP_NAMES, it's not used anywhere.

Ok by martin@.

revert previous; as yamt pointed out, these bits are in <sys/cpu.h>.

cargo-cult CPU_INFOITERATOR and _FOREACH to make kern_prf.c build again.
These should probably be abstracted out to sys/cpu.h at some point, since
they don't really change from arch to arch.

Sync with HEAD.

Fix acorn32 to boot.  Also fix cpu.h, a change sneaked in that isn't
currently being used.

Add initial reworking of acorn32 to use new interrupt code.

Note that cats probably won't work currently as acorn32 changed the way
that the pic is registered, it has to provide the irq lines as on acorn32
we attach the iomd after we need to register irqs for the pioc.  So we
setup the irqs for iomd before malloc etc are available.  This needs
to be fixed.

More work is still needed to update most of the podulebus drivers.
First I need to add podulebus wrapper for interrupts that handles the
maskaddr and maskbits.   Exposing them to the common irq code is wrong.

Add fast softint switching support.

sync with head

Sync to HEAD.

sync with HEAD

Sync with HEAD

current_intr_depth is dead.  Make sure we don't use it anymore.

Sync with HEAD.

Sync with HEAD.

Sync with head.

Sync with HEAD

sync with head.

Add cpu_intr_p().

Make all the evbarm kernels build again.  Fix lossage from rebase.

sync with HEAD

sync with head.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Sync with head.

Sync with HEAD.

sync with head.

Sync with HEAD

Sync with HEAD.

Sync with HEAD.

Make want_resched a member of cpu_info.

Make sure we won't set NULL curlwp.

sync with head.

If we are doing PROCESS_ID_IS_CURLWP, we don't need a ci_curlwp.

Move curpcb, curlwp, astpending, want_resched, current_spl_level,
and current_intr_depth to cpu_info.
Add support for storing either curlwp or curcpu in the ARMv6
supervisor process/thread id coprocessor register.
Add LWP0_CPU_INFO to store location of static cpu_info for lwp0 static
initialization.
Use cpsi[ed] on ARMv6.

Sync with HEAD.

Sync with HEAD.

Initial check-in of reworked arm interrupt routines.

Main things to note on this branch:
* spl routines are inlined, less complex, and small (kernel drops in size)
* interrupts are handled in priority order (for most things it doesn't
  matter, but pending ipls are used to determine if there is any work to do)
* arm_irqhandler.c is derived from footbridge_irqhandler.c, which was based
  on work by thorpej.
* The code tries to touch hardware as little as possible.
* spl masks are no longer tracked, as the system is based on pending ipls

The shared code uses global ipl lists to track which interrupt handlers
are attached to which ipl (arm_iplq[]).

Interrupt sources register with the common code to indicate:
* how many irq lines they have
* a function to set the hardware mask.
* call arm_intr_claim and arm_intr_disestablish to setup handlers

When an interrupt occurs the ipl is flagged as pending, in ipls_pending.
If it can be handled at the current_ipl_level the code does so.
If it can't be handled it's left until the current_ipl_level drops.

As the ipl level changes down a quick test is made of the new ipl level
against the ipls_pending value.  If an ipl is pending arm_intr_splx_lifter
is called to handle the pending ipls.

It should be noted that all interrupts are left enabled at the hardware
level, interrupts are only masked when they occur.  They are only
re-enabled after it's interrupt handler is called.  Hardware masks are not
changed at any other time.

Soft interrupts are treated the same as hardware interrupts, they
register as a provider, and do not get treated specially.  All the soft
interrupt handlers are placed onto the relevant global ipl queue, the same
as hard interrupts handlers.

At the moment only footbridge within a cats has been updated to use the new
handling.

Todo:
* change the handling of interrupts, so that the hardware doesn't register
  a routine to fetch the hardware status.  Instead is makes a call which
  provides the mask.  This removes the primary flag when registering an
  interrupt provider.  It also makes more sense with multiple interrupt
  sources.
* Arm v5 has the clz asm, which could be used instead of the carefully
  hand rolled arm_intr_fls function.
* switch cats isa support to use this framework.
* switch iomd and acorn32 to use this framework.
* switch shark to use this framework.
* port any other arm platforms that are interested
* examine overlaps between this code and ppcoea-renovation branch.
* add support for different trigger types (Edge, level, pulse, etc)

(note that iomd and shark currently touch hardware on every spl change,
hence why they're targets to port)

Sync with HEAD.

Sync with HEAD.

Add ci_cpuid where it's missing.

Sync with head.

Sync with HEAD.

Sync with head.

Another missed changed for acorn26 idlelwp. Provide IRQenable/IRQdisable
macros.

Sync with head.

Update to HEAD.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

Convert to the new atomic ops API.

Set curlwp in cpu_switchto and provide a cpu_did_resched.

Who is copying who now?

Adapt arm32. Thanks to scw for helping out.

Tested on my cats (SA1)

XXX hydra should die. i've made some changes, but no guarantees.

- sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.

sync with head.

Changes for newlock2.

Remove spllowersoftclock() and CLKF_BASEPRI(), and always dispatch callouts
via a soft interrupt. In the near future, softclock will be run from process
context.

sync with head.

sync with head

sync with head

Centralize the various checks for validity of a CPU context in one macro,
so we don't have to get it right in lots of different places.

sync with head.

Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.

Sync with head.

sync with head - hopefully this will work

sync with head

Don't define, just declare want_resched here.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

Change all archs that did:

#define clockframe somethingelse

to:

struct clockframe {
	struct somethingelse cf_se;
};

and change access macros accordingly.

That means that, at least for that very issue, things will not go
ka-boomy if you don't have the actual definition of struct clockframe
before including systm.h.

Sync with HEAD.

move some per-cpu data definitions to MI place so that they can be modified
without touching all ports.  discussed on tech-kern@.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Rearrange process exit path to avoid need to free resources from different
process context ('reaper').

From within the exiting process context:
* deactivate pmap and free vmspace while we can still block
* introduce MD cpu_lwp_free() - this cleans all MD-specific context (such
  as FPU state), and is the last potentially blocking operation;
  all of cpu_wait(), and most of cpu_exit(), is now folded into cpu_lwp_free()
* process is now immediatelly marked as zombie and made available for pickup
  by parent; the remaining last lwp continues the exit as fully detached
* MI (rather than MD) code bumps uvmexp.swtch, cpu_exit() is now same
  for both 'process' and 'lwp' exit

uvm_lwp_exit() is modified to never block; the u-area memory is now
always just linked to the list of available u-areas. Introduce (blocking)
uvm_uarea_drain(), which is called to release the excessive u-area memory;
this is called by parent within wait4(), or by pagedaemon on memory shortage.
uvm_uarea_free() is now private function within uvm_glue.c.

MD process/lwp exit code now always calls lwp_exit2() immediatelly after
switching away from the exiting lwp.

g/c now unneeded routines and variables, including the reaper kernel thread

Make sure to include opt_foo.h if a defflag option FOO is used.

Merge the nathanw_sa branch.

Copy/initialize PMC state in cpu_proc_fork().

Catch up to -current.

It appears that MI code requires ci_cpuid to be the CPU number of the CPU
in question, whereas the ARM code was using it to hold the model
identification.  To fix this, rename:

ci_cpuid -> ci_arm_cpuid
ci_cputype -> ci_arm_cputype (for consistency)
ci_cpurev -> ci_arm_cpurev (ditto)
ci_cpunum -> ci_cpuid

This makes top(1) give correct CPU numbers in its "STATE" column (all 0 for
now).

Remember the location of each CPU's idle PCB in struct cpu_info.
Move allocation of the idle PCB from hydra.c to cpu.c and add some
extra initialisation from cpu_fork().

Minimal changes to allow a kernel with "options MULTIPROCESSOR" to compile
and boot multi-user on a single-processor machine.  Many of these changes
are wildly inappropriate for actual multi-processor operation, and correcting
this will be my next task.

sync kqueue branch with HEAD

catch up with -current.

Partial (ARM only) sync with trunk -- significant performance improvements
for XScale-based systems.

* Add a new machdep.powersave sysctl, which controls the use of
  the CPU's "sleep" function in the idle loop.
* Default all CPUs to not use powersave, except for the PDA processors
  (SA11x0 and PXA2x0).

This significantly reduces inteterrupt latency in high-performance
applications (and was good to squeeze another ~10% out of an XScale
IOP on a Gig-E benchmark).

Inline SetCPSR calls where it seems prudent to do so.  This avoids two
branches and allows the compiler to better utilize registers around
calls to disable/enable/restore_interrupts().

catch up with -current on kqueue branch

Catch up to -current.

Hard-wire CLKF_BASEPRI() to 0 on the ARM, since spllowersoftclock() might
not actually be able to unblock the interrupt, which would cause us
to run the softclock interrupts with hardclock blocked.

Per discussion w/ Charles Hannum.

Catch up to -current.

Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel.  What
  you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
  on which ARM architecture versions are configured (based on CPU_*
  options).  Also defines ARM_NARCH to determins how many architecture
  versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
  which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
  to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.

Clean up handling of the vector page on 32-bit ARM systems:
* Don't refer to VA 0, instead refer to a new variable: vector_page
* Delete the old zero_page_*() functions, replacing them with a new
  one: vector_page_setprot().
* When manipulating vector page mappings in user pmaps, only do so if
  the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the
  vector page is mapped by the kernel pmap).
* Add a new function, arm32_vector_init(), which takes the virtual
  address of the vector page (which MUST be valid when the function
  is called) and a bitmask of vectors the kernel is going to take
  over, and performs all vector page initialization, including setting
  the V bit in the CPU Control register ("relocate vectors to high
  address"), if necessary.

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

Cache the cpu type and cpu revision in cpu_info.

arm26->acorn26 transition.

Catch up with -current.

Add a ci_dev element to struct cpu_info, pointing to the device that
corresponds to the CPU.

Replace cpu_id and cpu_ctrl in struct _cpu with ci_cpuid and ci_ctrl in
struct cpu_info.  Also kill the cpuctrl global while we're here, and make
identify_arm_cpu() take a struct cpu_info * as an argument alongside the CPU
number.

Move arm700bugcount into stuct cpu_info, and attach it in
identify_master_cpu().

Catch up to -current.

Sync w/ -current.

Some prototype cleanup.

Sync kqueue branch with -current.

Catch up to -current.

Merge ast() and userret() between arm32 and arm26.  The implementation used
is the arm32 one.

Add a cpu_proc_fork(), called from uvm_proc_fork(), which takes care
of machine-dependent handling a fork() time (this is different from
forking the actual context in an LWP world).  #define it away on
platforms which do not need it.

Problem noted by Gregory McGarry.

Add 26-bit and 32-bit types.h files, which indicate the programming
model in use for a given platform (__PROG26 vs __PROG32), then pulls
in <arm/types.h>.  Change each ARM port to pull in <arm/arm26/types.h>
or <arm/arm32/types.h> as appropriate.  Change all references to PROG26
and PROG32 to __PROG26 and __PROG32.  Eliminate the opt_progmode.h
header file.

Machine-dependent kernel mods for scheduler activations on
26-bit ARM processors.  Kernel builds, but I have no 26-bit
ARM with which I can test, at the moment.

PROC_PC -> LWP_PC

Machine-dependent kernel mods for scheduler activations on
32-bit ARM processors.  Kernel boots multi-user on an XScale,
but upcalls not yet tested.

Sync the thorpej-mips-cache branch with -current.

file cpu.h was added on branch nathanw_sa on 2001-11-15 06:39:22 +0000

Implement a badaddr_read() routine which performs a load of the
specified size for the caller, and returns true or false indicating
whether or not a Data Abort occurred (i.e. the address was "bad").

update to -current

Purge CPU_ARM7500.  Thanks to Reinoud's work, it's no longer needed.

Initial commit for merging A7000/NC with the RISCPC in order to get _one_
bootable GENERAL kernel for the 3 machines.

This is done by integrating the ARM7500 in a better way. In various places
the IOMD ID is checked and action is taken at runtime compared to
compiletime.

The small piece of assembler that is changed now uses the flag
`arm7500_ioc_found' that is set up by iomd.c at startup. When this chip
isnt found at startup it will skip reading the ARM7500 extended IRQ
registers and wont clear them either.

The next step will be getting the mode-definition files to the bootloader.
Currently they are compiled in.

Catch up to -current.

Don't need to prototype child_return() here, it's in <sys/proc.h>.

strstr() is no longer used in the kernel.  G/C it.

Rather large overhaul.  Mostly cosmetic, but also:

Provide PROC_PC on arm26.
Provide working CLKF_INTR on arm26.
Make setsoftast a macro everywhere.

Sync with HEAD.

Split cpu from mainbus so that cpu can attached to other buses (like ofbus).

Sync with HEAD.

file cpu.h was added on branch thorpej_scsipi on 2001-03-12 13:27:21 +0000

PCB convergence, part the first:
Move the pointer to the current user trapframe from struct mdproc to struct
pcb (as on arm26).  Only tested by compiling kernels on arm32 and
hpcarm (dnard seems to be incomplete anyway).  Someone should try running one.

Large overhaul for arm26 compatibility.  This file is now even more of a mess
than it was.

Tidy up ARM7500 restrictions.
Also insist on precisely one of PROG32 and PROG26's being turned on.

cpu_number() macro has no args

Rollback of patch ... there was a bug in the proc.h

Due to changes in ../sys/proc.h ``cpu_wait(p)'' is now a function due to the
prototype defined it in ... added it to arm/vm_machdep.c since all ARM machines
are still single processor anyway

Move arm32 ports over to using <arm/armreg.h>, so <cpu.h> mostly contains
NetBSD-specific definitions.

This also entails some changes to the way CPU identification is done.  I hope
I've got it right.

COPY_SIGCODE is never referenced in the kernel, and the comment attached to it
is out of date. Assume it's obsolete and g/c it.

Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.