src/sys/arch/arm/include/arm32/pmap.h - diff

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version 1.10.2.7, 2002/06/23 17:34:51

version 1.10.2.8, 2002/09/06 08:32:41

Line 159 typedef struct pv_addr {

#define PVF_REF 0x02 /* page is referenced */

#define PVF_WIRED 0x04 /* mapping is wired */

#define PVF_WRITE 0x08 /* mapping is writable */

#define PVF_NC 0x10 /* mapping is non-cacheable */

#define PVF_EXEC 0x10 /* mapping is executable */

#define PVF_NC 0x20 /* mapping is non-cacheable */

* Commonly referenced structures

Line 222 extern vaddr_t pmap_curmaxkvaddr;

Line 223 extern vaddr_t pmap_curmaxkvaddr;

* Useful macros and constants

* While the ARM MMU's L1 descriptors describe a 1M "section", each

* one pointing to a 1K L2 table, NetBSD's VM system allocates the

* page tables in 4K chunks, and thus we describe 4M "super sections".

* We'll lift terminology from another architecture and refer to this as

* the "page directory" size.

#define PD_SIZE (L1_S_SIZE * 4) /* 4M */

#define PD_OFFSET (PD_SIZE - 1)

#define PD_FRAME (~PD_OFFSET)

#define PD_SHIFT 22

/* Virtual address to page table entry */

#define vtopte(va) \

(((pt_entry_t *)PTE_BASE) + arm_btop((vaddr_t) (va)))

Line 230 extern vaddr_t pmap_curmaxkvaddr;

Line 244 extern vaddr_t pmap_curmaxkvaddr;

#define vtophys(va) \

((*vtopte(va) & L2_S_FRAME) | ((vaddr_t) (va) & L2_S_OFFSET))

#define PTE_SYNC(pte) \

cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t))

#define PTE_FLUSH(pte) \

cpu_dcache_wbinv_range((vaddr_t)(pte), sizeof(pt_entry_t))

#define PTE_SYNC_RANGE(pte, cnt) \

cpu_dcache_wb_range((vaddr_t)(pte), (cnt) << 2) /* * sizeof(...) */

#define PTE_FLUSH_RANGE(pte) \

cpu_dcache_wbinv_range((vaddr_t)(pte), (cnt) << 2) /* * sizeof(...) */

#define l1pte_valid(pde) ((pde) != 0)

#define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S)

#define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C)