CVS log for src/sys/arch/arm/include/arm32/pmap.h

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Pull up following revision(s) (requested by skrll in ticket #411):

	sys/arch/evbarm/nslu2/nslu2_machdep.c: revision 1.41
	sys/arch/evbarm/gumstix/gumstix_machdep.c: revision 1.75
	sys/arch/evbarm/iq80321/iq80321_machdep.c: revision 1.66
	sys/arch/iyonix/iyonix/iyonix_machdep.c: revision 1.34
	sys/arch/zaurus/zaurus/machdep.c: revision 1.52
	sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c: revision 1.41
	sys/arch/hpcarm/hpcarm/pxa2x0_hpc_machdep.c: revision 1.33
	sys/arch/evbarm/iq80310/iq80310_machdep.c: revision 1.96
	sys/arch/evbarm/adi_brh/brh_machdep.c: revision 1.53
	sys/arch/arm/include/arm32/pmap.h: revision 1.177
	sys/arch/evbarm/viper/viper_machdep.c: revision 1.34
	sys/arch/evbarm/iyonix/iyonix_machdep.c: revision 1.5
	sys/arch/evbarm/npwr_fc/npwr_fc_machdep.c: revision 1.30
	sys/arch/evbarm/hdl_g/hdlg_machdep.c: revision 1.35
	sys/arch/arm/arm32/pmap.c: revision 1.440
	sys/arch/evbarm/lubbock/lubbock_machdep.c: revision 1.45
	sys/arch/evbarm/ixdp425/ixdp425_machdep.c: revision 1.47

Fix non-DIAGNOSTIC builds

Fix non-DIAGNOSTIC builds

No need to define cpu_{,set}_tlb_info here - just use the
sys/uvm/pmap/pmap_tlb.h versions.

Fix DEVMAP_FLAGS, patch from Nick.

Provide a shared pmap_devmap implementation and convert all pmap_devmap
arrays to use DEVMAP_ENTRY{,_END}

Update to support EFI runtime outside the kernel virtual address space
by creating an EFI RT pmap that can be activated / deactivated when
required.

Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines.

On Arm64 the usage of pmapboot_enter is reduced and the mappings are
created much later in the boot process -- now in cpu_startup_hook.
Backward compatiblity for KVA mapped RT from old bootaa64.efi is
maintained.

Adding support to other platforms should be easier as a result.

Remove unnecessary brackets

pm_remove_all is a shared field so move it out the #ifdefs

Sync with HEAD.

Provide pte_{value,valid_p}

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Consistency...#define<tab>

Sync with HEAD

Sync with HEAD

PMAP_DEBUG has been deleted on arm

Merge changes from current as of 20200406

Don't define pt_entry_t if _LOCORE

Reported by Patrick Welche

Provide a pt_entry_t and PRIxPTE

pmap_remove_all(): Return a boolean value to indicate the behaviour.  If
true, all mappings have been removed, the pmap is totally cleared out, and
UVM can then avoid doing the work to call pmap_remove() for each map entry.
If false, either nothing has been done, or some helpful arch-specific voodoo
has taken place.

Sync with head.

Pull up following revision(s) (requested by skrll in ticket #742):

	sys/arch/arm/arm32/pmap.c: revision 1.388
	sys/arch/arm/arm32/armv7_generic_space.c: revision 1.11
	sys/arch/arm/arm/cpufunc.c: revision 1.176
	sys/arch/arm/conf/Makefile.arm: revision 1.54 (via patch)
	sys/arch/arm/include/arm32/pmap.h: revision 1.161

Fix the armv[67] memory attributes for uncached memory.  Previously it was
mapped as strongly-ordered which meant that unaligned accesses would fault.
armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO
bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get
mapped to the correct memory attribute bits for armv[67]

DEVMAP_ENTRY usees a new flag PTE_DEV.

The workaround for the unaligned access faults is now removed.
XXX Other armv[67] boards bus_space implementations should be checked.
XXX There is scope to reduce the difference to aarch64

Adjust for UVM locking changes

G/C l1pte_pgindex

Fix the armv[67] memory attributes for uncached memory.  Previously it was
mapped as strongly-ordered which meant that unaligned accesses would fault.

armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO

bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get
mapped to the correct memory attribute bits for armv[67]

DEVMAP_ENTRY usees a new flag PTE_DEV.

The workaround for the unaligned access faults is now removed.

XXX Other armv[67] boards bus_space implementations should be checked.
XXX There is scope to reduce the difference to aarch64

Sync with head.

s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pages
change

Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by
creating a new pool l1ttpl for the userland L1 translation table which
needs to be 8KB and 8KB aligned.

Limit the pool to maxproc and add hooks to allow the sysctl changing of
maxproc to adjust the pool.

This comes at a 5% performance penalty for build.sh -j8 kernel on a
Tegra TK1.

Sync with head.

fix -Wsign-compare because module tests trigger it.

pg->phys_addr -> VM_PAGE_TO_PHYS(pg)

Sync with HEAD

Sync with head

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors.  AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested.  Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

Remove port-acorn26

OK core@

update from HEAD

Centralise defines for DEVMAP_{ALIGN,SIZE,ENTRY,ENTRY_END}

Revert the *_PROT_RO_* define changes and do all the work in the *_PROT()
macros for RO kernel pages.

cats boots again - no idea how it slipped through my testing previously

Sync with HEAD

Fix up L{1_S,2_L,2_S}_PROT for recent changes to the
L{1_S,2_L,2_S}_PROT_RO* values.

KNF two comments

Re-define the L*_PROT_RO for MMUs that don't really support RO mapping
and adjust l2pte_set_{writeable,readony} to the new values.

This allows RO mappings for MMUs that actually support them.

Trailing whitespace

Use the define name PMAP_HWPAGEWALKER and not PMAP_TLB_HWPAGEWALKER

Spell ARM_MMU_EXTENDED correctly

Sync with HEAD

Sync with HEAD

Sync with netbsd-7-1-RELEASE

Pull up following revision(s) (requested by skrll in ticket #1366):
	sys/arch/arm/include/arm32/pmap.h: 1.145
	sys/arch/arm/arm32/pmap.c: 1.343, 1.344
	sys/arch/evbarm/gumstix/gumstix_machdep.c: 1.58 via patch
Fixup the compile time decisions around PMAP_{INCLUDE,NEEDS}_PTE_SYNC and
fix the options for xscale boards which require the code in
pmap_l2ptp_ctor marked as #ifndef PMAP_INCLUDE_PTE_SYNC.
Fix the typo (pte -> opte) in this code block and consistently use opte
elsewhere.
PR/51990: Regression data_abort_handler: data_aborts fsr=0x406 far=0xbfffeff5  on copyout in init
--
fix unused.
--
Set xscale_cache_clean_addr appropriately and re-arrange default KVA
layout to allow direct map for all boards.
OVERO/DUOVERO/PEPPER aren't tested.
PR/52010: Regression: Gumstix Verdex is hanging in enabling cache + KASSERT ram_size

Fixup the compile time decisions around PMAP_{INCLUDE,NEEDS}_PTE_SYNC and
fix the options for xscale boards which require the code in
pmap_l2ptp_ctor marked as #ifndef PMAP_INCLUDE_PTE_SYNC.

Fix the typo (pte -> opte) in this code block and consistently use opte
elsewhere.

PR/51990: Regression data_abort_handler: data_aborts fsr=0x406 far=0xbfffeff5  on copyout in init

Sync with HEAD

Spell PMAP_TLB_NEED_SHOOTDOWN correctly

Sync with HEAD (as of 26th Dec)

Support pmap_pv_track and friends

Sync with HEAD

Make L2_S_CACHE_MASK_armv6n consistent with other *_CACHE_MASK_armv6n

Sync with HEAD

pmap_directbase is a failed experiment, nuke it.

Support directmapped systems with >1GB that start memory at 0x80000000.

Pull up following revision(s) (requested by skrll in ticket #805):
	sys/arch/arm/include/arm32/pmap.h: revision 1.138
	sys/arch/arm/arm/cpufunc.c: revision 1.151
	sys/arch/arm/arm32/bus_dma.c: revision 1.90
	sys/arch/arm/broadcom/bcm53xx_pax.c: revision 1.14
	sys/arch/arm/arm32/bus_dma.c: revision 1.91
	sys/arch/arm/samsung/exynos_space.c: revision 1.2
	sys/arch/arm/arm32/db_machdep.c: revision 1.23
	sys/arch/arm/allwinner/awin_space.c: revision 1.4
	sys/arch/arm/include/rwlock.h: revision 1.9
	sys/arch/arm/amlogic/amlogic_space.c: revision 1.2
	sys/arch/arm/zynq/zynq_space.c: revision 1.2
	sys/arch/arm/broadcom/bcm2835_space.c: revision 1.7
	sys/arch/arm/arm32/pmap.c: revision 1.317
	sys/arch/arm/include/locore.h: revision 1.19
	sys/arch/arm/include/mutex.h: revision 1.20
	sys/arch/arm/include/lock.h: revision 1.31
	sys/arch/arm/include/lock.h: revision 1.32
	sys/arch/arm/broadcom/bcmgen_space.c: revision 1.5
- Kill redundant semicolons.
- Indentation.
- Improve inline asm around dsb/dmb/isb:
  - always use volatile and mark them as memory barrier
  - use the common version from locore.h in all places not included from
    userland

Add some KASSERTs to catch similar bugs to the cnptes/nptes one

Sync with HEAD

Improve inline asm around dsb/dmb/isb:
- always use volatile and mark them as memory barrier
- use the common version from locore.h in all places not included from
  userland

Pull up following revision(s) (requested by skrll in ticket #188):
	sys/arch/arm/include/arm32/pmap.h: revision 1.136
	sys/arch/arm/include/armreg.h: revision 1.100
	sys/arch/arm/cortex/gic.c: revision 1.11
	sys/arch/arm/arm32/db_interface.c: revision 1.54
	sys/arch/arm/include/armreg.h: revision 1.101
	sys/arch/arm/cortex/gic.c: revision 1.12
	sys/arch/arm/arm32/arm32_machdep.c: revision 1.107
	sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20
	sys/arch/evbarm/conf/BPI: revision 1.5
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21
	sys/arch/arm/arm32/pmap.c: revision 1.306
	sys/arch/arm/arm32/db_machdep.c: revision 1.22
	sys/arch/arm/arm32/arm32_tlb.c: revision 1.3
	sys/arch/arm/arm/undefined.c: revision 1.55
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22
	sys/arch/arm/arm32/pmap.c: revision 1.307
	sys/arch/arm/arm32/arm32_tlb.c: revision 1.4
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23
	sys/arch/arm/arm32/arm32_tlb.c: revision 1.5
	sys/arch/evbarm/conf/BPI: revision 1.8
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24
	sys/arch/arm/arm32/arm32_tlb.c: revision 1.6
	sys/arch/arm/arm32/arm32_tlb.c: revision 1.7
	sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5
	sys/arch/arm/pic/pic.c: revision 1.23
	sys/arch/arm/pic/pic.c: revision 1.24
	sys/arch/arm/pic/picvar.h: revision 1.11
	sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20
	sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16
	sys/arch/arm/arm32/pmap.c: revision 1.298
	sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17
	sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5
	sys/arch/arm/arm32/pmap.c: revision 1.310
	sys/arch/arm/arm32/pmap.c: revision 1.311
	sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19
	sys/arch/arm/arm32/arm32_boot.c: revision 1.10
	sys/arch/arm/arm/ast.c: revision 1.25
	sys/arch/arm/include/armreg.h: revision 1.98
	sys/uvm/pmap/pmap_tlb.c: revision 1.10
	sys/arch/arm/arm32/arm32_boot.c: revision 1.8
	sys/arch/arm/arm32/arm32_boot.c: revision 1.9
	sys/arch/arm/arm/arm_machdep.c: revision 1.43
Various ARM MP fixes.

Whitespace

Sprinkle #include "opt_multiprocessor.h"

Rebase to HEAD as of a few days ago.

Rebase.

Trailing whitespace

More fixes as a step towards ARM_MMU_EXTENDED on RPI.

- don't set CPU_CONTROL_SYST_ENABLE in arm11x6_setup for ARM_MMU_EXTENDED

- Use the new MMU defines for V6N

- pull in arm/cpuconf.h in vmparam s that VM_MAXUSER_ADDRESS gets set
  correctly.

Fix macro name; PMAP_TLB_NEED_SHOOTDOWN => PMAP_NEED_TLB_SHOOTDOWN

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Make to flush the secondary cache when syncing PTEs when the Sheeva L2 cache
is used.

Add a kernel for the CUBIETRUCK (CUBIEBOARD3).  Allow direct mapping of all
memory (but for now allow the memory mapped above KERNEL_BASE to used for
poolpages).

For ARM_MMU_V6C enable supersections

Deal with large page mappings in l2pte_set.

Now the RPI can get passed setting the new TTB.

ok matt@

For ARM_MMU_EXTENDED, a KERNEL_BASE >= 0x80000000 is ok but a
VM_USER_MAXADDRESS can not be more than 0x80000000 - PAGE_SIZE.

Add a missing 0 to an #error

Make the ARM pmap use ASIDs, split TTBRs, and MP safe.  This only happens for
ARMv6 or later CPUs.  This means that on context switch that the TLBs and
caches no longer to cleaned/flushed.  Also, eXecute Never (XN) protection has
been added so non-exec pages can not be run.  Change the page size for ARMv6+
to be 8KB while allows a L1PT to be a normal page.  This means that the L1PT
is not special.  Use the XN support to only sync pages that are executed from.

Define PMAP_KMPAGE

Remove duplicate PMAP_PTE

Replace 1000 with PAGE_SIZE

Add PMAP_PTE flag.  (map page so it can be used as a PDE or PTE page)

Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.

sync with head

struct pcb; for a function prototype.

Add l2pte_set and l2pte_reset inlines to set/reset a pte.  These will be
used to support > 4KB pages sizes.
Don't use >> L1_S_SHIFT, use L1_IDX() instead.

resync from head

Add a ARM_HAS_VBAR option which forces the use of the VBAR register.  This
allows much code to deal with vector_page mappings to be eliminated.  On a
BEAGLEBONE kernel, this saves 8KB of text and instructions that never have
to be executed.  (The PJ4B has VBAR but doesn't implement the security
extensions it is part of so a method was needed to allow it use VBAR with
relying on the default test for the security extensions.)

resync with head

pullup pmap changes from HEAD

sync with (a bit old) head

Protect more definitions with #ifndef _LOCORE

Enable direct-mapped poolpages if __HAVE_MM_MD_DIRECT_MAPPED_PHYS is defined.

Add b{zero,copy}_page{,_vfp} and physical_end

Add pmap_{copy,zero}_page_vfp

Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.

Resync to 2012-11-19 00:00:00 UTC

C99 types

sync with head

Add PMAP_MAP_POOLPAGE / PMAP_UNMAP_POOLPAGE if PMAP_NEED_ALLOC_POOLPAGE is
defined.

Add a PMAP_NEEDS_ALLOC_POOLPAGE / PMAP_ALLOC_POOLPAGE hook so systems can
allocate pool pages from a specific VM freelist.

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed.  Default cortex to pmap_needs_fixup = 1.  But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

Fix the CACHE_MASKs for armv6 to include TEX and S bits.
Fix a comment in pte.h

Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

Alas, Cortex-A8 can't TLB walk out of their caches so they need to sync each PTE.

Enable "shareable" access to the page table for armv7.  PTE_SYNC only does
a DSB now on an armv7 cpu and no longer needs to flush the cache line to ram.

Make bus_dma understand supersections.

Backout previous, Matt fixed it differently

Move struct pv_addr next to struct bootmem_info into machdep.h and have
pmap.h include that.
Seems to be the least intrusive build fix; Matt: feel free to revamp.

Add a l1pte_supersection_p macro.

Add support for mapping SuperSection on armv6 and armv7.  These always
a domain of 0 so move the kernel from domain 15 to domain 0.

Fix more -fno-common fallout.
Move more variables to common locations.

sync with head

merge to -current.

Nuke the simplelock from vm_page_md

Catchup with rmind-uvmplock merge.

Welcome to 5.99.53!  Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
  New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
  the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
  Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
  kernel-lock on some ports).  Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.

Sync with HEAD.

sync with head

Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.

sync with head

Sync with HEAD

implement arm32_pmap_flags() to allow mappings with write buffering enabled,
mostly for video memory
Tested on shark

Sync with HEAD.

Move struct vm_page_md definition from vmparam.h to pmap.h, because
it's used only by pmap.  vmparam.h has definitions for wider
audience.

All GENERIC kernels build tested, except ia64.

powerpc/include/booke/vmparam.h has one too, but it has no pmap.h,
so it's left as is.

Fix build of evbarm.

Sync with HEAD.

sync with head.

sync with head

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

Change struct uvm_object::vmobjlock to be dynamically allocated with
mutex_obj_alloc().  It allows us to share the locks among UVM objects.

sync with head

A few more VM_PAGE_TO_MD().

Missing bits of pmap_is_page_colored_p() conversion.

Add write-through cache work-around for ARM11 as well as ARM9/ARM10.  Analyzed
& tested on i.MX35 with help from Tsubai Masanari.

Simplify pmap_remove() a little by avoiding pmap_do_remove() layer, since
possibility to skip wired mappings is not needed anymore.  Apart from that,
no functional differences are intended.

sync with head

Use PMAP_ENABLE_PMAP_KMPAGE to enable PMAP_KMPAGE.  We still want the bit
defined in the MI space, not in an MD header.

sync with head.

Rationalize the definition of PMAP_KMPAGE.

sync with head.

Sync with HEAD.

Sync with HEAD.

Reclaim PVF_KNC in VIPT to be PVF_MULTCLR (page has multiple colors).
Track when a page is mapping in multiple colors and deal with the ramifications.
When a page's MOD attribute is cleared, clean it from the cache.
Fix a logic inversion.

With these changes, the TI SDP2420 H4 board can successfully natively build a
TISDP2420 kernel.

Update haad-dm branch to haad-dm-base2.

Make pmap_kernel() a MI macro for struct pmap *kernel_pmap_ptr,
which is now the "API" provided by the pmap module.  pmap_kernel()
remains as the syntactic sugar.

Bonus cosmetics round: move all the pmap_t pointer typedefs into
uvm_pmap.h.

Thanks to Greg Oster for providing cpu muscle for doing test builds.

Sync with HEAD.

Sync with HEAD.

Sync with wrstuden-revivesa-base-2.

Fix a few more corner cases.  Always KMPAGE or pages with unmanaged writeable
kernel mappings as modified.  Only ever set DIRTY bit is DMOD is true and
NC is false.  Don't modify unmanaged mappings in pmap_clearbit.

Sync with head.

Add PMAP_KMPAGE defintion (forgotten commit).  Also add PVF_DIRTY which will
be used by an update pmap.c shortly (to note what pages may have dirty
cache lines).

Sync with head.

Revamp bookkeeping for pages entered by pmap_kenter_pa.  Keep track of them
on pvlists so that the cacheability can be properly tracked.

Sync with HEAD.

sync with head.

sync with head.

Merge kernel changes in matt-armv6 to HEAD.

Sync with HEAD.

Sync with HEAD.

sync with head

sync with HEAD

Sync with HEAD

Sync with HEAD.

Add support for kcore headers to arm32 kernel core dumps.

The kcore code is based on i386's kcore header handling.

Having an asm stub for dumpsys, to dump the registers onto the stack, and
then call the C code to do the memory dump is based on amd64's core dump
code.

This allows a successful core dump on cats.

Part of fixing PR cats/18026.

Add AT91 support from Sami Kantoluoto
Add TI OMAP2430 support from Marty Fouts @ Danger Inc

Add pmap_icache_sync_range and change arm32_sync_icache to use it.
This will only invalidate va that have valid PTEs.  This avoids cleaning
unneeded cache lines.

Make all the evbarm kernels build again.  Fix lossage from rebase.

sync with HEAD

Sync with HEAD.

sync with head.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Import TI OMAP 2430 and ARM11/ARMv6 support.  Now on ARMv6, the cache is
no longer purged on context switches.

Sync with head.

Sync with HEAD

Sync with HEAD.

ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged
as its cache/tlb management smarts relied too heavily on pre-merge context-
switch behaviour. See PR kern/36548 for one manifestation of the breakage.

To address this:
 - Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate)
   as it was too easy for them to get out of sync with the pmap.
 - Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C.
   It's only slightly less efficient, but is much more readable/maintainable.
 - Document cpufuncs.cf_context_switch() as being C-callable.
 - pmap_activate() becomes a no-op if the lwp's vmspace is already active.
   (Good performance win, since pmap_activate() is now invoked on every
   context-switch, even though ARM's cpu_switchto() already does all the
   grunt work)

XXX: Some CPU-specific armXX_context_switch() implementations (arm67,
arm7tdmi, arm8) always flush the I+D caches. This should not be necessary.
Someone with access to hardware (acorn32?) needs to deal with this.

- sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.

sync with head.

TRUE -> true, FALSE -> false

Replace the Mach-derived boolean_t type with the C99 bool type.  A
future commit will replace use of TRUE and FALSE with true and false.

sync with head.

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

Sync with head.

Implement pmap_collect() for arm32.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

On Xscale, define PMAP_UAREA() and use it to tweak uarea mappings so
they use the mini D$.

This results in a small performance boost on xscale platforms, since
flushing the main cache on a context switch won't affect the kernel
stack/pcb.

Add support for ARM10 class processors.

protect with #ifndef _LOCORE so that assembler codes can share
definitions in this file such as PMAP_DOMAIN_KERNEL.

Add another devmap routine that allows bootstrap code to register
a devmap reflecting mappings that are created by really early
bootstrap code before pmap_devmap_bootstrap() is called.

Replace the ad-hoc "section mapping table" for static device mappings
with a more generic "devmap" structure that can also handle mappings
made with large and small pages.  Add new pmap routines to enter these
mappings during bootstrap (and "remember" the devmap), and routines to
look up the static mappings once the kernel is running.

Remove #ifdefs supporting the old pmap, switching fully to the new.

Reduce differences between ARM32_NEW_VM_LAYOUT and not; always pass
the start and end of the kernel managed virtual address space to
pmap_bootstrap() in the new pmap.

Fix the bug reported by Richard Earnshaw in port-arm32/21349.

Make sure to check the access permissions before doing
ref/mod/domain fixups. This is particularly important
on machines with ARM_VECTORS_LOW.

Some ARM32_PMAP_NEW-related cleanup:
* Define a new "MMU type", ARM_MMU_SA1.  While the SA-1's MMU is basically
  compatible with the generic, the SA-1 cache does not have a write-through
  mode, and it is useful to know have an indication of this.
* Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at
  compile time.  We evaluate it like so:
  - If SA-1-style MMU is the only type configured -> 1
  - If SA-1-style MMU is not configured -> 0
  - Otherwise, defer to a run-time variable.
  If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time
  check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly
  code can include the necessary run-time support.  PMAP_INCLUDE_PTE_SYNC
  largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve
  included with the original new pmap.
* In the new pmap, make pmap_pte_init_generic() check to see if the CPU
  has a write-back cache.  If so, init the PT cache mode to C=1,B=0 to get
  write-through mode.  Otherwise, init the PT cache mode to C=1,B=1.
* Add a new pmap_pte_init_arm8().  Old pmap, same as generic.  New pmap,
  sets page table cacheability to 0 (ARM8 has a write-back cache, but
  flushing it is quite expensive).
* In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to
  C=1,B=0, since the write-back check in generic gets it wrong for ARM9,
  since we use write-through mode all the time on ARM9 right now.  (What
  this really tells me is that the test for write-through cache is less
  than perfect, but we can fix that later.)
* Add a new pmap_pte_init_sa1().  Old pmap, same as generic.  New pmap,
  does generic initialization, then resets page table cache mode to
  C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.

Gah, fix *another* typo.

Oops, fix typo.

Define two new macros to test if a mapping is mappable with an L1 Section
mapping or an L2 Large Page mapping.

Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

 - It allows L1 descriptor tables to be shared efficiently between
   multiple processes. A typical "maxusers 32" kernel, where NPROC is set
   to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
   with just 4 L1s. This completely solves the problem of running out
   of contiguous physical memory for allocating new L1s at runtime on a
   busy system.

 - Much improved cache/TLB management "smarts". This change ripples
   out to encompass the low-level context switch code, which is also
   much smarter about when to flush the cache/TLB, and when not to.

 - Faster allocation of L2 page tables and associated metadata thanks,
   in part, to the pool_cache enhancements recently contributed to
   NetBSD by Wasabi Systems.

 - Faster VM space teardown due to accurate referenced tracking of L2
   page tables.

 - Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.

Add the ability for pool caches to cache the physical address of
objects.  Clients of the pool_cache API must consistently use
the "paddr" variants or not, otherwise behavior is undefined.

Enable this on Alpha, ARM, MIPS, and x86.  Other platforms must
define POOL_VTOPHYS() in the appropriate manner in order to enable
the feature.

Part 1 of a series of simple patches contributed by Wasabi Systems
to improve network performance.

Garbage collect pmap_map, the last (and only?) use has been removed.

Sync with HEAD.

Fix PTE_FLUSH_RANGE macro, it should have had a cnt parameter.

Catch up to -current.

sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work

it really helps to get the stub right before cutting + pasting it 27 times.
alas, I did not.  doh.

add pmap_remove_all() hook (empty on most platforms so far).

sync kqueue branch with HEAD

catch up with -current.

Sync with -current.

Define macros describing the 4M super-sections that our pmap
actually uses (since we allocate PT pages in 4K chunks, rather
than 1K chunks).

Enable caching on kernel and user page tables.  This saves having
to do uncached memory access during VM operations (which can be
quite expensive on some CPUs).

We currently write-back PTEs as soon as they're modified; there is
some room for optimization (to write them back in larger chunks).
For PTEs in the APTE space (i.e. PTEs for pmaps that describe another
process's address space), PTEs must also be evicted from the cache
complete (PTEs in PTE space will be evicted durint a context switch).

* Add PTE_SYNC() and PTE_SYNC_RANGE() macros.  These don't actually do
  anything yet.
* Use PTE_SYNC() and PTE_SYNC_RANGE() in some obvious places, i.e.
  where vtopte() is used.

Catch up to -current.

Add a PVF_EXEC -- we don't use it yet, though.

Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length.  In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.

Move the calls to uvm_page_physload() out of pmap_bootstrap() and
into platform-specific initialization code, giving platform-specific
code control over which free list a given chunk of memory gets put
onto.

Changes are essentially mechanical.  Test compiled for all ARM
platforms, test booted on Intel IQ80321 and Shark.

Discussed some time ago on port-arm.

catch up with -current on kqueue branch

Catch up to -current.

Default all XScale core processors to the read/write-allocate write-back
cache mode.  Add a new XSCALE_CACHE_WRITE_THROUGH option for people who
are paranoid about the cache-related errata (you *do* have to line up
the planets correctly to trip them, but having the option is useful).

Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel.  What
  you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
  on which ARM architecture versions are configured (based on CPU_*
  options).  Also defines ARM_NARCH to determins how many architecture
  versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
  which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
  to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.

Add separate pmap_{zero,copy}_page() functions for generic ARM
vs. XScale.  Use the mini-data cache for the destination on XScale,
thus saving tossing out 4K of possible-useful data from the main
data cache each time.

This significantly improves every test in lmbench.

* Move the code that cleans the XScale mini-data cache into its
  own function.
* Add a new function which sets up the mini-data cache clean area
  properly.

* Split pte_cache_mode into pte_l1_s_cache_mode, pte_l2_l_cache_mode,
  and pte_l2_s_cache_mode.  The cache-meaningful bits are different
  for these descriptor types on some processor models.
* Add pte_*_cache_mask, corresponding to each above, which has a mask
  of the cache-meangful bits, and define those for generic and XScale
  MMU classes.  Note, the L2_S_CACHE_MASK_xscale definition requires
  use of the Extended Small Page L2 descriptor (the "X" bit overlaps
  with AP bits otherwise).

Use the "Extended Small Page" L2 descriptor type on XScale (note
this means that there are no 1K sub-pages on XScale, but we don't
use them anyway).

Remove the implementation-defined bits from L1_S_PROTO_xscale and
L1_C_PROTO_xscale; while they are supposed to be set to 1 on generic
ARM MMUs (according to the SA-110 and ARM920T manuals), they are listed
as "should be zero" in the i80200 manual.

Define 2 classes of ARM MMUs:
1. Generic (compatible with ARM6)
1. XScale (can be used as generic, but also has certainly nifty extensions).

Define abstract PTE bit defintions for each MMU class.  If only one MMU
class is configured into the kernel (based on CPU_* options), then we
get the constants for that MMU class.  Otherwise we indirect through
varaibles set up via set_cpufuncs().

XXX The XScale bits are currently the same as the generic bits.  Baby steps.

Use abstract names for the protection and PTE type bits in
L1 and L2 descriptors.  This will allow us to support different
PTE layouts that enable the use of extensions on different
processor models.

* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
  Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h.  While
  doing this, two bugs (as a result of typos) were fixed in

	arm/arm32/bus_dma.c
	evbarm/integrator/int_bus_dma.c

Rename flags that are really part of the pv_entry/mdpage into
pmap.h and give them more descriptive names and better comments:
* PT_M  -> PVF_MOD (page is modified)
* PT_H  -> PVF_REF (page is referenced)
* PT_W  -> PVF_WIRED (mapping is wired)
* PT_Wr -> PVF_WRITE (mapping is writable)
* PT_NC -> PVF_NC (mapping is non-cacheable; multiple mappings)

Clean up handling of the vector page on 32-bit ARM systems:
* Don't refer to VA 0, instead refer to a new variable: vector_page
* Delete the old zero_page_*() functions, replacing them with a new
  one: vector_page_setprot().
* When manipulating vector page mappings in user pmaps, only do so if
  the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the
  vector page is mapped by the kernel pmap).
* Add a new function, arm32_vector_init(), which takes the virtual
  address of the vector page (which MUST be valid when the function
  is called) and a bitmask of vectors the kernel is going to take
  over, and performs all vector page initialization, including setting
  the V bit in the CPU Control register ("relocate vectors to high
  address"), if necessary.

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

* Some cleanup.
* Delete the call to pmap_copy() in pmap.h

Move some private pmap data structures into pmap.c

Tidy a few things up.

Correct the comment describing the layout of the VM space.  In
particular, don't describe a recursive PTE mapping, since the ARM
port doesn't (and can't) use one.

Remove exported pmap_pte() prototype.

Clean up PTE access macros a bit.

* arm_byte_to_page() -> arm_btop()
* arm_page_to_byte() -> arm_ptob()

Garbage-collect the "pagehook" stuff.

* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE
* Rename ALT_PAGE_TBLS_BASE -> APTE_BASE
* Garbage-collect PAGE_TABLE_SPACE_START

Remove redundant #ifdef _KERNEL

Catch up with -current.

* Make pmap_is_{modified,referenced}() macros in pmap.h that just
  test the attributes in the vm_page_md directly.
* Clean up pmap_clear_{modified,referenced}().
* Delete now-unused pmap_testbit().

Switch back to using vm_page_md (thanks chuq for finding the bug
in the code that made it unstable before!)

Implement pmap_growkernel for arm32 based ports.
Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats.
Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.

Catch up to -current.

Keep track of which kernel PTs are available during bootstrap,
and let pmap_map_chunk() lookup the correct one to use for the
current VA.  Eliminate the "l2table" argument to pmap_map_chunk().

Add a second L2 table for mapping kernel text/data/bss on the
IQ80310 (fixes booting kernels with ramdisks).

map_chunk() -> pmap_map_chunk(), and move it to pmap.c

map_pagetable() -> pmap_link_l2pt(), and move it to pmap.c

Collapse map_entry{,ro,nc}() into a single pmap_map_entry() that
takes a prot and a "cacheable" indicator.

Rename map_section() to pmap_map_section(), move it to pmap.c, and give it
an extra argument (prot - specifies protection of the mapping).

Sync w/ -current.

Back out all the vm_page_md changes.  They are causing some
mysterious problems (a similar change to the i386 pmap causes
mysterious problems there, as well), and the issue needs to
be investigated more.

Efficiency tweaks, some made possible by vm_page_md.

Use vm_page_md rather than pmap_physseg.  Saves lots of cycles in
common operations.

add a new flag PMAP_CACHE_VIVT for the pmap to inform the MI code that
that the cache is virtually-indexed and virtually-tagged (such as on the ARM),
and use this flag in the UBC code to be more friendly to those caches.

Sync kqueue branch with -current.

Catch up to -current.

Use <arm/cpufunc.h>, not <machine/cpufunc.h>.

- Move more contents of various <machine/vmparam.h> files into
  <arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
  implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
  that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
  than PT_CACHEABLE, since the latter expands to a variable these days).

Implement pmap_update().  Currently it just calls cpu_cpwait(),
which ensures that TLB/cache operations have completed.

Sync the thorpej-mips-cache branch with -current.

file pmap.h was added on branch nathanw_sa on 2002-01-08 00:23:12 +0000

Define boolean predicates pmap_pde_page, pmap_pde_section & pmap_pde_fpage,
which return true if their pde argument is a coarse page, section or
fine page respectively.

Catch up with -current.

Sprinkle some static and inline into a couple of functions.  Remove dead entries from pmap.h.

Update the kqueue branch to HEAD.

Update pmap_update to now take the updated pmap as an argument.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.

Currently this is a no-op on most platforms, so they should see no difference.

Reviewed by Jason.

Merge Aug 24 -current into the kqueue branch.

Checking a whole host of pmap changes:
Improved locking (not that we actually use it on a uniprocessor, but one day :)
Removed unneeded splvm's
tweaked pmap_clean_page code to only flush the cache if the page is mapped in the current pmap  (based on diff from richard E)
Adopted pv entry allocation mechanism from i386.
Laid framework for returning ptp's when we've finished with them rather than holding onto them till the process exits.
ptp's are now allocated with a uvm object for the pmap, means that we can walk a list to free them off in pmap_release, until they get freed off by pmap_remove.

Also implemented a page zeroing function when the processor is idling.  Note that hpcarm may wish to disable this.

I believe this code to be stable, if anyone has any problems please shout up.

update to -current

Rework the pmap_release code to not have to walk the ptpt, it now uses a uvm_object to track the allocated vm_pages, this means it can free off the entries in the uvm_object.

Testing shows that it's about 5% faster on the make configure step for gmake.

A couple of tidy ups to pmap:
pmap_t -> struct pmap * in pmap.c and pmap.h
kernel_pmap -> pmap_kernel() everywhere.

Compiled and booted on riscpc and cats.

GC a couple of unused entries in the pmap struct

Catch up to -current.

replace vm_page_t with struct vm_page *.

replace {simple_,}lock{_data,}_t with struct {simple,}lock {,*}.

Sync with HEAD.

Undo a misguided previous change to the pmap_update() API.

Give pmap_update() an argument (a pmap_t) so that it knows which
pmap it should be updating.

Update the comment for pmap_update().

Sync with HEAD.

file pmap.h was added on branch thorpej_scsipi on 2001-03-12 13:27:25 +0000

more vm_offset_t/vm_size_t -> {p,v}{addr,size}_t changes
move pmap_* declarations to pmap.h.  fix conflicts this
exposed (e.g different definitions for pmap_bootstrap).

Convert some vm_size_t to vsize_t/psize_t.   Change vaddr_t to paddr_t
where appropriate.

s/vm_offset_t/vaddr_t/g

Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.