Annotation of src/sys/arch/arm/imx/imx31_icu.c, Revision 1.1.20.1
1.1.20.1! mjf 1: /* $NetBSD$ */
! 2: /*-
! 3: * Copyright (c) 2007 The NetBSD Foundation, Inc.
! 4: * All rights reserved.
! 5: *
! 6: * This code is derived from software contributed to The NetBSD Foundation
! 7: * by Matt Thomas.
! 8: *
! 9: * Redistribution and use in source and binary forms, with or without
! 10: * modification, are permitted provided that the following conditions
! 11: * are met:
! 12: * 1. Redistributions of source code must retain the above copyright
! 13: * notice, this list of conditions and the following disclaimer.
! 14: * 2. Redistributions in binary form must reproduce the above copyright
! 15: * notice, this list of conditions and the following disclaimer in the
! 16: * documentation and/or other materials provided with the distribution.
! 17: *
! 18: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
! 19: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 20: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 21: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
! 22: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 23: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 24: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 25: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 26: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 27: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 28: * POSSIBILITY OF SUCH DAMAGE.
! 29: */
! 30: #include <sys/cdefs.h>
! 31: __KERNEL_RCSID(0, "$NetBSD$");
! 32:
! 33: #define _INTR_PRIVATE
! 34:
! 35: #include "locators.h"
! 36:
! 37: #include <sys/param.h>
! 38: #include <sys/evcnt.h>
! 39: #include <sys/device.h>
! 40:
! 41: #include <uvm/uvm_extern.h>
! 42:
! 43: #include <machine/intr.h>
! 44:
! 45: #include <arm/cpu.h>
! 46: #include <arm/armreg.h>
! 47: #include <arm/cpufunc.h>
! 48:
! 49: #include <machine/autoconf.h>
! 50: #include <machine/atomic.h>
! 51: #include <machine/bus.h>
! 52:
! 53: #include <arm/imx/imx31reg.h>
! 54: #include <arm/imx/imx31var.h>
! 55:
! 56: static void avic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
! 57: static void avic_block_irqs(struct pic_softc *, size_t, uint32_t);
! 58: static void avic_establish_irq(struct pic_softc *, struct intrsource *);
! 59: static void avic_source_name(struct pic_softc *, int, char *, size_t);
! 60:
! 61: const struct pic_ops avic_pic_ops = {
! 62: .pic_unblock_irqs = avic_unblock_irqs,
! 63: .pic_block_irqs = avic_block_irqs,
! 64: .pic_establish_irq = avic_establish_irq,
! 65: .pic_source_name = avic_source_name
! 66: };
! 67:
! 68: struct avic_softc {
! 69: struct device avic_dv;
! 70: struct pic_softc avic_pic;
! 71: bus_space_tag_t avic_memt;
! 72: bus_space_handle_t avic_memh;
! 73: };
! 74:
! 75: extern struct cfdriver avic_cd;
! 76:
! 77: #define INTC_READ(avic, reg) \
! 78: bus_space_read_4((avic)->avic_memt, (avic)->avic_memh, (reg))
! 79: #define INTC_WRITE(avic, reg, val) \
! 80: bus_space_write_4((avic)->avic_memt, (avic)->avic_memh, (reg), (val))
! 81: #define HW_TO_SW_IPL(ipl) ((ipl) + 1)
! 82: #define SW_TO_HW_IPL(ipl) ((ipl) - 1)
! 83:
! 84: void
! 85: avic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
! 86: {
! 87: struct avic_softc * const avic = (void *) pic;
! 88: #if 0
! 89: if (irq_base == 0)
! 90: INTC_WRITE(avic, IMX31_INTENABLEL, irq_mask);
! 91: else
! 92: INTC_WRITE(avic, IMX31_INTENABLEH, irq_mask);
! 93: #else
! 94: uint32_t irq;
! 95: while ((irq = ffs(irq_mask)) != 0) {
! 96: irq--;
! 97: irq_base += irq;
! 98: irq_mask >>= irq;
! 99: INTC_WRITE(avic, IMX31_INTENNUM, irq_base);
! 100: }
! 101: #endif
! 102: }
! 103:
! 104: void
! 105: avic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
! 106: {
! 107: struct avic_softc * const avic = (void *) pic;
! 108: #if 0
! 109: if (irq_base == 0)
! 110: INTC_WRITE(avic, IMX31_INTDISABLEL, irq_mask);
! 111: else
! 112: INTC_WRITE(avic, IMX31_INTDISABLEH, irq_mask);
! 113: #else
! 114: uint32_t irq;
! 115: while ((irq = ffs(irq_mask)) != 0) {
! 116: irq--;
! 117: irq_base += irq;
! 118: irq_mask >>= irq;
! 119: INTC_WRITE(avic, IMX31_INTDISNUM, irq_base);
! 120: }
! 121: #endif
! 122: }
! 123:
! 124: void
! 125: avic_establish_irq(struct pic_softc *pic, struct intrsource *is)
! 126: {
! 127: struct avic_softc * const avic = (void *) pic;
! 128: bus_addr_t priority_reg;
! 129: int priority_shift;
! 130: uint32_t v;
! 131:
! 132: KASSERT(is->is_irq < 64);
! 133: KASSERT(is->is_ipl < 16);
! 134:
! 135: priority_reg = IMX31_NIPRIORITY0 - (is->is_irq >> 3);
! 136: priority_shift = (is->is_irq & 7) * 4;
! 137: v = INTC_READ(avic, priority_reg);
! 138: v &= ~(0x0f << priority_shift);
! 139: v |= SW_TO_HW_IPL(is->is_ipl) << priority_shift;
! 140: INTC_WRITE(avic, priority_reg, v);
! 141:
! 142: KASSERT(is->is_type == IST_LEVEL);
! 143: }
! 144:
! 145: static const char * const avic_intr_source_names[] = AVIC_INTR_SOURCE_NAMES;
! 146:
! 147: void
! 148: avic_source_name(struct pic_softc *pic, int irq, char *buf, size_t len)
! 149: {
! 150: strlcpy(buf, avic_intr_source_names[irq], len);
! 151: }
! 152:
! 153: void
! 154: imx31_irq_handler(void *frame)
! 155: {
! 156: struct avic_softc * const avic = avic_cd.cd_devs[0];
! 157: struct pic_softc * const pic = &avic->avic_pic;
! 158: int32_t saved_nimask;
! 159: int32_t irq;
! 160: int ipl, newipl, oldipl;
! 161:
! 162: saved_nimask = INTC_READ(avic, IMX31_NIMASK);
! 163: for (;;) {
! 164: irq = INTC_READ(avic, IMX31_NIVECSR);
! 165: if (irq < 0)
! 166: break;
! 167: ipl = (int16_t) irq;
! 168: KASSERT(ipl >= 0);
! 169: irq >>= 16;
! 170: KASSERT(irq < 64);
! 171: KASSERT(pic->pic_sources[irq] != NULL);
! 172:
! 173: /*
! 174: * If this interrupt is not above the current spl,
! 175: * mark it as pending and try again.
! 176: */
! 177: newipl = HW_TO_SW_IPL(ipl);
! 178: if (newipl <= curcpu()->ci_cpl) {
! 179: pic_mark_pending(pic, irq);
! 180: continue;
! 181: }
! 182:
! 183: /*
! 184: * Before enabling interrupts, mask out lower priority
! 185: * interrupts and raise SPL to its equivalent.
! 186: */
! 187:
! 188: INTC_WRITE(avic, IMX31_NIMASK, ipl);
! 189: oldipl = _splraise(newipl);
! 190: cpsie(I32_bit);
! 191:
! 192: pic_dispatch(pic->pic_sources[irq], frame);
! 193:
! 194: /*
! 195: * Disable interrupts again. Drop SPL. Restore saved
! 196: * HW interrupt level.
! 197: */
! 198: cpsid(I32_bit);
! 199: splx(oldipl);
! 200: INTC_WRITE(avic, IMX31_NIMASK, saved_nimask);
! 201: }
! 202: }
! 203:
! 204: static int avic_match(device_t, cfdata_t, void *);
! 205: static void avic_attach(device_t, device_t, void *);
! 206:
! 207: CFATTACH_DECL(avic,
! 208: sizeof(struct avic_softc),
! 209: avic_match, avic_attach,
! 210: NULL, NULL);
! 211:
! 212: int
! 213: avic_match(device_t parent, cfdata_t self, void *aux)
! 214: {
! 215: struct ahb_attach_args * const ahba = aux;
! 216:
! 217: if (ahba->ahba_addr != INTC_BASE)
! 218: return 0;
! 219:
! 220: return 1;
! 221: }
! 222:
! 223: void
! 224: avic_attach(device_t parent, device_t self, void *aux)
! 225: {
! 226: struct avic_softc * const avic = (void *) self;
! 227: struct ahb_attach_args * const ahba = aux;
! 228: int error;
! 229:
! 230: KASSERT(ahba->ahba_irqbase != AHBCF_IRQBASE_DEFAULT);
! 231: KASSERT(self->dv_unit == 0);
! 232:
! 233: if (ahba->ahba_size == AHBCF_SIZE_DEFAULT)
! 234: ahba->ahba_size = INTC_SIZE;
! 235:
! 236: avic->avic_memt = ahba->ahba_memt;
! 237: error = bus_space_map(avic->avic_memt, ahba->ahba_addr, ahba->ahba_size,
! 238: 0, &avic->avic_memh);
! 239: if (error)
! 240: panic("avic_attach: failed to map register %#lx-%#lx: %d",
! 241: ahba->ahba_addr, ahba->ahba_addr + ahba->ahba_size - 1,
! 242: error);
! 243:
! 244: avic->avic_pic.pic_ops = &avic_pic_ops;
! 245: avic->avic_pic.pic_maxsources = 64;
! 246: strlcpy(avic->avic_pic.pic_name, self->dv_xname,
! 247: sizeof(avic->avic_pic.pic_name));
! 248:
! 249: pic_add(&avic->avic_pic, ahba->ahba_irqbase);
! 250: aprint_normal(": interrupts %d..%d\n",
! 251: ahba->ahba_irqbase, ahba->ahba_irqbase + 63);
! 252: #if 0
! 253: softintr_init();
! 254: #endif
! 255: }
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