CVS log for src/sys/arch/arm/imx/Attic/imx6_srcreg.h

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Default branch: MAIN

Sync w/ HEAD.

Tidyup the i.MX SoC support by

- Moving the  FDTised code to sys/arch/arm/nxp to match the
  sys/arch/{cpu}/{vendor} convention
- FDTise some more drivers
	- Secure Non-Volatile Storage
	- watchdog driver
	- On chip OTP
- Match fsl,imx6dl
- Add some more drivers to GENERIC that will be supported by i.MX 6
  boards

Sync with HEAD

Sync with head

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors.  AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested.  Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

update from HEAD

file imx6_srcreg.h was added on branch tls-maxphys on 2017-12-03 11:35:53 +0000

add support i.MX6 and NITROGEN6X evaluation board