CVS log for src/sys/arch/arm/cortex/gic.c

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Default branch: MAIN
Current tag: pgoyette-compat-0330

Revision 1.32 / (download) - annotate - [select for diffs], Wed Feb 7 20:42:17 2018 UTC (6 years, 2 months ago) by jmcneill
Branch: MAIN
CVS Tags: pgoyette-compat-base, pgoyette-compat-0330, pgoyette-compat-0322, pgoyette-compat-0315
Branch point for: pgoyette-compat
Changes since 1.31: +5 -6 lines
Diff to previous 1.31 (colored)

PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC

The priority level is changed by writing to GICC_PMR with interrupts
disabled. However, interrupts are enabled/disabled downstream of the GICC
at the CPU. When raising priority level, there is a window between the time
that interrupts are disabled and the GICC_PMR register is written. If an
interrupt occurs at a previously allowed priority before GICC_PMR is
changed, the CPU will receive the signal when interrupts are re-enabled.
At this time, GICC_PMR is now the new priority level, so reads of
GICC_IAR will report a spurious IRQ.

Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
there is at least one pending IRQ.

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