CVS log for src/sys/arch/arm/cortex/gic.c

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Default branch: MAIN
Current tag: netbsd-7-1-RELEASE

Revision 1.10.2.5 / (download) - annotate - [select for diffs], Thu Jul 30 09:37:37 2015 UTC (8 years, 8 months ago) by martin
Branch: netbsd-7
CVS Tags: netbsd-7-nhusb-base-20170116, netbsd-7-nhusb-base, netbsd-7-nhusb, netbsd-7-2-RELEASE, netbsd-7-1-RELEASE, netbsd-7-1-RC2, netbsd-7-1-RC1, netbsd-7-1-2-RELEASE, netbsd-7-1-1-RELEASE, netbsd-7-1, netbsd-7-0-RELEASE, netbsd-7-0-RC3, netbsd-7-0-2-RELEASE, netbsd-7-0-1-RELEASE, netbsd-7-0
Changes since 1.10.2.4: +5 -2 lines
Diff to previous 1.10.2.4 (colored) to branchpoint 1.10 (colored) next main 1.11 (colored)

Pull up following revision(s) (requested by skrll in ticket #890):
	sys/arch/arm/pic/pic.c: revision 1.27-1.32
	sys/arch/arm/omap/omap5430_intr.h: revision 1.3
	sys/arch/arm/broadcom/bcm2835_obio.c: revision 1.25
	sys/arch/arm/cortex/gic.c: revision 1.18
	sys/arch/arm/broadcom/bcm2835reg.h: revision 1.15
	sys/arch/evbarm/rpi/rpi_machdep.c: revision 1.61
	sys/arch/arm/broadcom/bcm2835_intr.h: revision 1.2
	sys/arch/arm/marvell/mvsoc_intr.h: revision 1.5
	sys/arch/arm/broadcom/bcm2835_intr.c: revision 1.8-1.10
	sys/arch/arm/pic/picvar.h: revision 1.12-1.14
	sys/arch/arm/omap/omap4430_intr.h: revision 1.3

Don't clear CI_ASTPENDING in exception return, do it in ast() instead.
Add basic support for __HAVE_PREEMPTION.
Use atomic ops for ci_astpending if __HAVE_PREEMPTION is defined.
Use kpreempt_disable/kpreempt_enable
Add __HAVE_PIC_HAVE_PENDING_INTRS and define it if __HAVE_PIC_SET_PRIORITY
is undefined (also define in mvsoc_intr.h since their use of the latter is
peculiar).  This new define controls whether the pending interrupt logic is
compiled.  The GIC doesn't use pending interrupts since it uses the priority
level on the GIC to control delivery of interrupts, thus there can never
be a pending interrupt.  The kernel shrinks about 4KB with the removal of
the pending interupt support,
Only if we __HAVE_PIC_PENDING_INTRS do we need the variables to track them.
Add #define __HAVE_PIC_PENDING_INTRS for the non-GIC PICs.
Add a pic_cpus to the softc which specifies which cpus the pic can send
IPIs to.  For GIC, initialize pic_cpus to kcpuset_running since it can handle
all the cpus.
Adapt pic to deal with the BCM2836 interrupts.
Move pic_pending_pics, pic_pending_ipls, and pic_blocked_irqs into a
structure and make then per-cpu.  There is no global interrupt state anymore.
Use right kcpuset call.
Don't need pic_ipi_sender anymore.
Don't send IPIs to ourselves if sending to everyone.
RPI2 MP support.
Thanks to Matt Thomas for making this possible with his changes to pic.c
Use a bit per IPI type in local mailbox 0 registers. Ok matt@
IPIs should be IPL_HIGH according to rmind@
Fix bcm2836mp_pic_{un,}block_irqs to handle timer AND mailbox interrupts
if they're both passed.  Thanks to nat@ for finding this.
Sprinkle some KASSERTs

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