src/sys/arch/arm/cortex/gic.c - diff

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version 1.10.2.3, 2015/03/15 22:46:38

version 1.10.2.4, 2015/03/21 17:24:19

Line 270 armgic_irq_handler(void *tf)

#if 0

const int ipl = armgic_priority_to_ipl(gicc_read(sc, GICC_RPR));

KASSERTMSG(panicstr != NULL || ipl == is->is_ipl,

"%s: irq %d: running ipl %d != source ipl %u",

ci->ci_data.cpu_name, irq, ipl, is->is_ipl);

#else

const int ipl = is->is_ipl;

Line 332 armgic_establish_irq(struct pic_softc *p

"irq %u: not valid (group[%zu]=0x%08x [0x%08x])",

is->is_irq, group, sc->sc_gic_valid_lines[group],

(uint32_t)__BIT(irq));

KASSERTMSG(is->is_type == IST_LEVEL || is->is_type == IST_EDGE,

"irq %u: type %u unsupported", is->is_irq, is->is_type);

Line 342 armgic_establish_irq(struct pic_softc *p

uint32_t cfg = gicd_read(sc, cfg_reg);

if (group > 0) {

* There are 4 irqs per TARGETS register. For now bind

* to the primary cpu.

Line 357 armgic_establish_irq(struct pic_softc *p

targets |= 1 << byte_shift;

gicd_write(sc, targets_reg, targets);

* There are 16 irqs per CFG register. 10=EDGE 00=LEVEL

uint32_t new_cfg = cfg;

Line 384 armgic_establish_irq(struct pic_softc *p

#endif

}

* There are 4 irqs per PRIORITY register. Map the IPL

* to GIC priority.

Line 436 static void

armgic_cpu_init_targets(struct armgic_softc *sc)

{

* Update the mpsafe targets

for (size_t irq = 32; irq < sc->sc_pic.pic_maxsources; irq++) {

struct intrsource * const is = sc->sc_pic.pic_sources[irq];