CVS log for src/sys/arch/arm/cortex/a9tmr.c

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arm: Use device_set_private for various drivers.

Sync w/ HEAD.

comparision -> comparison

Mostly merge changes from HEAD upto 20200411

Trailing whitespace

Sync with HEAD

Sync with HEAD, resolve a couple of conflicts

Switch the DE0 Nano SoC to the GENERIC kernel.

Enable the global timer at attach time, it ensures that delay() works.

Sync with head

Remove comment that the peripherals clock should be half of the cpu clock.
NFC

Sync with HEAD

Use mpcaa_off1 parameter for mapping subregion.

Rename ARM A9 Global Timer driver name to support fdt.

- Rename a9tmr to arma9tmr.
- Add a9tmr_fdt.c based gtmr_fdt.c.

update from HEAD

Sync with HEAD

KNF

- fix sc_ev_missing_ticks over-counting.
- don't use 64bit division, because it has expensive cost on gcc/arm
  whether it is a constant or not.

'delta' is usually taken a value around sc_autoinc depending on timing
of read. therefore 'delta / sc->sc_autoinc' would be count too much.

Sync with HEAD

Pull up following revision(s) (requested by jmcneill in ticket #598):
	sys/arch/arm/amlogic/amlogic_board.c: up to revision 1.9
     	sys/arch/arm/amlogic/amlogic_canvasreg.h: revision 1.1
     	sys/arch/arm/amlogic/amlogic_com.c: up to revision 1.4
     	sys/arch/arm/amlogic/amlogic_comreg.h: up to revision 1.3
	sys/arch/arm/amlogic/amlogic_comvar.h: revision 1.1
	sys/arch/arm/amlogic/amlogic_cpufreq.c: up to revision 1.2
     	sys/arch/arm/amlogic/amlogic_crureg.h: up to revision 1.7
     	sys/arch/arm/amlogic/amlogic_dwctwo.c: up to revision 1.2
     	sys/arch/arm/amlogic/amlogic_genfb.c: revision 1.1
	sys/arch/arm/amlogic/amlogic_gmac.c: up to revision 1.2
	sys/arch/arm/amlogic/amlogic_hdmireg.h: revision 1.1
     	sys/arch/arm/amlogic/amlogic_intr.h: up to revision 1.5
     	sys/arch/arm/amlogic/amlogic_io.c: up to revision 1.7
     	sys/arch/arm/amlogic/amlogic_reg.h: up to revision 1.9
	sys/arch/arm/amlogic/amlogic_rng.c: revision 1.1
     	sys/arch/arm/amlogic/amlogic_sdhc.c: up to revision 1.3
     	sys/arch/arm/amlogic/amlogic_sdhcreg.h: revision 1.1
     	sys/arch/arm/amlogic/amlogic_space.c: revision 1.1
     	sys/arch/arm/amlogic/amlogic_var.h: up to revision 1.8
     	sys/arch/arm/amlogic/amlogic_vpureg.h: revision 1.1
	sys/arch/arm/arm/bootconfig.c: revisions 1.7-1.8
	sys/arch/arm/conf/files.arm: revision 1.129
	sys/arch/arm/cortex/pl310.c: revisions 1.16-1.17
	sys/arch/arm/cortex/a9_mpsubr.S: revisions 1.25-1.29
	sys/arch/arm/cortex/a9tmr.c: revisions 1.8-1.12
	sys/arch/arm/cortex/a9tmr_var.h: revision 1.4
	sys/arch/arm/cortex/a9wdt.c: revisions 1.3-1.4
	sys/arch/arm/cortex/armperiph.c: revisions 1.5-1.7
	sys/arch/arm/arm/cpufunc.c: revision 1.151
	sys/arch/arm/include/bootconfig.h: revision 1.7
	sys/arch/arm/include/locore.h: revision 1.19
	sys/arch/evbarm/amlogic/amlogic_machdep.c: up to revision 1.17
     	sys/arch/evbarm/amlogic/amlogic_start.S: up to revision 1.2
     	sys/arch/evbarm/amlogic/genassym.cf: revision 1.1
     	sys/arch/evbarm/amlogic/platform.h: revision 1.1
     	sys/arch/evbarm/conf/files.amlogic: up to revision 1.8
	sys/arch/evbarm/conf/std.amlogic: up to revision 1.2
	sys/arch/evbarm/conf/mk.amlogic: revision 1.1
     	sys/arch/evbarm/conf/ODROID-C1: up to revision 1.12
     	sys/arch/evarm/conf/ODROID-C1_INSTALL: revision 1.1
Don't use not as a variable since it's reserved in C++.
--
clean the a9 l2 cache before turning it on.
--
Add Cortex-A17 support
--
Fix CORTEXA17 support
--
Let the "cbar" device property override the cbar value, to work around
broken bootloaders
--
add a helper to update a9tmr frequency
--
detach and re-attach timecounter when updating freq, and reinit timer on
each cpu
--
fix typo
--
add BOOTOPT_TYPE_MACADDR for parsing mac address parameters
--
make sure we set ACTLR.SMP=1 for CPU_CORTEXA5 in !MP case, ok matt@
--
According to the Cortex-A5 TRM, the CBAR register is not implemented and
always reads as 0x00000000. Add ARM_CBAR option to set this in kernel
config.
--
skip a TLBIALL on Cortex-A5 that stops my odroid-c1 from booting, ok matt
--
match on Cortex-A5
--
match on Cortex-A5
--
allow arml2cc to be used on Cortex-A5 if the "offset" property is specified
--
print "A5" instead of "A9" at attach time if running on a Cortex-A5
--
Improve inline asm around dsb/dmb/isb:
- always use volatile and mark them as memory barrier
- use the common version from locore.h in all places not included from
  userland
--
Work-in-progress Odroid-C1 support.
--
no need to override ARM_CBAR, remove unused COM_16750 option
--
Add basic serial console support.
--
add dwctwo and usb devices
--
ODROID-C1 SMP support.
--
auto-detect RAM size
--
ODROID-C1 onboard ethernet support.
--
add amlogicrng, add commented-out genfb placeholder
--
enable amlogicsdhc
--
add ODROID-C1 install kernel
--
Add CPUFREQ option to set boot CPU frequency. ODROID-C1 is advertised
as quad-core 1.5GHz but boots up at 1.2GHz; add CPUFREQ=1512 to config
and make sure to set the correct speed before attaching CPUs.
The speed can still be scaled down with machdep.cpu sysctls.
--
disable DEBUG, LOCKDEBUG, VERBOSE_INIT_ARM
--
Basic framebuffer console support. Work in progress.

print "A5" instead of "A9" at attach time if running on a Cortex-A5

match on Cortex-A5

fix typo

detach and re-attach timecounter when updating freq, and reinit timer on each cpu

add a helper to update a9tmr frequency

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Mark interrupt as MPSAFE.

Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.

resync from head

file a9tmr.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000

Pass the offset from CBAR/PERIPHBASE in mpcore_attach_args.
Modify the list of devices to include the offset(s) from PERIPHBASE.

Don't attach a9tmr if the CPU supports the generic timer.

resync with head

sync with (a bit old) head

Sync with HEAD.

Make sure we enable the timer since CFE doesn't enable it by default.

Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.

Resync to 2012-11-19 00:00:00 UTC

sync with head

file a9tmr.c was added on branch matt-nb6-plus on 2012-11-28 22:40:25 +0000

file a9tmr.c was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000

Don't bother dealing with "extra" ticks, just count them.

Set dv_private, use a9tmr_private.

Add Cortex-A9 support including the ARM Generic Interrupt Controller
and the A9 Global Timer / Watchdog.