Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. =================================================================== RCS file: /ftp/cvs/cvsroot/src/sys/arch/arm/arm32/pmap.c,v rcsdiff: /ftp/cvs/cvsroot/src/sys/arch/arm/arm32/pmap.c,v: warning: Unknown phrases like `commitid ...;' are present. retrieving revision 1.219 retrieving revision 1.219.4.1 diff -u -p -r1.219 -r1.219.4.1 --- src/sys/arch/arm/arm32/pmap.c 2010/11/12 07:59:25 1.219 +++ src/sys/arch/arm/arm32/pmap.c 2011/03/05 15:09:32 1.219.4.1 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.c,v 1.219 2010/11/12 07:59:25 uebayasi Exp $ */ +/* $NetBSD: pmap.c,v 1.219.4.1 2011/03/05 15:09:32 bouyer Exp $ */ /* * Copyright 2003 Wasabi Systems, Inc. @@ -211,7 +211,7 @@ #include #include -__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.219 2010/11/12 07:59:25 uebayasi Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.219.4.1 2011/03/05 15:09:32 bouyer Exp $"); #ifdef PMAP_DEBUG @@ -2745,6 +2745,16 @@ pmap_create(void) return (pm); } +u_int +arm32_mmap_flags(paddr_t pa) +{ + /* + * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff + * and we're using the upper bits in page numbers to pass flags around + * so we might as well use the same bits + */ + return (u_int)pa & PMAP_MD_MASK; +} /* * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, * u_int flags) @@ -2953,9 +2963,12 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_ /* * Make sure the vector table is mapped cacheable */ - if (pm != pmap_kernel() && va == vector_page) + if ((pm != pmap_kernel() && va == vector_page) || + (flags & ARM32_MMAP_CACHEABLE)) { npte |= pte_l2_s_cache_mode; - + } else if (flags & ARM32_MMAP_WRITECOMBINE) { + npte |= pte_l2_s_wc_mode; + } if (opg) { /* * Looks like there's an existing 'managed' mapping @@ -5917,14 +5930,17 @@ pmap_devmap_find_va(vaddr_t va, vsize_t */ pt_entry_t pte_l1_s_cache_mode; +pt_entry_t pte_l1_s_wc_mode; pt_entry_t pte_l1_s_cache_mode_pt; pt_entry_t pte_l1_s_cache_mask; pt_entry_t pte_l2_l_cache_mode; +pt_entry_t pte_l2_l_wc_mode; pt_entry_t pte_l2_l_cache_mode_pt; pt_entry_t pte_l2_l_cache_mask; pt_entry_t pte_l2_s_cache_mode; +pt_entry_t pte_l2_s_wc_mode; pt_entry_t pte_l2_s_cache_mode_pt; pt_entry_t pte_l2_s_cache_mask; @@ -5956,12 +5972,15 @@ pmap_pte_init_generic(void) { pte_l1_s_cache_mode = L1_S_B|L1_S_C; + pte_l1_s_wc_mode = L1_S_B; pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; pte_l2_l_cache_mode = L2_B|L2_C; + pte_l2_l_wc_mode = L2_B; pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; pte_l2_s_cache_mode = L2_B|L2_C; + pte_l2_s_wc_mode = L2_B; pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; /* @@ -6040,6 +6059,10 @@ pmap_pte_init_arm9(void) pte_l2_l_cache_mode = L2_C; pte_l2_s_cache_mode = L2_C; + pte_l1_s_wc_mode = L1_S_B; + pte_l2_l_wc_mode = L2_B; + pte_l2_s_wc_mode = L2_B; + pte_l1_s_cache_mode_pt = L1_S_C; pte_l2_l_cache_mode_pt = L2_C; pte_l2_s_cache_mode_pt = L2_C; @@ -6062,6 +6085,10 @@ pmap_pte_init_arm10(void) pte_l2_l_cache_mode = L2_B | L2_C; pte_l2_s_cache_mode = L2_B | L2_C; + pte_l1_s_cache_mode = L1_S_B; + pte_l2_l_cache_mode = L2_B; + pte_l2_s_cache_mode = L2_B; + pte_l1_s_cache_mode_pt = L1_S_C; pte_l2_l_cache_mode_pt = L2_C; pte_l2_s_cache_mode_pt = L2_C; @@ -6084,6 +6111,10 @@ pmap_pte_init_arm11(void) pte_l2_l_cache_mode = L2_C; pte_l2_s_cache_mode = L2_C; + pte_l1_s_wc_mode = L1_S_B; + pte_l2_l_wc_mode = L2_B; + pte_l2_s_wc_mode = L2_B; + pte_l1_s_cache_mode_pt = L1_S_C; pte_l2_l_cache_mode_pt = L2_C; pte_l2_s_cache_mode_pt = L2_C; @@ -6123,12 +6154,15 @@ pmap_pte_init_xscale(void) int write_through = 0; pte_l1_s_cache_mode = L1_S_B|L1_S_C; + pte_l1_s_wc_mode = L1_S_B; pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; pte_l2_l_cache_mode = L2_B|L2_C; + pte_l2_l_wc_mode = L2_B; pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; pte_l2_s_cache_mode = L2_B|L2_C; + pte_l2_s_wc_mode = L2_B; pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; pte_l1_s_cache_mode_pt = L1_S_C;