Annotation of src/sys/arch/arm/arm32/locore.S, Revision 1.14.2.1
1.14.2.1! skrll 1: /* $NetBSD: locore.S,v 1.15 2004/02/13 11:36:11 wiz Exp $ */
1.1 chris 2:
3: /*
4: * Copyright (C) 1994-1997 Mark Brinicombe
5: * Copyright (C) 1994 Brini
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by Brini.
19: * 4. The name of Brini may not be used to endorse or promote products
20: * derived from this software without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
23: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25: * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26: * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28: * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32: */
33:
34: #include "opt_ipkdb.h"
35: #include "assym.h"
36: #include <sys/syscall.h>
37: #include <sys/errno.h>
38: #include <machine/asm.h>
39: #include <machine/cpu.h>
40: #include <machine/frame.h>
41: #include <machine/param.h>
42:
43: /* What size should this really be ? It is only used by init_arm() */
44: #define INIT_ARM_STACK_SIZE 2048
45:
46: /*
47: * This is for kvm_mkdb, and should be the address of the beginning
48: * of the kernel text segment (not necessarily the same as kernbase).
49: */
50:
1.2 thorpej 51: .text
52: .align 0
1.5 thorpej 53:
54: ENTRY_NP(kernel_text)
1.2 thorpej 55:
1.1 chris 56: ASENTRY_NP(start)
1.9 bjh21 57: adr r1, .Lstart
1.4 thorpej 58: ldmia r1, {r1, r2, sp} /* Set initial stack and */
59: sub r2, r2, r1 /* get zero init data */
1.1 chris 60: mov r3, #0
61:
1.7 briggs 62: .L1:
1.4 thorpej 63: str r3, [r1], #0x0004 /* Zero the bss */
1.1 chris 64: subs r2, r2, #4
1.7 briggs 65: bgt .L1
1.1 chris 66:
1.4 thorpej 67: mov fp, #0x00000000 /* trace back starts here */
68: bl _C_LABEL(initarm) /* Off we go */
1.1 chris 69:
70: /* init arm will return the new stack pointer. */
71: mov sp, r0
72:
73: mov fp, #0x00000000 /* trace back starts here */
74: mov ip, sp
75: stmfd sp!, {fp, ip, lr, pc}
76: sub fp, ip, #4
77:
1.4 thorpej 78: bl _C_LABEL(main) /* call main()! */
1.1 chris 79:
1.9 bjh21 80: adr r0, .Lmainreturned
1.4 thorpej 81: b _C_LABEL(panic)
82: /* NOTEACHED */
1.1 chris 83:
1.7 briggs 84: .Lstart:
1.1 chris 85: .word _edata
86: .word _end
87: .word svcstk + INIT_ARM_STACK_SIZE
1.4 thorpej 88:
1.8 thorpej 89: .Lmainreturned:
1.4 thorpej 90: .asciz "main() returned"
91: .align 0
1.1 chris 92:
93: .bss
94: svcstk:
95: .space INIT_ARM_STACK_SIZE
96:
97: .text
98: .align 0
99:
100: #ifndef OFW
101: /* OFW based systems will used OF_boot() */
102:
1.8 thorpej 103: .Lcpufuncs:
1.1 chris 104: .word _C_LABEL(cpufuncs)
105:
106: ENTRY_NP(cpu_reset)
1.7 briggs 107: mrs r2, cpsr
1.1 chris 108: bic r2, r2, #(PSR_MODE)
109: orr r2, r2, #(PSR_SVC32_MODE)
110: orr r2, r2, #(I32_bit | F32_bit)
111: msr cpsr_all, r2
112:
1.8 thorpej 113: ldr r4, .Lcpu_reset_address
1.1 chris 114: ldr r4, [r4]
115:
1.8 thorpej 116: ldr r0, .Lcpufuncs
1.10 bsh 117: mov lr, pc
1.3 thorpej 118: ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
1.1 chris 119:
120: /*
121: * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's
122: * necessary.
123: */
124:
1.8 thorpej 125: ldr r1, .Lcpu_reset_needs_v4_MMU_disable
1.1 chris 126: ldr r1, [r1]
127: cmp r1, #0
1.14 thorpej 128: mov r2, #0
1.1 chris 129:
130: /*
131: * MMU & IDC off, 32 bit program & data space
132: * Hurl ourselves into the ROM
133: */
1.13 thorpej 134: mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
1.1 chris 135: mcr 15, 0, r0, c1, c0, 0
1.14 thorpej 136: mcrne 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
1.1 chris 137: mov pc, r4
138:
139: /*
140: * _cpu_reset_address contains the address to branch to, to complete
1.14.2.1! skrll 141: * the CPU reset after turning the MMU off
1.1 chris 142: * This variable is provided by the hardware specific code
143: */
1.8 thorpej 144: .Lcpu_reset_address:
1.1 chris 145: .word _C_LABEL(cpu_reset_address)
146:
147: /*
148: * cpu_reset_needs_v4_MMU_disable contains a flag that signals if the
149: * v4 MMU disable instruction needs executing... it is an illegal instruction
150: * on f.e. ARM6/7 that locks up the computer in an endless illegal
151: * instruction / data-abort / reset loop.
152: */
1.8 thorpej 153: .Lcpu_reset_needs_v4_MMU_disable:
1.1 chris 154: .word _C_LABEL(cpu_reset_needs_v4_MMU_disable)
155:
156: #endif /* OFW */
157:
158: #ifdef IPKDB
159: /*
160: * Execute(inst, psr, args, sp)
161: *
162: * Execute INSTruction with PSR and ARGS[0] - ARGS[3] making
163: * available stack at SP for next undefined instruction trap.
164: *
165: * Move the instruction onto the stack and jump to it.
166: */
167: ENTRY_NP(Execute)
168: mov ip, sp
169: stmfd sp!, {r2, r4-r7, fp, ip, lr, pc}
170: sub fp, ip, #4
171: mov ip, r3
1.7 briggs 172: ldr r7, .Lreturn
1.1 chris 173: stmfd sp!, {r0, r7}
1.9 bjh21 174: adr r7, #.LExec
1.1 chris 175: mov r5, r1
1.7 briggs 176: mrs r4, cpsr
1.1 chris 177: ldmia r2, {r0-r3}
178: mov r6, sp
179: mov sp, ip
180: msr cpsr_all, r5
181: mov pc, r6
1.7 briggs 182: .LExec:
183: mrs r5, cpsr
1.1 chris 184: /* XXX Cannot switch thus easily back from user mode */
185: msr cpsr_all, r4
186: add sp, r6, #8
187: ldmfd sp!, {r6}
188: stmia r6, {r0-r3}
189: mov r0, r5
190: ldmdb fp, {r4-r7, fp, sp, pc}
1.7 briggs 191: .Lreturn:
1.1 chris 192: mov pc, r7
193: #endif
194:
195: /*
196: * setjump + longjmp
197: */
198: ENTRY(setjmp)
199: stmia r0, {r4-r14}
200: mov r0, #0x00000000
201: mov pc, lr
202:
203: ENTRY(longjmp)
204: ldmia r0, {r4-r14}
205: mov r0, #0x00000001
206: mov pc, lr
207:
208: .data
209: .global _C_LABEL(esym)
210: _C_LABEL(esym): .word _C_LABEL(end)
211:
212: ENTRY_NP(abort)
213: b _C_LABEL(abort)
214:
215:
216: /* End of locore.S */
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