version 1.26, 2012/08/16 18:22:40 |
version 1.27, 2012/08/29 07:14:04 |
Line 56 ENTRY_NP(kernel_text) |
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Line 56 ENTRY_NP(kernel_text) |
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ASENTRY_NP(start) |
ASENTRY_NP(start) |
adr r1, .Lstart |
adr r1, .Lstart |
ldmia r1, {r1, r2, sp} /* Set initial stack and */ |
ldmia r1, {r1, r2, r8, sp} /* Set initial stack and */ |
sub r2, r2, r1 /* get zero init data */ |
sub r2, r2, r1 /* get zero init data and cpu_info_store */ |
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#ifdef PROCESS_ID_IS_CURCPU |
#if defined(TPIDRPRW_IS_CURCPU) || defined(TPIDRPRW_IS_CURLWP) |
ldr r3, .Lcpu_info_store |
mcr p15, 0, r8, c13, c0, 4 |
mcr p15, 0, r3, c13, c0, 4 |
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#endif |
#endif |
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mov r3, #0 |
mov r3, #0 |
Line 70 ASENTRY_NP(start) |
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Line 69 ASENTRY_NP(start) |
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subs r2, r2, #4 |
subs r2, r2, #4 |
bgt .L1 |
bgt .L1 |
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mrc p15, 0, r3, c0, c0, 0 /* get our cpuid and save it early */ |
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str r3, [r8, #CI_ARM_CPUID] |
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mov fp, #0x00000000 /* trace back starts here */ |
mov fp, #0x00000000 /* trace back starts here */ |
bl _C_LABEL(initarm) /* Off we go */ |
bl _C_LABEL(initarm) /* Off we go */ |
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Line 87 ASENTRY_NP(start) |
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Line 89 ASENTRY_NP(start) |
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b _C_LABEL(panic) |
b _C_LABEL(panic) |
/* NOTREACHED */ |
/* NOTREACHED */ |
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#ifdef PROCESS_ID_IS_CURCPU |
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.Lcpu_info_store: |
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.word _C_LABEL(cpu_info_store) |
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#endif |
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.Lstart: |
.Lstart: |
.word _edata |
.word _edata |
.word _end |
.word _end |
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#if defined(TPIDRPRW_IS_CURCPU) |
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.word _C_LABEL(cpu_info_store) |
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#elif defined(TPIDRPRW_IS_CURLWP) |
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.word _C_LABEL(lwp0) |
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#else |
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.word 0 |
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#endif |
.word svcstk + INIT_ARM_STACK_SIZE |
.word svcstk + INIT_ARM_STACK_SIZE |
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.Lmainreturned: |
.Lmainreturned: |
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.word _C_LABEL(cpufuncs) |
.word _C_LABEL(cpufuncs) |
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ENTRY_NP(cpu_reset) |
ENTRY_NP(cpu_reset) |
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#ifdef _ARM_ARCH_6 |
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cpsid if, #PSR_SVC32_MODE |
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#else |
mrs r2, cpsr |
mrs r2, cpsr |
bic r2, r2, #(PSR_MODE) |
bic r2, r2, #(PSR_MODE) |
orr r2, r2, #(PSR_SVC32_MODE) |
orr r2, r2, #(PSR_SVC32_MODE) |
orr r2, r2, #(IF32_bits) |
orr r2, r2, #(IF32_bits) |
msr cpsr_c, r2 |
msr cpsr_c, r2 |
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#endif |
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ldr r0, .Lcpufuncs |
ldr r0, .Lcpufuncs |
mov lr, pc |
mov lr, pc |
Line 142 ENTRY_NP(cpu_reset) |
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Line 150 ENTRY_NP(cpu_reset) |
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* MMU & IDC off, 32 bit program & data space |
* MMU & IDC off, 32 bit program & data space |
* Hurl ourselves into the ROM |
* Hurl ourselves into the ROM |
*/ |
*/ |
mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE) |
mrc p15, 0, r0, c1, c0, 0 |
mcr 15, 0, r0, c1, c0, 0 |
bic r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE) |
mcreq 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */ |
bic r0, #(CPU_CONTROL_IC_ENABLE) |
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orr r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE) |
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mcr p15, 0, r0, c1, c0, 0 |
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mcreq p15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */ |
mov pc, r4 |
mov pc, r4 |
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/* |
/* |