CVS log for src/sys/arch/arm/arm32/genassym.cf

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Keyword substitution: kv
Default branch: MAIN

Some KASAN fixes and tweaks

- don't access BSS variables when __md_early
- centralise the INIT_ARM_STACK_{SHIFT,SIZE} defines and create a new
  INIT_ARM_TOTAL_STACK
- Only create L1PT entries in kasan_md_shadow_map_page if
  arm32_kernel_vm_init hasn't created the L2PTs (and their L1PT entries)
- Add some comments to explain what's going on

Mirror the changes to aarch64 and

- Switch to TPIDRPRW_IS_CURLWP, because curlwp is accessed much more often
  by MI code.  It also makes curlwp preemption safe,

- Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs
  can see spurious ASTs (which doesn't cause a problem, it just means some
  time may be wasted).

- Make sure ASTs are always set on the same CPU as the target LWP, and
  delivered via IPI if posted from a remote CPU so that they are resolved
  quickly.

- Add some cache line padding to struct cpu_info.

- Add a memory barrier in a couple of places where ci_curlwp is set.  This
  is needed whenever an LWP that is resuming on the CPU could hold an
  adaptive mutex.  The barrier needs to drain the CPU's store buffer, so
  that the update to ci_curlwp becomes globally visible before the LWP can
  resume and call mutex_exit().

Use the stack provided by armv6_start.S rather than svcstk.  This saves
some bss too.

Sort the __HAVE_* defines

Sort include "opt_..."s

KNF (sort includes)

Merge changes from current as of 20200406

Really use armv7 noncache memory attribute for early kernel mapping and
not SO

Sync with head.

G/C

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
  drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
  - a static cpu_info_store array
  - the same arm_cpu_{hatched,mbox}

Sort define CI_*. NFCI.

G/C some more

G/C

Sync with head.

Hopefully fix some problems seen with MP support on non-x86, in particular
where curcpu() is defined as curlwp->l_cpu:

- mi_switch(): undo the ~2007ish optimisation to unlock curlwp before
  calling cpu_switchto().  It's not safe to let other actors mess with the
  LWP (in particular l->l_cpu) while it's still context switching.  This
  removes l->l_ctxswtch.

- Move the LP_RUNNING flag into l->l_flag and rename to LW_RUNNING since
  it's now covered by the LWP's lock.

- Ditch lwp_exit_switchaway() and just call mi_switch() instead.  Everything
  is in cache anyway so it wasn't buying much by trying to avoid saving old
  state.  This means cpu_switchto() will never be called with prevlwp ==
  NULL.

- Remove some KERNEL_LOCK handling which hasn't been needed for years.

corect #include order

cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().

Sync with HEAD

Sync with head

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors.  AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested.  Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Group/sort struct arm_cache_info members

Sync with HEAD

on evbarm/RPI,RPI2, VERBOSE_INIT_ARM had broken.

XPUTC() of evbarm/rpi/rpi*_start.S uses bcm283[567]_platform_early_putchar() and it requires stack.
fixed to allocate stack when starting from rpi*_start.S and a9_mpsubr.S if needed.

to work XPUTC(), need to define VERBOSE_INIT_ARM and EARLYCONS option.

Remove port-acorn26

OK core@

update from HEAD

Sync with HEAD

Pull up following revision(s) (requested by skrll in ticket #1452):
	sys/arch/arm/arm32/genassym.cf: revision 1.75
	sys/arch/arm/arm/cpufunc_asm_arm11x6.S: revision 1.8
In idcache_wbinv_range if the range size is bigger than the dcache size
then call idcache_wbinv_all
Avoids a problem with large ranges as seen in
port-evbarm/52169: setting dtrace module to load cause Pi to hang on boot

Pull up following revision(s) (requested by skrll in ticket #122):
	sys/arch/arm/arm32/genassym.cf: revision 1.75
	sys/arch/arm/arm/cpufunc_asm_arm11x6.S: revision 1.8
In idcache_wbinv_range if the range size is bigger than the dcache size
then call idcache_wbinv_all
Avoids a problem with large ranges as seen in
port-evbarm/52169: setting dtrace module to load cause Pi to hang on boot

Alignment whitespace.  No functional change.

In idcache_wbinv_range if the range size is bigger than the dcache size
then call idcache_wbinv_all

Avoids a problem with large ranges as seen in
port-evbarm/52169: setting dtrace module to load cause Pi to hang on boot

Sync with HEAD

Trailing whitespace.

Use TTBR_[UM]PATTR in a9_mpsubr.S as well as cpufunc_asm_armv7

Prompted by matt@

Sync with HEAD

define __HAVE_PREEMPTION

__HAVE_UNNESTED_INTRS is never used.

Sync with HEAD

Pull up following revision(s) (requested by skrll in ticket #646):
	sys/arch/arm/arm32/genassym.cf: revision 1.70
	sys/arch/arm/arm32/cpuswitch.S: revision 1.86-1.89

Only set vfp & tpid registers and do ras lookups if new
lwp is not LW_SYSTEM.

Add L_FLAG/LW_SYSTEM

Rebase to HEAD as of a few days ago.

Rebase.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

emit VERBOSE_INIT_ARM

Add ARM_MMU_EXTENDED support.

Move pmap_recent_user to ci->ci_pmap_lastuser and
pmap_previous_active_lwp to ci->ci_lastlwp.  Fix some comments.

Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.

wrap opt_* includes with if defined(_KERNEL_OPT)

sync with head

include <arm/locore.h>

Add more TF_* symbols

Add L2_S_SIZE

resync from head

Add L1_S_V6_S

Add some defines for epoc32.

resync with head

sync with head

sync with (a bit old) head

Add CPU_VFP_ID and PCB_VFP_FPEXC

add __HAVE_MM_MD_DIRECT_MAPPED_PHYS

Add VFP_FPEXC_EN

Rename pcb_sp/PCB_SP to pcb_ksp/PCB_KSP so that ipsec.c will compile.

Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.

Resync to 2012-11-19 00:00:00 UTC

sync with head

Change to use symbolic constants from assym.h and fix a typo in a comment.

Implement a "fast" path for IRQ handling out of the idle loop.  Since we
are in SVC32 already we only need to save a few registers.  Processing is
also simplified since we know we can't return to user-mode.

Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

Add __BITS to asm.h  (remove from imxuartreg.h)
Add L1_S_AP_KR to genassym.h
Use L1_S_AP_* in omap_start.S and don't include pmap.h

Make cpu_reset, most of initarm and the kvm init code common.
Add MP hooks for cpu_need_resced
Add idlestck which is allocated in arm32_kvminit

Don't use locations in .data to store exception temporaries, use decidicated
space in cpu_info instead.  This also moves undefined_handler_address into
cpu_info as well.
Use the new armreg* inlines for getting TPIDRPRW register.
Add MULTIPROCESSOR version of CPU_INFO_FOREACH

Use ARMV6+ cpsi{d,f} instructions whenever possible.  Use r7 to hold previous
mode and avoid recomputing it.  Add support for obtaining kernel_lock on
exception entry and exit.

small rototill.
pcb_flags is dead.  PCB_NOALIGNFLT is now in stored l_md.md_flags as
MDLWP_NOALIGNFLT.  This avoids a few loads of the PCB in exception handling.
pcb_tf has been moved to l_md.md_tf.  Again this avoids a lot of pcb
references just to access or set this.  It also means that pcb doesn't
need to accessed by MI code.
Move pcb_onfault to after the pcb union.
Add pcb_sp macro to make code prettier.
Add lwp_settrapframe(l, tf) to set the l_md.md_tf field.
Use lwp_trapframe to access it (was process_frame but that name was changed
in a previous commit).
Kill off curpcb in acorn26.
Kill the checks for curlwp being NULL.
Move TRAP_USERMODE from arm32/fault.c to frame.h and a __PROG26 version.
Replace tests for usermode with that macro.

Kill curpcb/ci_curpcb.  Use device_t in cpu_info.
Add ci_softc (where ci_curpcb was so cpu_info doesn't change).

Remove irqframe and replace with identical trapframe.

Sync with HEAD.

sync with head

Fetch user read-only thread and process id from l->l_private, not the pcb.
(need to g/c the pcb field formerly used for this).

sync with head

Sync with HEAD

Define the L1* pte values.  Now pmap.h and pte.h no longer needed in .S files.

Retire struct user, remove sys/user.h inclusions.  Note sys/user.h header
as obsolete.  Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits.  Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

sync with head

Rename L_ADDR to L_PCB and amend some comments accordingly.

sync with head.

Sync with HEAD.

Sync with HEAD.

Sync with HEAD.

Remove advertising clause for UCB in various genassym.cf files,
which were derived from genassym.c in 4.4BSD-Lite2 (or 386BSD).
Closes PR misc/39573.  Approved by martin@.

Sync with wrstuden-revivesa-base-2.

Do fast softint processing in DO_AST_AND_RESTORE_ALIGNMENT_FAULTS.
Redo the softint mask so ci_softints >> ci_cpl != 0 becomes an easy
test for work to be done.

Sync with HEAD.

sync with head.

sync with head.

Merge kernel changes in matt-armv6 to HEAD.

sync with HEAD

Sync with HEAD.

Sync with HEAD.

Add assym symbols needed for fast softint switching

sync with head

Sync with HEAD

Sync to HEAD.

With the removal of IPKDB on arm, the undefined stack is only used to
bounce into SVC32 mode, there is no per-process data stored on it.

We can therefore use the undefined stack setup by the platform machdep.c
as a system wide undefined stack.

This removes the need for a per-process undefined stack, and the processor
mode switching overhead it causes in cpu_switchto.

The space freed in the USPACE is used to increase the per process kernel
stack size.

sync with HEAD

Sync with HEAD

As of this commit, all arm32 kernel now build.

Make sure interrupt handler is updating curcpu()->ci_depth

Sync with HEAD.

sync with HEAD

Sync with HEAD.

sync with head.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Sync with head.

Sync with HEAD

Sync with HEAD.

ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged
as its cache/tlb management smarts relied too heavily on pre-merge context-
switch behaviour. See PR kern/36548 for one manifestation of the breakage.

To address this:
 - Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate)
   as it was too easy for them to get out of sync with the pmap.
 - Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C.
   It's only slightly less efficient, but is much more readable/maintainable.
 - Document cpufuncs.cf_context_switch() as being C-callable.
 - pmap_activate() becomes a no-op if the lwp's vmspace is already active.
   (Good performance win, since pmap_activate() is now invoked on every
   context-switch, even though ARM's cpu_switchto() already does all the
   grunt work)

XXX: Some CPU-specific armXX_context_switch() implementations (arm67,
arm7tdmi, arm8) always flush the I+D caches. This should not be necessary.
Someone with access to hardware (acorn32?) needs to deal with this.

sync with head.

Update to new world order.

Sync with head.

Sync with head.

Update to HEAD.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

Remove process/LWP status constants.

Adapt arm32. Thanks to scw for helping out.

Tested on my cats (SA1)

XXX hydra should die. i've made some changes, but no guarantees.

Sync with HEAD.

Rewrite the ARM mutex implementation to be of the simple-mutex variety.
Because pre-v6 ARM lacks support for an atomic compare-and-swap, we
implement _lock_cas() as a restartable atomic squence that is checked
in the IRQ handler right before AST processing.  (This is safe because,
for all practical purposes, there are no SMP pre-v6 ARM systems.)

This can serve as a model for other non-MP platforms that lack the
necessary atomic operations for mutexes (SuperH, for example).

Upshots of this change:
- kmutex_t is now down to 8 bytes on ARM; about as good as we can get.
- ARM2 systems don't have to trap and emulate SWP or SWPB for mutexes.

The acorn26 port is not updated by this commit to do the LOCK_CAS_CHECK.
That is left as an exercise for the port maintainer.

Reviewed and tested by Matt Thomas.

Pull up following revision(s) (requested by matt in ticket #470):
	sys/arch/evbarm/iq80310/iq80310_timer.c: revision 1.20
	sys/arch/evbarm/ifpga/pl030_rtc.c: revision 1.8
	sys/arch/evbarm/include/types.h: revision 1.7
	sys/arch/arm/arm32/genassym.cf: revision 1.30
	sys/arch/arm/arm32/cpuswitch.S: revision 1.46
Get DOMAIN_CLIENT directly from arm/arm32/pte.h instead of from genassym
to avoid redefinition when both assymh and pte.h are included (as in
INTEGRATOR's intmmu.S, which uses more macros from pte.h).
Convert evbarm to __HAVE_GENERIC_TODR.

- sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.

sync with head.

Pull up following revision(s) (requested by matt in ticket #457):
	sys/arch/arm/arm32/genassym.cf: revision 1.31
Add KERNEL_BASE

Add KERNEL_BASE

Get DOMAIN_CLIENT directly from arm/arm32/pte.h instead of from genassym
to avoid redefinition when both assymh and pte.h are included (as in
INTEGRATOR's intmmu.S, which uses more macros from pte.h).

sync with head.

Sync with head.

sync with head

- Document COMPAT_15 as doing nothing
- Add COMPAT_15 to all the kernel that had COMPAT_14, for the sake of coherency
- Remove the only occurences of #ifdef COMPAT_15 in the tree: for the ARM
ports, COMPAT_15 was always used in conjunction with EXEC_AOUT. Only EXEC_AOUT
matters here.

This address kern/18407

merge ktrace-lwp.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Remove p_nras from struct proc - use LIST_EMPTY(&p->p_raslist) instead.
Remove p_raslock and rename p_lwplock p_lock (one lock is enough).
Simplify window test when adding a ras and correct test on VM_MAXUSER_ADDRESS.
Avoid unpredictable branch in i386 locore.S
(pad fields left in struct proc to avoid kernel bump)

Enable alignment faults on arm32 for both kernel and userland.

If COMPAT_15 and EXEC_AOUT are defined, support per-process
alignment checking where AFLTs are always enabled when running
kernel code and userland ELF binaries, and dynamically disabled/
enabled when switching to/from a.out binaries. This is necessary
in order to execute older a.out binaries, where gcc made
deliberate use of misaligned loads under certain circumstances.

Hand-optimised in_cksum/in4_cksum for ARM and XSCALE.
Contributed by Wasabi Systems, with input from Chris Gilbert,
Richard Earnshaw and David Laight.

Remove old pmap support.

Some ARM32_PMAP_NEW-related cleanup:
* Define a new "MMU type", ARM_MMU_SA1.  While the SA-1's MMU is basically
  compatible with the generic, the SA-1 cache does not have a write-through
  mode, and it is useful to know have an indication of this.
* Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at
  compile time.  We evaluate it like so:
  - If SA-1-style MMU is the only type configured -> 1
  - If SA-1-style MMU is not configured -> 0
  - Otherwise, defer to a run-time variable.
  If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time
  check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly
  code can include the necessary run-time support.  PMAP_INCLUDE_PTE_SYNC
  largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve
  included with the original new pmap.
* In the new pmap, make pmap_pte_init_generic() check to see if the CPU
  has a write-back cache.  If so, init the PT cache mode to C=1,B=0 to get
  write-through mode.  Otherwise, init the PT cache mode to C=1,B=1.
* Add a new pmap_pte_init_arm8().  Old pmap, same as generic.  New pmap,
  sets page table cacheability to 0 (ARM8 has a write-back cache, but
  flushing it is quite expensive).
* In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to
  C=1,B=0, since the write-back check in generic gets it wrong for ARM9,
  since we use write-through mode all the time on ARM9 right now.  (What
  this really tells me is that the test for write-through cache is less
  than perfect, but we can fix that later.)
* Add a new pmap_pte_init_sa1().  Old pmap, same as generic.  New pmap,
  does generic initialization, then resets page table cache mode to
  C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.

Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

 - It allows L1 descriptor tables to be shared efficiently between
   multiple processes. A typical "maxusers 32" kernel, where NPROC is set
   to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
   with just 4 L1s. This completely solves the problem of running out
   of contiguous physical memory for allocating new L1s at runtime on a
   busy system.

 - Much improved cache/TLB management "smarts". This change ripples
   out to encompass the low-level context switch code, which is also
   much smarter about when to flush the cache/TLB, and when not to.

 - Faster allocation of L2 page tables and associated metadata thanks,
   in part, to the pool_cache enhancements recently contributed to
   NetBSD by Wasabi Systems.

 - Faster VM space teardown due to accurate referenced tracking of L2
   page tables.

 - Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.

Use PAGE_SIZE rather than NBPG.

Merge the nathanw_sa branch.

Add CI_IDLEPCB for cpu_switch().

Re-do the following revisions, this time on a branch where they won't
interfere with the nathanw_sa merge:

syssrc/sys/arch/arm/arm32/cpuswitch.S			1.26
syssrc/sys/arch/arm/arm32/genassym.cf			1.18
syssrc/sys/arch/arm/arm32/vm_machdep.c			1.21
syssrc/sys/arch/arm/include/pcb.h			1.5

Original commit message:

In cpu_switch(), stack more registers at the start of the function,
and hence save fewer into the PCB.  This should give me enough free
registers in cpu_switch to tidy things up and support MULTIPROCESSOR
properly.  While we're here, make the stacked registers into an
APCS stack frame, so that DDB backtraces through cpu_switch() will
work.

This also affects cpu_fork(), which has to fabricate a switchframe and
PCB for the new process.

file genassym.cf was added on branch bjh21-hydra on 2002-10-19 11:59:36 +0000

Undo recent cpu_switch register usage changes in order to decrease nathanw_sa
merge pain.

In cpu_switch(), stack more registers at the start of the function,
and hence save fewer into the PCB.  This should give me enough free
registers in cpu_switch to tidy things up and support MULTIPROCESSOR
properly.  While we're here, make the stacked registers into an
APCS stack frame, so that DDB backtraces through cpu_switch() will
work.

This also affects cpu_fork(), which has to fabricate a switchframe and
PCB for the new process.

Catch up to -current.

Move curpcb into struct cpu_info in MULTIPROCESSOR kernels.

Minimal changes to allow a kernel with "options MULTIPROCESSOR" to compile
and boot multi-user on a single-processor machine.  Many of these changes
are wildly inappropriate for actual multi-processor operation, and correcting
this will be my next task.

This need L_PROC now, for the RAS code.

Catch up to -current.

sync kqueue branch with HEAD

catch up with -current.

Add machine-dependent bits of RAS for arm32.

Catch up to -current.

catch up with -current.

When delivering an upcall, arrange to have the kernel return to
the upcall directly, and use the upcall trampoline only to exit
if the upcall returns.

catch up with -current on kqueue branch

Garbage-collect sigframe references.

Catch up to -current.

* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
  Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h.  While
  doing this, two bugs (as a result of typos) were fixed in

	arm/arm32/bus_dma.c
	evbarm/integrator/int_bus_dma.c

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE
* Rename ALT_PAGE_TBLS_BASE -> APTE_BASE
* Garbage-collect PAGE_TABLE_SPACE_START

Catch up with -current.

Implement pmap_growkernel for arm32 based ports.
Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats.
Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.

Catch up to -current.

Sync w/ -current.

Allow platforms to use an extra level of indirection for FIQs,
enabled by definining __ARM_FIQ_INDIRECT in <machine/types.h>.
This is needed for OpenFirmware systems (like the Shark), where
the OFW vector page is used, and kernel entries merely patched
into it.

Overhaul of the ARM cache code.  This is mostly a simplification
pass.  Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:

	icache_sync_all         Synchronize I-cache
	icache_sync_range       Synchronize I-cache range

	dcache_wbinv_all        Write-back and Invalidate D-cache
	dcache_wbinv_range      Write-back and Invalidate D-cache range
	dcache_inv_range        Invalidate D-cache range
	dcache_wb_range         Write-back D-cache range

	idcache_wbinv_all       Write-back and Invalidate D-cache,
				Invalidate I-cache
	idcache_wbinv_range     Write-back and Invalidate D-cache,
				Invalidate I-cache range

Note: This does not yet include an overhaul of the actual asm files
that implement the primitives.  Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.

Sync kqueue branch with -current.

Catch up to -current.

* Share a common vector page between arm26 and arm32.
* Use a common set of exception handlers for all arm32 platforms.
* New FIQ framework based on discussions with Ben Harris, shared
  between arm26 and arm32.

Don't define interrupt handler-related offsets here.

Provide __PROG32 to assembly code.

Machine-dependent kernel mods for scheduler activations on
32-bit ARM processors.  Kernel boots multi-user on an XScale,
but upcalls not yet tested.

Catch up with -current.

Update the kqueue branch to HEAD.

file genassym.cf was added on branch nathanw_sa on 2001-11-15 06:39:22 +0000

Don't define pcb_* register macros.
pcb_sp macro conflicts with sys/netinet6/ipsec.c.

Don't compile SPL/INTR stuff if NEWINTR is defined.

Change <machine/irqhandler.h> to <machine/intr.h>.  Change
{irq,fiq}handler_t to struct XXXhandler

Remove unused entries from the pcb.  This is with a long term view of merging the arm26 and arm32 pcb's.

update to -current

file genassym.cf was added on branch kqueue on 2001-08-03 04:10:58 +0000

finish moving common arm32 bits out into arm/arm32.