CVS log for src/sys/arch/arm/arm32/arm32_tlb.c

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Keyword substitution: kv
Default branch: MAIN

Pass the pmap in tlb_set_asid for the benefit of aarch64.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime
detection instead of ifdefs where required.

Sync with HEAD

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

Sprinkle #include "opt_cputypes.h"

update from HEAD

Sync with HEAD

Do runtime detection of MP extensions to allow using a MULTIPROCESSOR
kernel on CPUs without the MP extensions feature (like Cortex-A8).

Sync with HEAD

Adapt to common pmap changes.

Sync with HEAD

don't use armreg_tlbiasidis_write() and armreg_icialluis_write()
on single processor platforms.

fix CPU_CORTEXA5 && !MULTIPROCESSOR build

Revision 1.7 got somehow lost in the merge from -current

Pull up following revision(s) (requested by skrll in ticket #188):
	sys/arch/arm/include/arm32/pmap.h: revision 1.136
	sys/arch/arm/include/armreg.h: revision 1.100
	sys/arch/arm/cortex/gic.c: revision 1.11
	sys/arch/arm/arm32/db_interface.c: revision 1.54
	sys/arch/arm/include/armreg.h: revision 1.101
	sys/arch/arm/cortex/gic.c: revision 1.12
	sys/arch/arm/arm32/arm32_machdep.c: revision 1.107
	sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20
	sys/arch/evbarm/conf/BPI: revision 1.5
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21
	sys/arch/arm/arm32/pmap.c: revision 1.306
	sys/arch/arm/arm32/db_machdep.c: revision 1.22
	sys/arch/arm/arm32/arm32_tlb.c: revision 1.3
	sys/arch/arm/arm/undefined.c: revision 1.55
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22
	sys/arch/arm/arm32/pmap.c: revision 1.307
	sys/arch/arm/arm32/arm32_tlb.c: revision 1.4
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23
	sys/arch/arm/arm32/arm32_tlb.c: revision 1.5
	sys/arch/evbarm/conf/BPI: revision 1.8
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24
	sys/arch/arm/arm32/arm32_tlb.c: revision 1.6
	sys/arch/arm/arm32/arm32_tlb.c: revision 1.7
	sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5
	sys/arch/arm/pic/pic.c: revision 1.23
	sys/arch/arm/pic/pic.c: revision 1.24
	sys/arch/arm/pic/picvar.h: revision 1.11
	sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20
	sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16
	sys/arch/arm/arm32/pmap.c: revision 1.298
	sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17
	sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5
	sys/arch/arm/arm32/pmap.c: revision 1.310
	sys/arch/arm/arm32/pmap.c: revision 1.311
	sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32
	sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19
	sys/arch/arm/arm32/arm32_boot.c: revision 1.10
	sys/arch/arm/arm/ast.c: revision 1.25
	sys/arch/arm/include/armreg.h: revision 1.98
	sys/uvm/pmap/pmap_tlb.c: revision 1.10
	sys/arch/arm/arm32/arm32_boot.c: revision 1.8
	sys/arch/arm/arm32/arm32_boot.c: revision 1.9
	sys/arch/arm/arm/arm_machdep.c: revision 1.43
Various ARM MP fixes.

Part of break-before-make is to dsb after the TLB invalidation. Do it in
tlb_invalidate_addr

s/0/KERNEL_PID/

isb after setting TTBCR_S_PD0 as per Example B3-5 Disable non-global
mappings when changing ASID in the ARM ARM.

Sprinkle #include "opt_multiprocessor.h"

armreg_tlbiasid_write -> armreg_tlbiasidis_write

Use tlb is variants for MULTIPROCESSOR

Rebase to HEAD as of a few days ago.

Rebase.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

file arm32_tlb.c was added on branch tls-maxphys on 2014-08-20 00:02:45 +0000

file arm32_tlb.c was added on branch yamt-pagecache on 2014-05-22 11:39:31 +0000

file arm32_tlb.c was added on branch rmind-smpnet on 2014-05-18 17:44:56 +0000

Deal with ASID tagged VIVT icaches (not that we have any cpus with them but...)

Add tlb routines for pmap_tlb.c