CVS log for src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S

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Keyword substitution: kv
Default branch: MAIN

Pull up following revision(s) (requested by skrll in ticket #1555):
	sys/arch/arm/arm/cpufunc_asm_arm11x6.S: 1.10
PR/52934: Yasushi Oshima: Apply the erratum fix that was applied to wbinv_range
to isync_range so that we don't hang when we try to sync from execcmd_readvn().

Pull up following revision(s) (requested by skrll in ticket #507):
	sys/arch/arm/arm/cpufunc_asm_arm11x6.S: revision 1.10
PR/52934: Yasushi Oshima: Apply the erratum fix that was applied to wbinv_range
to isync_range so that we don't hang when we try to sync from execcmd_readvn().
XXX: pullup 8

PR/52934: Yasushi Oshima: Apply the erratum fix that was applied to wbinv_range
to isync_range so that we don't hang when we try to sync from execcmd_readvn().
XXX: pullup 8

update from HEAD

Sync with HEAD

Pull up following revision(s) (requested by skrll in ticket #1452):
	sys/arch/arm/arm32/genassym.cf: revision 1.75
	sys/arch/arm/arm/cpufunc_asm_arm11x6.S: revision 1.8
In idcache_wbinv_range if the range size is bigger than the dcache size
then call idcache_wbinv_all
Avoids a problem with large ranges as seen in
port-evbarm/52169: setting dtrace module to load cause Pi to hang on boot

2264596

file cpufunc_asm_arm11x6.S was added on branch perseant-stdc-iso10646 on 2017-07-15 06:25:21 +0000

Fix a comment

Pull up following revision(s) (requested by skrll in ticket #122):
	sys/arch/arm/arm32/genassym.cf: revision 1.75
	sys/arch/arm/arm/cpufunc_asm_arm11x6.S: revision 1.8
In idcache_wbinv_range if the range size is bigger than the dcache size
then call idcache_wbinv_all
Avoids a problem with large ranges as seen in
port-evbarm/52169: setting dtrace module to load cause Pi to hang on boot

In idcache_wbinv_range if the range size is bigger than the dcache size
then call idcache_wbinv_all

Avoids a problem with large ranges as seen in
port-evbarm/52169: setting dtrace module to load cause Pi to hang on boot

Rebase to HEAD as of a few days ago.

Rebase.

Use lower case.  No functional change.

Fixup some comments.

Trailing whitespace.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Allow for 8KB page size.  Add ARM_MMU_EXTENDED support.
Add missing END()

Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.

sync with head

file cpufunc_asm_arm11x6.S was added on branch matt-nb5-mips64 on 2014-02-15 16:18:35 +0000

Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

Resync to 2012-11-19 00:00:00 UTC

sync with head

file cpufunc_asm_arm11x6.S was added on branch yamt-pagecache on 2012-10-30 17:18:55 +0000

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed.  Default cortex to pmap_needs_fixup = 1.  But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

Pull up revisions:
  src/sys/arch/evbarm/dev/plcomreg.h revisions 1.2,1.3,1.4
  src/sys/arch/evbarm/conf/INTEGRATOR revision 1.65
  src/sys/arch/evbarm/dev/plcom.c revisions 1.34,1.35,1.36,1.37,1.38,1.39,1.40
  src/sys/arch/evbarm/ifpga/plcom_ifpga.c revisions 1.12,1.13,1.14
  src/sys/arch/evbarm/dev/plcomvar.h revisions 1.9,1.10,1.11
  src/sys/arch/evbarm/ifpga/plcom_ifpgavar.h revision 1.2
  src/sys/arch/arm/arm/cpufunc.c revisions 1.105,1.108
  src/sys/arch/arm/arm32/cpu.c revision 1.79
  src/sys/arch/arm/include/armreg.h revisions 1.49,1.54
  src/sys/arch/arm/arm32/pmap.c revision 1.229
  src/sys/arch/arm/arm32/arm32_machdep.c revision 1.77
  src/sys/arch/arm/include/cpu.h revision 1.64
  src/sys/arch/arm/arm/cpufunc_asm_arm1136.S revision 1.3
  src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S revision 1.1
  src/sys/arch/arm/conf/files.arm revision 1.106
  src/sys/arch/arm/include/cpufunc.h revision 1.57
  src/sys/dev/sdmmc/sdhc.c revisions 1.14,1.24
  src/sys/dev/sdmmc/sdhcvar.h revisions 1.7,1.8
  src/sys/arch/evbarm/ifpga/ifpgareg.h revision 1.4
  src/sys/arch/evbarm/integrator/integrator_machdep.c revision 1.69
  src/sys/arch/arm/broadcom/bcm2835_dma.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_emmc.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_intr.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_intr.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_obio.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_plcom.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_pm.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_pmvar.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_space.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_tmr.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835reg.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835var.h revision 1.1
  src/sys/arch/arm/broadcom/bcm_amba.h revision 1.1
  src/sys/arch/arm/broadcom/files.bcm2835 revision 1.1
  src/sys/arch/evbarm/Makefile revision 1.9
  src/sys/arch/evbarm/conf/RPI revision 1.1
  src/sys/arch/evbarm/conf/files.rpi revision 1.1
  src/sys/arch/evbarm/conf/mk.rpi revision 1.1
  src/sys/arch/evbarm/conf/std.rpi revision 1.1
  src/sys/arch/evbarm/rpi/genassym.cf revision 1.1
  src/sys/arch/evbarm/rpi/rpi.h revision 1.1
  src/sys/arch/evbarm/rpi/rpi_machdep.c revision 1.1
  src/sys/arch/evbarm/rpi/rpi_start.S revision 1.1,1.2
  src/etc/etc.evbarm/Makefile.inc revision 1.28
(requested by skrll in ticket #454).

don't mix #define<TAB> and #define<SPACE> in a file.

avoid warning with options PLCOM_DEBUG for INTEGRATOR.

Rename register values. No functional change - same code before and after.

Existing names are prefixed with PL01X_ where they're common between the
PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're
found only on the respective chips.

Replace the simple_lock with a kmutex_t.  Update the locking to match
com(4) in the few places it didn't already.

DOH.  Replace a line that got accidently deleted in the last commit.

device_t/softc split
struct device * -> device_t
struct cfdata * -> cfdata_t

Add the 'Z' to the 1176 cpu product name.

ok matt@

Fix locking botch introduced in 1.36.

Fix a KASSERT. From/OK'ed by matt@

Fix racy softint dispatch that lead to KASSERT(si->si_active) in
softint_execute

Discussed with matt@. "Looks good to me"

Add the documented ARM11[37]6 Auxiliary control register defines.

Add support for the ARM1176JZS

Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that).

Provide a method for attachments to specify capabilites.

Add support for the PL011 to plcom. Pull across a bunch of fixes from
com(4) while I'm here and do some other tidyup.

Tested on a RaspberryPi.

PL010 not tested.

Initial commit of support for the RaspberryPI (www.raspberrypi.org)

This is enough for serial console via the gpio header pins and to get to
multiuser.

A huge thank you to Matt Thomas for all his help.

Add RPI to KERNEL_SETS

Remove #if 0 code.

file cpufunc_asm_arm11x6.S was added on branch netbsd-6 on 2012-08-09 06:36:45 +0000

Add support for the ARM1176JZS