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Annotation of src/sys/arch/arm/arm/cpufunc_asm.S, Revision 1.13.78.1

1.13.78.1! yamt        1: /*     $NetBSD: cpufunc_asm.S,v 1.13 2005/12/11 12:16:41 christos Exp $        */
1.1       bjh21       2:
                      3: /*
                      4:  * Copyright (c) 1997,1998 Mark Brinicombe.
                      5:  * Copyright (c) 1997 Causality Limited
                      6:  * All rights reserved.
                      7:  *
                      8:  * Redistribution and use in source and binary forms, with or without
                      9:  * modification, are permitted provided that the following conditions
                     10:  * are met:
                     11:  * 1. Redistributions of source code must retain the above copyright
                     12:  *    notice, this list of conditions and the following disclaimer.
                     13:  * 2. Redistributions in binary form must reproduce the above copyright
                     14:  *    notice, this list of conditions and the following disclaimer in the
                     15:  *    documentation and/or other materials provided with the distribution.
                     16:  * 3. All advertising materials mentioning features or use of this software
                     17:  *    must display the following acknowledgement:
                     18:  *     This product includes software developed by Causality Limited.
                     19:  * 4. The name of Causality Limited may not be used to endorse or promote
                     20:  *    products derived from this software without specific prior written
                     21:  *    permission.
                     22:  *
                     23:  * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
                     24:  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
                     25:  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
                     26:  * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
                     27:  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
                     28:  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
                     29:  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
                     30:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
                     31:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
                     32:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
                     33:  * SUCH DAMAGE.
                     34:  *
                     35:  * RiscBSD kernel project
                     36:  *
                     37:  * cpufunc.S
                     38:  *
                     39:  * Assembly functions for CPU / MMU / TLB specific operations
                     40:  *
                     41:  * Created      : 30/01/97
                     42:  */
                     43:
                     44: #include <machine/asm.h>
1.13.78.1! yamt       45: #include <machine/cpu.h>
1.1       bjh21      46:
                     47:        .text
                     48:        .align  0
                     49:
                     50: ENTRY(cpufunc_nullop)
1.13.78.1! yamt       51:        RET
1.1       bjh21      52:
                     53: /*
                     54:  * Generic functions to read the internal coprocessor registers
                     55:  *
                     56:  * Currently these registers are :
                     57:  *  c0 - CPU ID
                     58:  *  c5 - Fault status
                     59:  *  c6 - Fault address
                     60:  *
                     61:  */
                     62:
                     63: ENTRY(cpufunc_id)
1.9       rearnsha   64:        mrc     p15, 0, r0, c0, c0, 0
1.13.78.1! yamt       65:        RET
1.1       bjh21      66:
                     67: ENTRY(cpu_get_control)
1.9       rearnsha   68:        mrc     p15, 0, r0, c1, c0, 0
1.13.78.1! yamt       69:        RET
1.12      rearnsha   70:
                     71: ENTRY(cpu_read_cache_config)
                     72:        mrc     p15, 0, r0, c0, c0, 1
1.13.78.1! yamt       73:        RET
1.1       bjh21      74:
                     75: ENTRY(cpufunc_faultstatus)
1.9       rearnsha   76:        mrc     p15, 0, r0, c5, c0, 0
1.13.78.1! yamt       77:        RET
1.1       bjh21      78:
                     79: ENTRY(cpufunc_faultaddress)
1.9       rearnsha   80:        mrc     p15, 0, r0, c6, c0, 0
1.13.78.1! yamt       81:        RET
1.1       bjh21      82:
                     83:
                     84: /*
                     85:  * Generic functions to write the internal coprocessor registers
                     86:  *
                     87:  *
                     88:  * Currently these registers are
                     89:  *  c1 - CPU Control
                     90:  *  c3 - Domain Access Control
                     91:  *
                     92:  * All other registers are CPU architecture specific
                     93:  */
                     94:
1.11      thorpej    95: #if 0 /* See below. */
                     96: ENTRY(cpufunc_control)
1.9       rearnsha   97:        mcr     p15, 0, r0, c1, c0, 0
1.13.78.1! yamt       98:        RET
1.11      thorpej    99: #endif
1.1       bjh21     100:
                    101: ENTRY(cpufunc_domains)
1.9       rearnsha  102:        mcr     p15, 0, r0, c3, c0, 0
1.13.78.1! yamt      103:        RET
1.1       bjh21     104:
                    105: /*
                    106:  * Generic functions to read/modify/write the internal coprocessor registers
                    107:  *
                    108:  *
                    109:  * Currently these registers are
                    110:  *  c1 - CPU Control
                    111:  *
                    112:  * All other registers are CPU architecture specific
                    113:  */
                    114:
                    115: ENTRY(cpufunc_control)
1.9       rearnsha  116:        mrc     p15, 0, r3, c1, c0, 0   /* Read the control register */
1.1       bjh21     117:        bic     r2, r3, r0              /* Clear bits */
                    118:        eor     r2, r2, r1              /* XOR bits */
                    119:
                    120:        teq     r2, r3                  /* Only write if there is a change */
1.9       rearnsha  121:        mcrne   p15, 0, r2, c1, c0, 0   /* Write new control register */
1.1       bjh21     122:        mov     r0, r3                  /* Return old value */
1.13.78.1! yamt      123:        RET
1.1       bjh21     124:
                    125: /*
                    126:  * other potentially useful software functions are:
                    127:  *  clean D cache entry and flush I cache entry
                    128:  *   for the moment use cache_purgeID_E
                    129:  */
1.4       bjh21     130:
                    131: /* Random odd functions */
                    132:
                    133: /*
                    134:  * Function to get the offset of a stored program counter from the
                    135:  * instruction doing the store.  This offset is defined to be the same
                    136:  * for all STRs and STMs on a given implementation.  Code based on
                    137:  * section 2.4.3 of the ARM ARM (2nd Ed.), with modifications to work
                    138:  * in 26-bit modes as well.
                    139:  */
                    140: ENTRY(get_pc_str_offset)
                    141:        mov     ip, sp
1.9       rearnsha  142:        stmfd   sp!, {fp, ip, lr, pc}
1.4       bjh21     143:        sub     fp, ip, #4
                    144:        sub     sp, sp, #4
                    145:        mov     r1, pc          /* R1 = addr of following STR */
                    146:        mov     r0, r0
                    147:        str     pc, [sp]        /* [SP] = . + offset */
                    148:        ldr     r0, [sp]
                    149:        sub     r0, r0, r1
1.9       rearnsha  150:        ldmdb   fp, {fp, sp, pc}