The NetBSD Project

CVS log for src/sys/arch/arm/arm/cpufunc.c

[BACK] Up to [cvs.NetBSD.org] / src / sys / arch / arm / arm

Request diff between arbitrary revisions


Default branch: MAIN
Current tag: MAIN


Revision 1.185 / (download) - annotate - [select for diffs], Thu Dec 22 06:58:07 2022 UTC (14 months, 3 weeks ago) by ryo
Branch: MAIN
CVS Tags: triaxx-drm, thorpej-ifq-base, thorpej-ifq, thorpej-altq-separation-base, thorpej-altq-separation, HEAD
Changes since 1.184: +3 -2 lines
Diff to previous 1.184 (colored)

Explicitly disable overflow interrupts before enabling the cycle counter.

Revision 1.184 / (download) - annotate - [select for diffs], Mon May 16 07:07:17 2022 UTC (22 months ago) by skrll
Branch: MAIN
CVS Tags: netbsd-10-base, bouyer-sunxi-drm-base, bouyer-sunxi-drm
Branch point for: netbsd-10
Changes since 1.183: +5 -4 lines
Diff to previous 1.183 (colored)

port-arm/50635: arm11_setup() cpuctrlmask value causes CPU_CONTROL_VECRELOC bit to toggle

Fix slightly differently to as suggested in the PR.  Annotate arm10_setup
while I'm here.

Revision 1.183 / (download) - annotate - [select for diffs], Sat Nov 27 08:51:01 2021 UTC (2 years, 3 months ago) by skrll
Branch: MAIN
Changes since 1.182: +20 -2 lines
Diff to previous 1.182 (colored)

Apply some errata workarounds for Cortex A17

Revision 1.182 / (download) - annotate - [select for diffs], Sat Nov 13 01:48:12 2021 UTC (2 years, 4 months ago) by jmcneill
Branch: MAIN
Changes since 1.181: +4 -7 lines
Diff to previous 1.181 (colored)

Set ACTLR.SMP=1 on Cortex-A17

Revision 1.181 / (download) - annotate - [select for diffs], Fri Jul 2 07:15:35 2021 UTC (2 years, 8 months ago) by skrll
Branch: MAIN
CVS Tags: thorpej-i2c-spi-conf2-base, thorpej-i2c-spi-conf2, thorpej-i2c-spi-conf-base, thorpej-futex2-base, thorpej-futex2, thorpej-cfargs2-base, thorpej-cfargs2
Changes since 1.180: +5 -5 lines
Diff to previous 1.180 (colored)

Be consistent about #ifndef ARM32_DISABLE_ALIGNMENT_FAULTS.  NFCI.

Revision 1.180 / (download) - annotate - [select for diffs], Sun Jan 31 05:59:55 2021 UTC (3 years, 1 month ago) by skrll
Branch: MAIN
CVS Tags: thorpej-futex-base, thorpej-cfargs-base, thorpej-cfargs, cjep_sun2x-base1, cjep_sun2x-base, cjep_sun2x, cjep_staticlib_x-base1, cjep_staticlib_x-base, cjep_staticlib_x
Branch point for: thorpej-i2c-spi-conf
Changes since 1.179: +2 -3 lines
Diff to previous 1.179 (colored)

One #include "opt_cputypes.h" is enough for anyone

Revision 1.179 / (download) - annotate - [select for diffs], Tue Dec 1 02:46:19 2020 UTC (3 years, 3 months ago) by rin
Branch: MAIN
Changes since 1.178: +16 -10 lines
Diff to previous 1.178 (colored)

Fix earmv6{,hf}eb start-up routines:

- Turn on U-bit in SCTLR before E-bit is turned on by ``setend be'',
  in order to avoid undefined condition. ARM1176JZF-S, at least, halts
  if only E-bit is turned on.

- Turn on EE-bit in SCTLR instead of B-bit as we've switched to BE8.

Revision 1.178 / (download) - annotate - [select for diffs], Fri Oct 30 18:54:36 2020 UTC (3 years, 4 months ago) by skrll
Branch: MAIN
Branch point for: thorpej-futex
Changes since 1.177: +3 -3 lines
Diff to previous 1.177 (colored)

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Revision 1.177 / (download) - annotate - [select for diffs], Fri Jul 10 12:25:08 2020 UTC (3 years, 8 months ago) by skrll
Branch: MAIN
Changes since 1.176: +3 -3 lines
Diff to previous 1.176 (colored)

Add support for KASAN on ARMv[67]

Thanks to maxv for many pointers and reviews.

Revision 1.176 / (download) - annotate - [select for diffs], Wed Feb 5 07:37:35 2020 UTC (4 years, 1 month ago) by skrll
Branch: MAIN
CVS Tags: phil-wifi-20200421, phil-wifi-20200411, phil-wifi-20200406, is-mlppp-base, is-mlppp, bouyer-xenpvh-base2, bouyer-xenpvh-base1, bouyer-xenpvh-base, bouyer-xenpvh, ad-namecache-base3
Changes since 1.175: +3 -3 lines
Diff to previous 1.175 (colored)

Fix the armv[67] memory attributes for uncached memory.  Previously it was
mapped as strongly-ordered which meant that unaligned accesses would fault.

armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO

bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get
mapped to the correct memory attribute bits for armv[67]

DEVMAP_ENTRY usees a new flag PTE_DEV.

The workaround for the unaligned access faults is now removed.

XXX Other armv[67] boards bus_space implementations should be checked.
XXX There is scope to reduce the difference to aarch64

Revision 1.175 / (download) - annotate - [select for diffs], Sat Oct 20 06:35:34 2018 UTC (5 years, 4 months ago) by skrll
Branch: MAIN
CVS Tags: phil-wifi-20191119, phil-wifi-20190609, pgoyette-compat-20190127, pgoyette-compat-20190118, pgoyette-compat-1226, pgoyette-compat-1126, netbsd-9-base, netbsd-9-0-RELEASE, netbsd-9-0-RC2, netbsd-9-0-RC1, isaki-audio2-base, isaki-audio2, ad-namecache-base2, ad-namecache-base1, ad-namecache-base
Branch point for: netbsd-9, ad-namecache
Changes since 1.174: +5 -4 lines
Diff to previous 1.174 (colored)

Clean up around cpu_ttb and fix a bunch of builds

Revision 1.174 / (download) - annotate - [select for diffs], Thu Oct 18 09:01:52 2018 UTC (5 years, 5 months ago) by skrll
Branch: MAIN
CVS Tags: pgoyette-compat-1020
Changes since 1.173: +95 -33 lines
Diff to previous 1.173 (colored)

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors.  AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested.  Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Revision 1.173 / (download) - annotate - [select for diffs], Thu Aug 23 21:01:43 2018 UTC (5 years, 6 months ago) by skrll
Branch: MAIN
CVS Tags: pgoyette-compat-0930, pgoyette-compat-0906
Changes since 1.172: +3 -3 lines
Diff to previous 1.172 (colored)

Whitespace

Revision 1.172 / (download) - annotate - [select for diffs], Wed Aug 15 06:00:02 2018 UTC (5 years, 7 months ago) by skrll
Branch: MAIN
Changes since 1.171: +3 -2 lines
Diff to previous 1.171 (colored)

Sprinkle #include "opt_cputypes.h"

Revision 1.171 / (download) - annotate - [select for diffs], Fri Aug 10 16:17:29 2018 UTC (5 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.170: +6 -214 lines
Diff to previous 1.170 (colored)

Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.

ok jmcneill@ skrll@

Revision 1.170 / (download) - annotate - [select for diffs], Thu Jul 12 12:48:50 2018 UTC (5 years, 8 months ago) by jakllsch
Branch: MAIN
CVS Tags: pgoyette-compat-0728
Changes since 1.169: +2 -3 lines
Diff to previous 1.169 (colored)

<sys/pmc.h> is gone; don't #include it

Revision 1.169 / (download) - annotate - [select for diffs], Thu Jul 12 10:46:42 2018 UTC (5 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.168: +2 -19 lines
Diff to previous 1.168 (colored)

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

 * Removes "options PERFCTRS", the associated includes, and the associated
   ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
   good.

 * Removes the PMC code of ARM XSCALE.

 * Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

 * Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
   definitions are put in sysarch.h.

 * Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
   and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
   netbsd32 and rump.

 * Removes the pmc_evid_t and pmc_ctr_t types.

 * Removes all the associated man pages. The sets are marked as obsolete.

Revision 1.168 / (download) - annotate - [select for diffs], Sun Apr 1 04:35:03 2018 UTC (5 years, 11 months ago) by ryo
Branch: MAIN
CVS Tags: phil-wifi-base, pgoyette-compat-0625, pgoyette-compat-0521, pgoyette-compat-0502, pgoyette-compat-0422, pgoyette-compat-0415, pgoyette-compat-0407
Branch point for: phil-wifi
Changes since 1.167: +21 -2 lines
Diff to previous 1.167 (colored)

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

Revision 1.167 / (download) - annotate - [select for diffs], Sun Oct 22 07:52:40 2017 UTC (6 years, 4 months ago) by skrll
Branch: MAIN
CVS Tags: tls-maxphys-base-20171202, pgoyette-compat-base, pgoyette-compat-0330, pgoyette-compat-0322, pgoyette-compat-0315
Branch point for: pgoyette-compat
Changes since 1.166: +3 -3 lines
Diff to previous 1.166 (colored)

KNF

Revision 1.166 / (download) - annotate - [select for diffs], Sun Aug 27 11:44:49 2017 UTC (6 years, 6 months ago) by skrll
Branch: MAIN
Changes since 1.165: +4 -2 lines
Diff to previous 1.165 (colored)

#ifdef whack-a-mole

Revision 1.165 / (download) - annotate - [select for diffs], Sat Aug 26 07:17:12 2017 UTC (6 years, 6 months ago) by skrll
Branch: MAIN
Changes since 1.164: +28 -20 lines
Diff to previous 1.164 (colored)

Fixup CPU_PJ4B for recent armv7 tlb operation changes.

Revision 1.164 / (download) - annotate - [select for diffs], Thu Aug 24 14:19:36 2017 UTC (6 years, 6 months ago) by jmcneill
Branch: MAIN
CVS Tags: nick-nhusb-base-20170825
Changes since 1.163: +20 -8 lines
Diff to previous 1.163 (colored)

Do runtime detection of MP extensions to allow using a MULTIPROCESSOR
kernel on CPUs without the MP extensions feature (like Cortex-A8).

Revision 1.163 / (download) - annotate - [select for diffs], Sat Jan 28 13:21:11 2017 UTC (7 years, 1 month ago) by jakllsch
Branch: MAIN
CVS Tags: prg-localcount2-base3, prg-localcount2-base2, prg-localcount2-base1, prg-localcount2-base, prg-localcount2, pgoyette-localcount-20170426, pgoyette-localcount-20170320, perseant-stdc-iso10646-base, perseant-stdc-iso10646, nick-nhusb-base-20170204, netbsd-8-base, netbsd-8-2-RELEASE, netbsd-8-1-RELEASE, netbsd-8-1-RC1, netbsd-8-0-RELEASE, netbsd-8-0-RC2, netbsd-8-0-RC1, netbsd-8, matt-nb8-mediatek-base, matt-nb8-mediatek, jdolecek-ncq-base, jdolecek-ncq, bouyer-socketcan-base1
Changes since 1.162: +3 -3 lines
Diff to previous 1.162 (colored)

Drop inadvertent redundant CPU_CONTROL_MMU_ENABLE ((1 < 22)) for PJ4Bv7.

This was intended to be CPU_CONTROL_UNAL_ENABLE, which is already handled.

Should fix PR kern/51921.

Revision 1.162 / (download) - annotate - [select for diffs], Tue Oct 18 13:58:52 2016 UTC (7 years, 5 months ago) by kiyohara
Branch: MAIN
CVS Tags: pgoyette-localcount-20170107, pgoyette-localcount-20161104, nick-nhusb-base-20161204, bouyer-socketcan-base
Branch point for: bouyer-socketcan
Changes since 1.161: +7 -7 lines
Diff to previous 1.161 (colored)

Indent.

Revision 1.161 / (download) - annotate - [select for diffs], Mon May 30 17:18:38 2016 UTC (7 years, 9 months ago) by dholland
Branch: MAIN
CVS Tags: pgoyette-localcount-base, pgoyette-localcount-20160806, pgoyette-localcount-20160726, nick-nhusb-base-20161004, nick-nhusb-base-20160907, localcount-20160914
Branch point for: pgoyette-localcount
Changes since 1.160: +3 -4 lines
Diff to previous 1.160 (colored)

PR 50669 David Binderman: remove dead code

Revision 1.160 / (download) - annotate - [select for diffs], Sat Jan 23 21:39:17 2016 UTC (8 years, 1 month ago) by christos
Branch: MAIN
CVS Tags: nick-nhusb-base-20160529, nick-nhusb-base-20160422, nick-nhusb-base-20160319
Changes since 1.159: +6 -6 lines
Diff to previous 1.159 (colored)

Rename the cpu_id() define to cpu_idnum() so that it does not conflict with
dtrace and friends.

Revision 1.159 / (download) - annotate - [select for diffs], Thu Dec 10 22:04:54 2015 UTC (8 years, 3 months ago) by skrll
Branch: MAIN
CVS Tags: nick-nhusb-base-20151226
Changes since 1.158: +3 -3 lines
Diff to previous 1.158 (colored)

PR port-arm/50512: Source code condition impossible

Fix condition which broke ARM1136 function selection when ARM1176 support
was added

Revision 1.158 / (download) - annotate - [select for diffs], Wed Nov 25 08:39:45 2015 UTC (8 years, 3 months ago) by skrll
Branch: MAIN
Changes since 1.157: +2 -13 lines
Diff to previous 1.157 (colored)

G/C TEGRAK1_PMAP_WORKAROUND.

Using XN (eXecute Never) properly means speculative reads from devices
aren't done.  Pretty sure this was the cause of the wedges.

Revision 1.157 / (download) - annotate - [select for diffs], Thu Oct 15 07:13:50 2015 UTC (8 years, 5 months ago) by skrll
Branch: MAIN
Changes since 1.156: +13 -2 lines
Diff to previous 1.156 (colored)

Setting actlr.bit15=1 (Force in order issue in the branch execution unit)
makes my jetson tk1 stable.  Apply this workaround until we figure out
what the real problem is.

Revision 1.156 / (download) - annotate - [select for diffs], Thu Jul 2 08:33:31 2015 UTC (8 years, 8 months ago) by skrll
Branch: MAIN
CVS Tags: nick-nhusb-base-20150921
Changes since 1.155: +13 -17 lines
Diff to previous 1.155 (colored)

Use armreg_*_{read,write} instead of handcrafted asm

No functional change.

Revision 1.155 / (download) - annotate - [select for diffs], Wed Jun 3 02:30:11 2015 UTC (8 years, 9 months ago) by hsuenaga
Branch: MAIN
CVS Tags: nick-nhusb-base-20150606
Changes since 1.154: +6 -2 lines
Diff to previous 1.154 (colored)

initialize sdcache operations for PJ4B.
otherwise the kernel crashes without 'options L2CACHE_ENABLE.'

Revision 1.154 / (download) - annotate - [select for diffs], Thu May 14 05:39:32 2015 UTC (8 years, 10 months ago) by hsuenaga
Branch: MAIN
Changes since 1.153: +36 -16 lines
Diff to previous 1.153 (colored)

add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.

Revision 1.153 / (download) - annotate - [select for diffs], Fri Apr 17 13:39:01 2015 UTC (8 years, 11 months ago) by hsuenaga
Branch: MAIN
Changes since 1.152: +5 -3 lines
Diff to previous 1.152 (colored)

don't call L2 maintance function if L2 cache is disabled.

Revision 1.152 / (download) - annotate - [select for diffs], Wed Apr 15 10:52:18 2015 UTC (8 years, 11 months ago) by hsuenaga
Branch: MAIN
Changes since 1.151: +37 -21 lines
Diff to previous 1.151 (colored)

clean up cpufuncs of CPU_PJ4B.

PJ4B is a ARMv7 compatible CPU, so most of cpufuncs are just redundant.
we need funcs for:
  - Marvell specific registers
  - workaround of errata
  - and Marvell specific L2 cache maintainance
if I/O coherency fabric is enabled(option AURORA_IO_CACHE_COHERENCY),
probaly we don't need to maintain L2 cache by software.

Revision 1.151 / (download) - annotate - [select for diffs], Wed Feb 25 13:52:42 2015 UTC (9 years ago) by joerg
Branch: MAIN
CVS Tags: nick-nhusb-base-20150406
Changes since 1.150: +4 -4 lines
Diff to previous 1.150 (colored)

Improve inline asm around dsb/dmb/isb:
- always use volatile and mark them as memory barrier
- use the common version from locore.h in all places not included from
  userland

Revision 1.150 / (download) - annotate - [select for diffs], Thu Jul 31 07:14:42 2014 UTC (9 years, 7 months ago) by skrll
Branch: MAIN
CVS Tags: tls-maxphys-base, tls-earlyentropy-base, nick-nhusb-base, netbsd-7-base
Branch point for: nick-nhusb, netbsd-7
Changes since 1.149: +5 -5 lines
Diff to previous 1.149 (colored)

Trailing whitespace.

Revision 1.149 / (download) - annotate - [select for diffs], Wed Jul 30 20:52:18 2014 UTC (9 years, 7 months ago) by skrll
Branch: MAIN
Changes since 1.148: +18 -3 lines
Diff to previous 1.148 (colored)

Apply some errata workarounds

Revision 1.148 / (download) - annotate - [select for diffs], Sun Jul 27 21:31:34 2014 UTC (9 years, 7 months ago) by skrll
Branch: MAIN
Changes since 1.147: +4 -3 lines
Diff to previous 1.147 (colored)

More fixes as a step towards ARM_MMU_EXTENDED on RPI.

- don't set CPU_CONTROL_SYST_ENABLE in arm11x6_setup for ARM_MMU_EXTENDED

- Use the new MMU defines for V6N

- pull in arm/cpuconf.h in vmparam s that VM_MAXUSER_ADDRESS gets set
  correctly.

Revision 1.147 / (download) - annotate - [select for diffs], Fri Apr 18 23:50:59 2014 UTC (9 years, 11 months ago) by christos
Branch: MAIN
CVS Tags: yamt-pagecache-base9, rmind-smpnet-nbase, rmind-smpnet-base
Changes since 1.146: +3 -3 lines
Diff to previous 1.146 (colored)

Include cpufunc_proto.h before locore.h so that we define cpu_cpwait first.
XXX: this is a mess.

Revision 1.146 / (download) - annotate - [select for diffs], Mon Apr 14 20:50:46 2014 UTC (9 years, 11 months ago) by matt
Branch: MAIN
Changes since 1.145: +38 -22 lines
Diff to previous 1.145 (colored)

Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.

Revision 1.145 / (download) - annotate - [select for diffs], Thu Apr 10 02:49:42 2014 UTC (9 years, 11 months ago) by matt
Branch: MAIN
Changes since 1.144: +15 -14 lines
Diff to previous 1.144 (colored)

change cortex_cpufunc to armv7_cpufuncs.  CPU_CORTEX -> CPU_ARMV7

Revision 1.144 / (download) - annotate - [select for diffs], Sun Mar 30 23:20:14 2014 UTC (9 years, 11 months ago) by matt
Branch: MAIN
CVS Tags: riastradh-xf86-video-intel-2-7-1-pre-2-21-15
Branch point for: tls-earlyentropy
Changes since 1.143: +13 -7 lines
Diff to previous 1.143 (colored)

arm11 ARM_MMU_EXTENDED support (setting CPU_CONTROL_XP_ENABLE)

Revision 1.143 / (download) - annotate - [select for diffs], Sun Mar 30 08:36:21 2014 UTC (9 years, 11 months ago) by skrll
Branch: MAIN
Changes since 1.142: +3 -3 lines
Diff to previous 1.142 (colored)

Use arm11_setttb for arm1176 as well.

Revision 1.142 / (download) - annotate - [select for diffs], Sat Mar 29 23:44:37 2014 UTC (9 years, 11 months ago) by matt
Branch: MAIN
Changes since 1.141: +10 -19 lines
Diff to previous 1.141 (colored)

cortex doesn't need xscale_setup
use arm11_setttb for arm11x6.

Revision 1.141 / (download) - annotate - [select for diffs], Fri Mar 28 21:49:22 2014 UTC (9 years, 11 months ago) by matt
Branch: MAIN
Changes since 1.140: +33 -12 lines
Diff to previous 1.140 (colored)

Initialize cache way_size and sets

Revision 1.140 / (download) - annotate - [select for diffs], Fri Feb 21 06:28:25 2014 UTC (10 years ago) by matt
Branch: MAIN
CVS Tags: riastradh-drm2-base3
Changes since 1.139: +4 -3 lines
Diff to previous 1.139 (colored)

For now, don't reset arm_cache_prefer_mask unless both l1 caches are PIPT

Revision 1.139 / (download) - annotate - [select for diffs], Thu Feb 20 23:24:55 2014 UTC (10 years ago) by matt
Branch: MAIN
Changes since 1.138: +44 -13 lines
Diff to previous 1.138 (colored)

Keep track of what each cache is (VIVT/VIPT/PIPT).

cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache

Revision 1.138 / (download) - annotate - [select for diffs], Thu Feb 20 17:38:42 2014 UTC (10 years ago) by matt
Branch: MAIN
Changes since 1.137: +7 -7 lines
Diff to previous 1.137 (colored)

armv7 doens't need to use the arm11 routines anymore.

Revision 1.137 / (download) - annotate - [select for diffs], Thu Feb 20 14:48:11 2014 UTC (10 years ago) by matt
Branch: MAIN
Changes since 1.136: +7 -14 lines
Diff to previous 1.136 (colored)

Make sure AFLT_ENABLE in the cpuctrl mask for armv7_setup.

Revision 1.136 / (download) - annotate - [select for diffs], Thu Jan 23 19:28:47 2014 UTC (10 years, 1 month ago) by matt
Branch: MAIN
Changes since 1.135: +9 -5 lines
Diff to previous 1.135 (colored)

For armv7, CPU_CONTROL_UNAL_ENABLE is MBO/SBPO.
Make sure CPU_CONTROL_EX_BEND is set for big endian kernels.
Don't clear bits we aren't setting.

Revision 1.135 / (download) - annotate - [select for diffs], Tue Jan 21 19:05:10 2014 UTC (10 years, 1 month ago) by christos
Branch: MAIN
Changes since 1.134: +43 -43 lines
Diff to previous 1.134 (colored)

- comment out set but not used variables.
- make commenting out the cpuctrlmask consistent

Revision 1.134 / (download) - annotate - [select for diffs], Sun Jan 12 19:37:43 2014 UTC (10 years, 2 months ago) by joerg
Branch: MAIN
Changes since 1.133: +3 -3 lines
Diff to previous 1.133 (colored)

Improve assembler syntax.

Revision 1.133 / (download) - annotate - [select for diffs], Sat Jan 4 02:58:38 2014 UTC (10 years, 2 months ago) by joerg
Branch: MAIN
Changes since 1.132: +3 -3 lines
Diff to previous 1.132 (colored)

Add missing volatile for hidden side effects of asm.

Revision 1.132 / (download) - annotate - [select for diffs], Fri Dec 20 06:48:09 2013 UTC (10 years, 3 months ago) by matt
Branch: MAIN
Changes since 1.131: +13 -2 lines
Diff to previous 1.131 (colored)

Add CPU_IS_ARMV6_P() macro

Revision 1.131 / (download) - annotate - [select for diffs], Wed Dec 18 12:52:47 2013 UTC (10 years, 3 months ago) by skrll
Branch: MAIN
Changes since 1.130: +10 -6 lines
Diff to previous 1.130 (colored)

Remove unused variables.

Revision 1.130 / (download) - annotate - [select for diffs], Tue Nov 12 17:31:55 2013 UTC (10 years, 4 months ago) by matt
Branch: MAIN
Changes since 1.129: +8 -8 lines
Diff to previous 1.129 (colored)

Make sure CPU_CONTROL_UNAL_ENABLE is enabled for armv7 cpus (should be
already but ...)

Revision 1.129 / (download) - annotate - [select for diffs], Tue Nov 12 17:14:39 2013 UTC (10 years, 4 months ago) by skrll
Branch: MAIN
Changes since 1.128: +3 -2 lines
Diff to previous 1.128 (colored)

Add CPU_CONTROL_UNAL_ENABLE. New ABIs demand unaligned accesses!

Revision 1.128 / (download) - annotate - [select for diffs], Wed Nov 6 02:36:36 2013 UTC (10 years, 4 months ago) by christos
Branch: MAIN
Changes since 1.127: +9 -7 lines
Diff to previous 1.127 (colored)

ifdef notyet code.

Revision 1.127 / (download) - annotate - [select for diffs], Wed Oct 23 20:28:11 2013 UTC (10 years, 4 months ago) by skrll
Branch: MAIN
Changes since 1.126: +6 -4 lines
Diff to previous 1.126 (colored)

Fix PR/48332 by reverting to passing 0xffffffff as the cpuctrlmask.
Comment out the cpuctrlmask that doesn't work for the imx23_olinuxino
leaving it there for reference.

Revision 1.126 / (download) - annotate - [select for diffs], Sun Oct 20 09:30:41 2013 UTC (10 years, 5 months ago) by skrll
Branch: MAIN
Changes since 1.125: +4 -4 lines
Diff to previous 1.125 (colored)

Use cpuctrlmask in the arm1[01] case.

Revision 1.125 / (download) - annotate - [select for diffs], Sun Aug 18 07:57:27 2013 UTC (10 years, 7 months ago) by matt
Branch: MAIN
Changes since 1.124: +12 -2 lines
Diff to previous 1.124 (colored)

Add a CPU_IS_ARMV7_P() macro (nonv7 evals to false, v7 only true, otherwise
cpu_armv7_p is checked (and is set by cpuconf for cortex and pj4b).

Revision 1.124 / (download) - annotate - [select for diffs], Sun Aug 18 06:50:31 2013 UTC (10 years, 7 months ago) by matt
Branch: MAIN
Changes since 1.123: +3 -2 lines
Diff to previous 1.123 (colored)

Include <arm/locore.h>

Revision 1.123 / (download) - annotate - [select for diffs], Tue Jun 18 15:27:05 2013 UTC (10 years, 9 months ago) by matt
Branch: MAIN
CVS Tags: riastradh-drm2-base2, riastradh-drm2-base1, riastradh-drm2-base, riastradh-drm2
Branch point for: rmind-smpnet
Changes since 1.122: +28 -2 lines
Diff to previous 1.122 (colored)

Only set CPU_CONTROL_VECRELOC if ARM_HAS_VBAR is not defined.

Revision 1.122 / (download) - annotate - [select for diffs], Wed Jun 12 01:16:48 2013 UTC (10 years, 9 months ago) by matt
Branch: MAIN
Changes since 1.121: +3 -3 lines
Diff to previous 1.121 (colored)

Nuke cpu_pfr, just use the armreg_pfr?_read inlines

Revision 1.121 / (download) - annotate - [select for diffs], Wed Jun 12 00:35:34 2013 UTC (10 years, 9 months ago) by matt
Branch: MAIN
Changes since 1.120: +5 -3 lines
Diff to previous 1.120 (colored)

If the L1 instruction cache policy is PIPT, don't set the prefer_mask.

Revision 1.120 / (download) - annotate - [select for diffs], Sun May 19 15:37:06 2013 UTC (10 years, 10 months ago) by rkujawa
Branch: MAIN
Changes since 1.119: +114 -4 lines
Diff to previous 1.119 (colored)

Plug support for PJ4B core into our ARM CPU support infrastructure.

Obtained from Marvell, Semihalf.

Revision 1.119 / (download) - annotate - [select for diffs], Fri Dec 28 03:48:00 2012 UTC (11 years, 2 months ago) by msaitoh
Branch: MAIN
CVS Tags: yamt-pagecache-base8, khorben-n900, agc-symver-base, agc-symver
Changes since 1.118: +12 -2 lines
Diff to previous 1.118 (colored)

Enable DCache Streaming Switch and Write Allocate for Sheeva CPU.
This change improve system performance significantly.

Revision 1.118 / (download) - annotate - [select for diffs], Mon Nov 12 18:00:34 2012 UTC (11 years, 4 months ago) by skrll
Branch: MAIN
CVS Tags: yamt-pagecache-base7
Changes since 1.117: +4 -4 lines
Diff to previous 1.117 (colored)

C99 types

Revision 1.117 / (download) - annotate - [select for diffs], Fri Oct 19 13:47:03 2012 UTC (11 years, 5 months ago) by matt
Branch: MAIN
CVS Tags: yamt-pagecache-base6
Changes since 1.116: +3 -3 lines
Diff to previous 1.116 (colored)

Add armv7_drain_writebuf (which is just a dsb).

Revision 1.116 / (download) - annotate - [select for diffs], Tue Sep 11 17:51:38 2012 UTC (11 years, 6 months ago) by matt
Branch: MAIN
Branch point for: tls-maxphys
Changes since 1.115: +86 -2 lines
Diff to previous 1.115 (colored)

Add secondary cache range ops

Revision 1.115 / (download) - annotate - [select for diffs], Fri Sep 7 11:48:59 2012 UTC (11 years, 6 months ago) by matt
Branch: MAIN
Changes since 1.114: +77 -63 lines
Diff to previous 1.114 (colored)

Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

Revision 1.114 / (download) - annotate - [select for diffs], Fri Sep 7 04:39:14 2012 UTC (11 years, 6 months ago) by matt
Branch: MAIN
Changes since 1.113: +22 -23 lines
Diff to previous 1.113 (colored)

Change _l2_ to _log2_ to make sure they don't confused with level 2.

Revision 1.113 / (download) - annotate - [select for diffs], Wed Aug 29 18:37:14 2012 UTC (11 years, 6 months ago) by matt
Branch: MAIN
Changes since 1.112: +2 -49 lines
Diff to previous 1.112 (colored)

Recode armv7_dcache_wbinv_all in asm.  Add armv7_dcache_inv_all and
armv7_icache_inv_all as well.
Use dsb/dmb/isb instructions

Revision 1.112 / (download) - annotate - [select for diffs], Wed Aug 29 18:29:04 2012 UTC (11 years, 6 months ago) by matt
Branch: MAIN
Changes since 1.111: +11 -3 lines
Diff to previous 1.111 (colored)

always start PMC cycle counter for ARM11 and Cortex.

Revision 1.111 / (download) - annotate - [select for diffs], Wed Aug 29 07:14:03 2012 UTC (11 years, 6 months ago) by matt
Branch: MAIN
Changes since 1.110: +2 -34 lines
Diff to previous 1.110 (colored)

Rename ARM options PROCESS_ID_IS_CUR{CPU,LWP} to TPIDRPRW_IS_CUR{CPU,LWP}
since TPIDRPRW is the cp15 register name.
Initialize it early in start along with CI_ARM_CPUID.
Remove other initializations.
We alays have ci_curlwp.
Enable TIPRPRW_IS_CURCPU in std.beagle.
[tested on a beaglboard (cortex-a8)]

Revision 1.110 / (download) - annotate - [select for diffs], Thu Aug 16 18:22:38 2012 UTC (11 years, 7 months ago) by matt
Branch: MAIN
Changes since 1.109: +2 -26 lines
Diff to previous 1.109 (colored)

Move the standard definitions of the {UND,IRQ,FIQ,ABT}_STACK_SIZE to
<arm32/machdep.h>
Move the extern for cpu_reset_address to the same file.
Add cpu_reset_address_paddr.
Kill cpu_reset_v4_MMU_disable.
if cpu_reset_address is NULL, then the MMU will be disabled.

Revision 1.109 / (download) - annotate - [select for diffs], Mon Jul 23 15:51:48 2012 UTC (11 years, 7 months ago) by skrll
Branch: MAIN
Changes since 1.108: +4 -4 lines
Diff to previous 1.108 (colored)

Make auxiliary register naming consistent for the 1136.

Revision 1.108 / (download) - annotate - [select for diffs], Sat Jul 21 12:19:15 2012 UTC (11 years, 8 months ago) by skrll
Branch: MAIN
Changes since 1.107: +94 -21 lines
Diff to previous 1.107 (colored)

Add support for the ARM1176JZS

Revision 1.107 / (download) - annotate - [select for diffs], Sat Jul 14 12:59:55 2012 UTC (11 years, 8 months ago) by hans
Branch: MAIN
Changes since 1.106: +4 -3 lines
Diff to previous 1.106 (colored)

Support cpu_sleep() on Sheeva CPUs.

Revision 1.106 / (download) - annotate - [select for diffs], Fri Jul 13 05:23:30 2012 UTC (11 years, 8 months ago) by matt
Branch: MAIN
Changes since 1.105: +3 -6 lines
Diff to previous 1.105 (colored)

Begin support for Cortex A5, A7, A15 and expand A8 and A9 definitions.
Instead of testing all possible CPUids for a cortex, we know what range
a cortex will be so mask out the insignificant parts and do a single test.

Revision 1.105 / (download) - annotate - [select for diffs], Sun May 20 17:56:30 2012 UTC (11 years, 10 months ago) by skrll
Branch: MAIN
CVS Tags: yamt-pagecache-base5, jmcneill-usbmp-base10
Changes since 1.104: +4 -4 lines
Diff to previous 1.104 (colored)

Add the 'Z' to the 1176 cpu product name.

ok matt@

Revision 1.104 / (download) - annotate - [select for diffs], Tue Jan 31 04:31:37 2012 UTC (12 years, 1 month ago) by matt
Branch: MAIN
CVS Tags: yamt-pagecache-base4, netbsd-6-base, jmcneill-usbmp-base9, jmcneill-usbmp-base8, jmcneill-usbmp-base7, jmcneill-usbmp-base6, jmcneill-usbmp-base5, jmcneill-usbmp-base4, jmcneill-usbmp-base3, jmcneill-usbmp-base2
Branch point for: netbsd-6
Changes since 1.103: +5 -6 lines
Diff to previous 1.103 (colored)

Convert stragglers to use real C89 prototypes.

Revision 1.103 / (download) - annotate - [select for diffs], Thu Mar 10 08:06:27 2011 UTC (13 years ago) by bsh
Branch: MAIN
CVS Tags: yamt-pagecache-base3, yamt-pagecache-base2, yamt-pagecache-base, rmind-uvmplock-nbase, rmind-uvmplock-base, jym-xensuspend-nbase, jym-xensuspend-base, jmcneill-usbmp-pre-base2, jmcneill-usbmp-base, jmcneill-audiomp3-base, jmcneill-audiomp3, cherry-xenmp-base, cherry-xenmp
Branch point for: yamt-pagecache, jmcneill-usbmp
Changes since 1.102: +4 -2 lines
Diff to previous 1.102 (colored)

add MPCore to CPU-ID table
add branch predict bit to arm11_options

Revision 1.102 / (download) - annotate - [select for diffs], Thu Mar 10 07:47:14 2011 UTC (13 years ago) by bsh
Branch: MAIN
Changes since 1.101: +137 -2 lines
Diff to previous 1.101 (colored)

Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.

Revision 1.101 / (download) - annotate - [select for diffs], Sat Oct 2 05:37:58 2010 UTC (13 years, 5 months ago) by kiyohara
Branch: MAIN
CVS Tags: yamt-nfs-mp-base11, uebayasi-xip-base7, uebayasi-xip-base6, uebayasi-xip-base5, uebayasi-xip-base4, uebayasi-xip-base3, matt-mips64-premerge-20101231, jruoho-x86intr-base, bouyer-quota2-nbase, bouyer-quota2-base, bouyer-quota2
Branch point for: jruoho-x86intr
Changes since 1.100: +131 -4 lines
Diff to previous 1.100 (colored)

Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
  Discovery Innovation not yet.

Revision 1.100 / (download) - annotate - [select for diffs], Thu Sep 23 07:31:10 2010 UTC (13 years, 5 months ago) by kiyohara
Branch: MAIN
Changes since 1.99: +24 -24 lines
Diff to previous 1.99 (colored)

Replace some whitespaces to Tab.

Revision 1.99 / (download) - annotate - [select for diffs], Mon Jul 5 06:54:48 2010 UTC (13 years, 8 months ago) by kiyohara
Branch: MAIN
CVS Tags: yamt-nfs-mp-base10, uebayasi-xip-base2
Changes since 1.98: +47 -47 lines
Diff to previous 1.98 (colored)

Remove unnecessary white-spaces.

Revision 1.98 / (download) - annotate - [select for diffs], Mon Jul 5 06:50:01 2010 UTC (13 years, 8 months ago) by kiyohara
Branch: MAIN
Changes since 1.97: +6 -3 lines
Diff to previous 1.97 (colored)

Fix set the control register.

Revision 1.97 / (download) - annotate - [select for diffs], Sat Jun 19 20:42:43 2010 UTC (13 years, 9 months ago) by matt
Branch: MAIN
Changes since 1.96: +19 -9 lines
Diff to previous 1.96 (colored)

Fix cache probing on Cortex.  Add missing CORTEX dependency in cpu.c

Revision 1.96 / (download) - annotate - [select for diffs], Sat Jun 19 19:44:57 2010 UTC (13 years, 9 months ago) by matt
Branch: MAIN
Changes since 1.95: +25 -22 lines
Diff to previous 1.95 (colored)

Cleanup the armv7 changes.  Add ARM_ARCH_7.   Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well.  Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

Revision 1.95 / (download) - annotate - [select for diffs], Wed Jun 16 22:06:53 2010 UTC (13 years, 9 months ago) by jmcneill
Branch: MAIN
Changes since 1.94: +208 -19 lines
Diff to previous 1.94 (colored)

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

Revision 1.94 / (download) - annotate - [select for diffs], Sun Dec 27 05:14:56 2009 UTC (14 years, 2 months ago) by uebayasi
Branch: MAIN
CVS Tags: yamt-nfs-mp-base9, uebayasi-xip-base1, uebayasi-xip-base
Branch point for: uebayasi-xip, rmind-uvmplock
Changes since 1.93: +6 -2 lines
Diff to previous 1.93 (colored)

Add write-through cache work-around for ARM11 as well as ARM9/ARM10.  Analyzed
& tested on i.MX35 with help from Tsubai Masanari.

Revision 1.93 / (download) - annotate - [select for diffs], Sun Mar 15 22:23:16 2009 UTC (15 years ago) by cegger
Branch: MAIN
CVS Tags: yamt-nfs-mp-base8, yamt-nfs-mp-base7, yamt-nfs-mp-base6, yamt-nfs-mp-base5, yamt-nfs-mp-base4, yamt-nfs-mp-base3, nick-hppapmap-base4, nick-hppapmap-base3, nick-hppapmap-base, matt-premerge-20091211, jymxensuspend-base
Changes since 1.92: +5 -8 lines
Diff to previous 1.92 (colored)

ansify function definitions

Revision 1.92 / (download) - annotate - [select for diffs], Sat Mar 14 15:36:01 2009 UTC (15 years ago) by dsl
Branch: MAIN
Changes since 1.91: +16 -30 lines
Diff to previous 1.91 (colored)

Change about 4500 of the K&R function definitions to ANSI ones.
There are still about 1600 left, but they have ',' or /* ... */
in the actual variable definitions - which my awk script doesn't handle.
There are also many that need () -> (void).
(The script does handle misordered arguments.)

Revision 1.91 / (download) - annotate - [select for diffs], Sat Mar 14 14:45:54 2009 UTC (15 years ago) by dsl
Branch: MAIN
Changes since 1.90: +4 -4 lines
Diff to previous 1.90 (colored)

Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

Revision 1.90 / (download) - annotate - [select for diffs], Fri Dec 12 18:13:55 2008 UTC (15 years, 3 months ago) by matt
Branch: MAIN
CVS Tags: nick-hppapmap-base2, mjf-devfs2-base
Branch point for: jym-xensuspend
Changes since 1.89: +8 -5 lines
Diff to previous 1.89 (colored)

Fix merge botch from april...

Revision 1.89 / (download) - annotate - [select for diffs], Wed Oct 15 16:56:49 2008 UTC (15 years, 5 months ago) by matt
Branch: MAIN
CVS Tags: netbsd-5-base, netbsd-5-2-RELEASE, netbsd-5-2-RC1, netbsd-5-2-3-RELEASE, netbsd-5-2-2-RELEASE, netbsd-5-2-1-RELEASE, netbsd-5-2, netbsd-5-1-RELEASE, netbsd-5-1-RC4, netbsd-5-1-RC3, netbsd-5-1-RC2, netbsd-5-1-RC1, netbsd-5-1-5-RELEASE, netbsd-5-1-4-RELEASE, netbsd-5-1-3-RELEASE, netbsd-5-1-2-RELEASE, netbsd-5-1-1-RELEASE, netbsd-5-1, netbsd-5-0-RELEASE, netbsd-5-0-RC4, netbsd-5-0-RC3, netbsd-5-0-RC2, netbsd-5-0-RC1, netbsd-5-0-2-RELEASE, netbsd-5-0-1-RELEASE, netbsd-5-0, netbsd-5, matt-nb5-pq3-base, matt-nb5-pq3, matt-nb5-mips64-u2-k2-k4-k7-k8-k9, matt-nb5-mips64-u1-k1-k5, matt-nb5-mips64-premerge-20101231, matt-nb5-mips64-premerge-20091211, matt-nb5-mips64-k15, matt-nb4-mips64-k7-u2a-k9b, matt-mips64-base2, haad-nbase2, haad-dm-base2, haad-dm-base1, haad-dm-base, ad-audiomp2-base, ad-audiomp2
Branch point for: nick-hppapmap, matt-nb5-mips64
Changes since 1.88: +3 -3 lines
Diff to previous 1.88 (colored)

Add fa526_flush_prefetchbuf

Revision 1.88 / (download) - annotate - [select for diffs], Tue Oct 14 16:01:22 2008 UTC (15 years, 5 months ago) by matt
Branch: MAIN
Changes since 1.87: +129 -5 lines
Diff to previous 1.87 (colored)

Add FA526 support (compile tested only)

Revision 1.87 / (download) - annotate - [select for diffs], Wed Aug 27 11:07:49 2008 UTC (15 years, 6 months ago) by matt
Branch: MAIN
CVS Tags: wrstuden-revivesa-base-4, wrstuden-revivesa-base-3, wrstuden-revivesa-base-2
Changes since 1.86: +34 -3 lines
Diff to previous 1.86 (colored)

Add support Cortex-A8.  Pretend they are ARM11s.  Support new cache sizing
method introduced with Cortex-A8.

Revision 1.86 / (download) - annotate - [select for diffs], Tue Jul 22 07:07:23 2008 UTC (15 years, 8 months ago) by matt
Branch: MAIN
CVS Tags: simonb-wapbl-nbase, simonb-wapbl-base
Changes since 1.85: +31 -2 lines
Diff to previous 1.85 (colored)

Implement workaround for:
arm11 Errata 364296:Possible Cache Data Corruption with Hit-Under-Miss

Remove hack in userret which is redundant with workaround.

workaround code from <imre.deak@teleca.com>

Revision 1.85 / (download) - annotate - [select for diffs], Sun Jul 13 09:12:14 2008 UTC (15 years, 8 months ago) by chris
Branch: MAIN
Changes since 1.84: +2 -11 lines
Diff to previous 1.84 (colored)

Remove repeated setting of cpuctl bit for vectors being high in cpu setup
code.

Pointed out in private email by Kevin Lo.

Revision 1.84 / (download) - annotate - [select for diffs], Sun Apr 27 18:58:43 2008 UTC (15 years, 10 months ago) by matt
Branch: MAIN
CVS Tags: yamt-pf42-base4, yamt-pf42-base3, yamt-pf42-base2, yamt-nfs-mp-base2, wrstuden-revivesa-base-1, wrstuden-revivesa-base, hpcarm-cleanup-nbase
Branch point for: wrstuden-revivesa, simonb-wapbl, haad-dm
Changes since 1.83: +194 -24 lines
Diff to previous 1.83 (colored)

Merge kernel changes in matt-armv6 to HEAD.

Revision 1.83 / (download) - annotate - [select for diffs], Sat Mar 15 10:35:30 2008 UTC (16 years ago) by rearnsha
Branch: MAIN
CVS Tags: yamt-pf42-baseX, yamt-pf42-base, yamt-nfs-mp-base, yamt-lazymbuf-base15, yamt-lazymbuf-base14, matt-armv6-nbase, keiichi-mipv6-nbase, keiichi-mipv6-base, chris-arm-intr-rework-base7, ad-socklock-base1
Branch point for: yamt-pf42, yamt-nfs-mp
Changes since 1.82: +5 -2 lines
Diff to previous 1.82 (colored)

Allow detection of VFP devices on ARM11 cores.

Revision 1.82 / (download) - annotate - [select for diffs], Sun Feb 24 20:50:38 2008 UTC (16 years ago) by matt
Branch: MAIN
CVS Tags: hpcarm-cleanup-base
Changes since 1.81: +5 -2 lines
Diff to previous 1.81 (colored)

allow arm11 to use high vectors.

Revision 1.81 / (download) - annotate - [select for diffs], Sun Apr 15 20:29:21 2007 UTC (16 years, 11 months ago) by matt
Branch: MAIN
CVS Tags: yamt-x86pmap-base4, yamt-x86pmap-base3, yamt-x86pmap-base2, yamt-x86pmap-base, yamt-x86pmap, yamt-kmem-base3, yamt-kmem-base2, yamt-kmem-base, yamt-kmem, yamt-idlelwp-base8, vmlocking2-base3, vmlocking2-base2, vmlocking2-base1, vmlocking2, vmlocking-nbase, vmlocking-base, reinoud-bufcleanup-nbase, reinoud-bufcleanup-base, ppcoea-renovation-base, ppcoea-renovation, nick-net80211-sync-base, nick-net80211-sync, nick-csl-alignment-base5, nick-csl-alignment-base, nick-csl-alignment, mjf-ufs-trans-base, mjf-devfs-base, mjf-devfs, matt-mips64-base, matt-mips64, matt-armv6-base, jmcneill-pm-base, jmcneill-pm, jmcneill-base, cube-autoconf-base, cube-autoconf, chris-arm-intr-rework-base6, chris-arm-intr-rework-base5, chris-arm-intr-rework-base4, chris-arm-intr-rework-base3, chris-arm-intr-rework-base2, chris-arm-intr-rework-base, bouyer-xeni386-nbase, bouyer-xeni386-merge1, bouyer-xeni386-base, bouyer-xeni386, bouyer-xenamd64-base2, bouyer-xenamd64-base, bouyer-xenamd64
Branch point for: mjf-devfs2, matt-armv6, keiichi-mipv6, hpcarm-cleanup, chris-arm-intr-rework
Changes since 1.80: +438 -456 lines
Diff to previous 1.80 (colored)

Convert to cpufunc_* to struct initializers.

Revision 1.80 / (download) - annotate - [select for diffs], Thu Mar 8 20:42:48 2007 UTC (17 years ago) by matt
Branch: MAIN
CVS Tags: thorpej-atomic-base, thorpej-atomic, reinoud-bufcleanup
Branch point for: vmlocking, mjf-ufs-trans
Changes since 1.79: +3 -4 lines
Diff to previous 1.79 (colored)

Fix inverted test (cputype != 0) and now my shark boots again!

Revision 1.79 / (download) - annotate - [select for diffs], Sun Mar 4 14:47:18 2007 UTC (17 years ago) by bjh21
Branch: MAIN
Changes since 1.78: +157 -7 lines
Diff to previous 1.78 (colored)

Finally make cpufuncs work properly on acorn26, since something seems to be
using it.  This entailed adding support for ARM2 and ARM2as, and allowing
for getting CPU IDs other than from CP15, since ARM2(as) doesn't have CP15.

Revision 1.78 / (download) - annotate - [select for diffs], Sat Jan 6 00:50:54 2007 UTC (17 years, 2 months ago) by christos
Branch: MAIN
CVS Tags: post-newlock2-merge, newlock2-nbase, newlock2-base, ad-audiomp-base, ad-audiomp
Branch point for: yamt-idlelwp
Changes since 1.77: +78 -11 lines
Diff to previous 1.77 (colored)

Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E

Revision 1.77 / (download) - annotate - [select for diffs], Sun Mar 26 14:34:30 2006 UTC (17 years, 11 months ago) by peter
Branch: MAIN
CVS Tags: yamt-splraiseipl-base5, yamt-splraiseipl-base4, yamt-splraiseipl-base3, yamt-splraiseipl-base2, yamt-splraiseipl-base, yamt-splraiseipl, yamt-pdpolicy-base9, yamt-pdpolicy-base8, yamt-pdpolicy-base7, yamt-pdpolicy-base6, yamt-pdpolicy-base5, yamt-pdpolicy-base4, yamt-pdpolicy-base3, simonb-timecounters-base, rpaulo-netinet-merge-pcb-base, netbsd-4-base, gdamore-uart-base, gdamore-uart, elad-kernelauth-base, chap-midi-nbase, chap-midi-base, chap-midi, abandoned-netbsd-4-base, abandoned-netbsd-4
Branch point for: newlock2, netbsd-4
Changes since 1.76: +3 -2 lines
Diff to previous 1.76 (colored)

Report the SA1100 control register state.

From Arnaud Lacombe on port-hpcarm.

Revision 1.76 / (download) - annotate - [select for diffs], Sat Dec 24 22:45:34 2005 UTC (18 years, 2 months ago) by perry
Branch: MAIN
CVS Tags: yamt-uio_vmspace-base5, yamt-uio_vmspace, yamt-pdpolicy-base2, yamt-pdpolicy-base, peter-altq-base
Branch point for: yamt-pdpolicy, simonb-timecounters, rpaulo-netinet-merge-pcb, peter-altq, elad-kernelauth
Changes since 1.75: +4 -4 lines
Diff to previous 1.75 (colored)

bare asm -> __asm

Revision 1.75 / (download) - annotate - [select for diffs], Sat Dec 24 20:06:47 2005 UTC (18 years, 2 months ago) by perry
Branch: MAIN
Changes since 1.74: +9 -9 lines
Diff to previous 1.74 (colored)

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

Revision 1.74 / (download) - annotate - [select for diffs], Sun Dec 11 12:16:41 2005 UTC (18 years, 3 months ago) by christos
Branch: MAIN
Changes since 1.73: +2 -2 lines
Diff to previous 1.73 (colored)

merge ktrace-lwp.

Revision 1.73 / (download) - annotate - [select for diffs], Wed Jul 20 14:38:11 2005 UTC (18 years, 8 months ago) by nonaka
Branch: MAIN
CVS Tags: yamt-vop-base3, yamt-vop-base2, yamt-vop-base, yamt-vop, yamt-readahead-pervnode, yamt-readahead-perfile, yamt-readahead-base3, yamt-readahead-base2, yamt-readahead-base, yamt-readahead, thorpej-vnode-attr-base, thorpej-vnode-attr, ktrace-lwp-base
Changes since 1.72: +4 -3 lines
Diff to previous 1.72 (colored)

Added i80219.

Revision 1.72 / (download) - annotate - [select for diffs], Mon Jul 4 00:42:36 2005 UTC (18 years, 8 months ago) by bsh
Branch: MAIN
Branch point for: yamt-lazymbuf
Changes since 1.71: +12 -11 lines
Diff to previous 1.71 (colored)

The first step to support Intel PXA270.

kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270.  If both of them are defined,
CPU is determined run-time.

Revision 1.71 / (download) - annotate - [select for diffs], Fri Jun 3 15:55:55 2005 UTC (18 years, 9 months ago) by rearnsha
Branch: MAIN
Changes since 1.70: +142 -17 lines
Diff to previous 1.70 (colored)

Very basic support for the ARM1136.

This code takes no advantage of any 'new' features provided by
architecture 6 devices (such as physically tagged caches or new
MMU features), and basically runs the chip in a 'legacy v5' mode.

Revision 1.70 / (download) - annotate - [select for diffs], Thu Jun 2 17:45:59 2005 UTC (18 years, 9 months ago) by he
Branch: MAIN
Changes since 1.69: +3 -3 lines
Diff to previous 1.69 (colored)

Adapt to shadowing and qualifier-cast warnings.

Revision 1.69 / (download) - annotate - [select for diffs], Tue May 10 12:59:22 2005 UTC (18 years, 10 months ago) by rearnsha
Branch: MAIN
Changes since 1.68: +4 -3 lines
Diff to previous 1.68 (colored)

Detect arm1026ej-s.

Revision 1.68 / (download) - annotate - [select for diffs], Wed Dec 22 19:18:13 2004 UTC (19 years, 3 months ago) by joff
Branch: MAIN
CVS Tags: yamt-km-base4, yamt-km-base3, yamt-km-base2, yamt-km-base, yamt-km, netbsd-3-base, netbsd-3-1-RELEASE, netbsd-3-1-RC4, netbsd-3-1-RC3, netbsd-3-1-RC2, netbsd-3-1-RC1, netbsd-3-1-1-RELEASE, netbsd-3-1, netbsd-3-0-RELEASE, netbsd-3-0-RC6, netbsd-3-0-RC5, netbsd-3-0-RC4, netbsd-3-0-RC3, netbsd-3-0-RC2, netbsd-3-0-RC1, netbsd-3-0-3-RELEASE, netbsd-3-0-2-RELEASE, netbsd-3-0-1-RELEASE, netbsd-3-0, netbsd-3, kent-audio2-base, kent-audio2, kent-audio1-beforemerge
Changes since 1.67: +5 -2 lines
Diff to previous 1.67 (colored)

support high vectors on ARM9

Revision 1.67 / (download) - annotate - [select for diffs], Sat Apr 3 04:34:40 2004 UTC (19 years, 11 months ago) by bsh
Branch: MAIN
CVS Tags: kent-audio1-base, kent-audio1
Changes since 1.66: +6 -2 lines
Diff to previous 1.66 (colored)

add an option to force ARM9 dcache to write-through mode.

Revision 1.66 / (download) - annotate - [select for diffs], Mon Jan 26 15:54:16 2004 UTC (20 years, 1 month ago) by rearnsha
Branch: MAIN
CVS Tags: netbsd-2-base, netbsd-2-1-RELEASE, netbsd-2-1-RC6, netbsd-2-1-RC5, netbsd-2-1-RC4, netbsd-2-1-RC3, netbsd-2-1-RC2, netbsd-2-1-RC1, netbsd-2-1, netbsd-2-0-base, netbsd-2-0-RELEASE, netbsd-2-0-RC5, netbsd-2-0-RC4, netbsd-2-0-RC3, netbsd-2-0-RC2, netbsd-2-0-RC1, netbsd-2-0-3-RELEASE, netbsd-2-0-2-RELEASE, netbsd-2-0-1-RELEASE, netbsd-2-0, netbsd-2
Changes since 1.65: +22 -17 lines
Diff to previous 1.65 (colored)

Switch the ARM9 to using the Dcache in write-back mode.  Avoid an
unknown problem with dcache_inv_range by using a wbinv for now
(similarly for ARM10).

When setting the ARM9 system control register, use the computed
cpuctrlmask value (not 0xffffffff) so that the clocking-mode bits are
not reset to FastBus mode (which isn't very fast).

Revision 1.65 / (download) - annotate - [select for diffs], Wed Nov 5 12:53:15 2003 UTC (20 years, 4 months ago) by scw
Branch: MAIN
Changes since 1.64: +47 -16 lines
Diff to previous 1.64 (colored)

Add "options ARM32_DISABLE_ALIGNMENT_FAULTS" to forcibly disable
alignment fault checking if necessary.

This option gets the acorn32 port working again.

XXX: Richard Earnshaw suggested enabling alignment faults for
XXX: userland only on acorn32. Need to investigate this.

Revision 1.64 / (download) - annotate - [select for diffs], Sat Oct 25 19:44:42 2003 UTC (20 years, 4 months ago) by scw
Branch: MAIN
Changes since 1.63: +16 -11 lines
Diff to previous 1.63 (colored)

Enable alignment faults on arm32 for both kernel and userland.

If COMPAT_15 and EXEC_AOUT are defined, support per-process
alignment checking where AFLTs are always enabled when running
kernel code and userland ELF binaries, and dynamically disabled/
enabled when switching to/from a.out binaries. This is necessary
in order to execute older a.out binaries, where gcc made
deliberate use of misaligned loads under certain circumstances.

Revision 1.63 / (download) - annotate - [select for diffs], Sat Sep 6 09:31:37 2003 UTC (20 years, 6 months ago) by rearnsha
Branch: MAIN
Changes since 1.62: +143 -3 lines
Diff to previous 1.62 (colored)

Support for ARM10.  Extract some additional information about the
dcache so that we can have cache cleaning code that works for any
permitted arm10 cache architecture.

Revision 1.62 / (download) - annotate - [select for diffs], Wed Sep 3 02:07:07 2003 UTC (20 years, 6 months ago) by mycroft
Branch: MAIN
Changes since 1.61: +5 -3 lines
Diff to previous 1.61 (colored)

Recognize some TI processors -- not that you'd want to use them.

Revision 1.61 / (download) - annotate - [select for diffs], Tue Jul 15 00:24:38 2003 UTC (20 years, 8 months ago) by lukem
Branch: MAIN
Changes since 1.60: +4 -1 lines
Diff to previous 1.60 (colored)

__KERNEL_RCSID()

Revision 1.60 / (download) - annotate - [select for diffs], Sun May 25 01:30:52 2003 UTC (20 years, 9 months ago) by ichiro
Branch: MAIN
Branch point for: ktrace-lwp
Changes since 1.59: +2 -2 lines
Diff to previous 1.59 (colored)

About CP14 register, ixp425 does not need xscalereg.h

Revision 1.59 / (download) - annotate - [select for diffs], Fri May 23 00:57:23 2003 UTC (20 years, 10 months ago) by ichiro
Branch: MAIN
Changes since 1.58: +31 -8 lines
Diff to previous 1.58 (colored)

support IXP425 Intel Network Processor
 running on BigEndian

Revision 1.58 / (download) - annotate - [select for diffs], Tue Apr 22 00:24:48 2003 UTC (20 years, 11 months ago) by thorpej
Branch: MAIN
Changes since 1.57: +6 -6 lines
Diff to previous 1.57 (colored)

Some ARM32_PMAP_NEW-related cleanup:
* Define a new "MMU type", ARM_MMU_SA1.  While the SA-1's MMU is basically
  compatible with the generic, the SA-1 cache does not have a write-through
  mode, and it is useful to know have an indication of this.
* Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at
  compile time.  We evaluate it like so:
  - If SA-1-style MMU is the only type configured -> 1
  - If SA-1-style MMU is not configured -> 0
  - Otherwise, defer to a run-time variable.
  If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time
  check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly
  code can include the necessary run-time support.  PMAP_INCLUDE_PTE_SYNC
  largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve
  included with the original new pmap.
* In the new pmap, make pmap_pte_init_generic() check to see if the CPU
  has a write-back cache.  If so, init the PT cache mode to C=1,B=0 to get
  write-through mode.  Otherwise, init the PT cache mode to C=1,B=1.
* Add a new pmap_pte_init_arm8().  Old pmap, same as generic.  New pmap,
  sets page table cacheability to 0 (ARM8 has a write-back cache, but
  flushing it is quite expensive).
* In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to
  C=1,B=0, since the write-back check in generic gets it wrong for ARM9,
  since we use write-through mode all the time on ARM9 right now.  (What
  this really tells me is that the test for write-through cache is less
  than perfect, but we can fix that later.)
* Add a new pmap_pte_init_sa1().  Old pmap, same as generic.  New pmap,
  does generic initialization, then resets page table cache mode to
  C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.

Revision 1.57 / (download) - annotate - [select for diffs], Mon Apr 21 04:33:30 2003 UTC (20 years, 11 months ago) by thorpej
Branch: MAIN
Changes since 1.56: +2 -2 lines
Diff to previous 1.56 (colored)

#ifdef, not #if, for XSCALE_NO_COALESCE_WRITES.

Revision 1.56 / (download) - annotate - [select for diffs], Fri Apr 18 10:45:23 2003 UTC (20 years, 11 months ago) by scw
Branch: MAIN
Changes since 1.55: +14 -2 lines
Diff to previous 1.55 (colored)

- In the various cpu_setup() functions, check if the vector page
  is at ARM_VECTORS_HIGH and set CPU_CONTROL_VECRELOC if so.

- Don't de-ref a NULL args pointer in parse_cpu_options().

Revision 1.55 / (download) - annotate - [select for diffs], Tue Mar 18 11:20:56 2003 UTC (21 years ago) by bsh
Branch: MAIN
Changes since 1.54: +5 -3 lines
Diff to previous 1.54 (colored)

simplify CPU ID test for Intel PXA2xx by masking core revision part.

This also allows the kernel to run on pxa255.

Revision 1.54 / (download) - annotate - [select for diffs], Tue Aug 20 02:30:51 2002 UTC (21 years, 7 months ago) by briggs
Branch: MAIN
CVS Tags: nathanw_sa_before_merge, nathanw_sa_base, kqueue-beforemerge, kqueue-base, kqueue-aftermerge, gmcgarry_ucred_base, gmcgarry_ucred, gmcgarry_ctxsw_base, gmcgarry_ctxsw, gehenna-devsw-base, fvdl_fs64_base, bjh21-hydra-base, bjh21-hydra
Changes since 1.53: +5 -1 lines
Diff to previous 1.53 (colored)

Coalesced writes on xscale systems do not always work.  If
XSCALE_NO_COALESCE_WRITES is set, disable.  Otherwise, enable.

Revision 1.53 / (download) - annotate - [select for diffs], Tue Aug 20 02:00:46 2002 UTC (21 years, 7 months ago) by briggs
Branch: MAIN
Changes since 1.52: +11 -2 lines
Diff to previous 1.52 (colored)

Enable branch prediction and write coalescing on XScale.

Revision 1.52 / (download) - annotate - [select for diffs], Fri Aug 16 15:25:53 2002 UTC (21 years, 7 months ago) by thorpej
Branch: MAIN
Changes since 1.51: +20 -1 lines
Diff to previous 1.51 (colored)

* Add a new machdep.powersave sysctl, which controls the use of
  the CPU's "sleep" function in the idle loop.
* Default all CPUs to not use powersave, except for the PDA processors
  (SA11x0 and PXA2x0).

This significantly reduces inteterrupt latency in high-performance
applications (and was good to squeeze another ~10% out of an XScale
IOP on a Gig-E benchmark).

Revision 1.51 / (download) - annotate - [select for diffs], Fri Aug 16 00:06:26 2002 UTC (21 years, 7 months ago) by thorpej
Branch: MAIN
Changes since 1.50: +37 -10 lines
Diff to previous 1.50 (colored)

If __ARMEB__ is defined, always set CPU_CONTROL_BEND_ENABLE in
the CPU control register.

Revision 1.50 / (download) - annotate - [select for diffs], Wed Aug 7 05:14:56 2002 UTC (21 years, 7 months ago) by briggs
Branch: MAIN
Changes since 1.49: +16 -1 lines
Diff to previous 1.49 (colored)

Implement pmc(9) -- An interface to hardware performance monitoring
counters.  These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface.  Initially, the Intel XScale
counters are the only ones supported.

Revision 1.49 / (download) - annotate - [select for diffs], Mon Jul 22 18:17:42 2002 UTC (21 years, 8 months ago) by briggs
Branch: MAIN
Changes since 1.48: +3 -2 lines
Diff to previous 1.48 (colored)

Handle i80200 step D0 and i80321 step B0

Revision 1.48 / (download) - annotate - [select for diffs], Mon Jul 15 16:27:15 2002 UTC (21 years, 8 months ago) by ichiro
Branch: MAIN
Changes since 1.47: +112 -3 lines
Diff to previous 1.47 (colored)

add support for ixp12x0

Revision 1.47 / (download) - annotate - [select for diffs], Wed Jul 10 07:00:50 2002 UTC (21 years, 8 months ago) by ichiro
Branch: MAIN
Changes since 1.46: +3 -2 lines
Diff to previous 1.46 (colored)

add cpu id for "PXA250/210 3rd version CPUcore".

for using many PDA/xscale-core.

Revision 1.46 / (download) - annotate - [select for diffs], Fri Jun 7 18:25:28 2002 UTC (21 years, 9 months ago) by thorpej
Branch: MAIN
Changes since 1.45: +2 -2 lines
Diff to previous 1.45 (colored)

Add the CPU ID for the 600MHz i80321 part.

Revision 1.45 / (download) - annotate - [select for diffs], Wed May 22 19:06:23 2002 UTC (21 years, 10 months ago) by thorpej
Branch: MAIN
Changes since 1.44: +1 -2 lines
Diff to previous 1.44 (colored)

Back out an unintended change.

Revision 1.44 / (download) - annotate - [select for diffs], Fri May 3 16:45:22 2002 UTC (21 years, 10 months ago) by rjs
Branch: MAIN
CVS Tags: netbsd-1-6-base
Branch point for: netbsd-1-6, gehenna-devsw
Changes since 1.43: +136 -21 lines
Diff to previous 1.43 (colored)

Use processor specific versions of ARM cache control functions for SA1100
and SA1110 instead of using SA110 ones.

Rename common StrongARM functions from sa110_* to sa1_*.

Reviewed by Jason Thorpe.

Revision 1.43 / (download) - annotate - [select for diffs], Fri May 3 03:28:48 2002 UTC (21 years, 10 months ago) by thorpej
Branch: MAIN
Changes since 1.42: +22 -7 lines
Diff to previous 1.42 (colored)

Add support for the Intel PXA210 and PXA250.  From Hiroyuki Bessho, PR 16617.

Revision 1.42 / (download) - annotate - [select for diffs], Fri Apr 12 21:52:45 2002 UTC (21 years, 11 months ago) by thorpej
Branch: MAIN
Changes since 1.41: +2 -2 lines
Diff to previous 1.41 (colored)

Default all XScale core processors to the read/write-allocate write-back
cache mode.  Add a new XSCALE_CACHE_WRITE_THROUGH option for people who
are paranoid about the cache-related errata (you *do* have to line up
the planets correctly to trip them, but having the option is useful).

Revision 1.41 / (download) - annotate - [select for diffs], Fri Apr 12 18:50:31 2002 UTC (21 years, 11 months ago) by thorpej
Branch: MAIN
Changes since 1.40: +2 -2 lines
Diff to previous 1.40 (colored)

Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel.  What
  you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
  on which ARM architecture versions are configured (based on CPU_*
  options).  Also defines ARM_NARCH to determins how many architecture
  versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
  which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
  to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.

Revision 1.40 / (download) - annotate - [select for diffs], Tue Apr 9 21:00:42 2002 UTC (21 years, 11 months ago) by thorpej
Branch: MAIN
Changes since 1.39: +9 -3 lines
Diff to previous 1.39 (colored)

Define 2 classes of ARM MMUs:
1. Generic (compatible with ARM6)
1. XScale (can be used as generic, but also has certainly nifty extensions).

Define abstract PTE bit defintions for each MMU class.  If only one MMU
class is configured into the kernel (based on CPU_* options), then we
get the constants for that MMU class.  Otherwise we indirect through
varaibles set up via set_cpufuncs().

XXX The XScale bits are currently the same as the generic bits.  Baby steps.

Revision 1.39 / (download) - annotate - [select for diffs], Fri Apr 5 16:58:03 2002 UTC (21 years, 11 months ago) by thorpej
Branch: MAIN
Changes since 1.38: +5 -3 lines
Diff to previous 1.38 (colored)

* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
  Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h.  While
  doing this, two bugs (as a result of typos) were fixed in

	arm/arm32/bus_dma.c
	evbarm/integrator/int_bus_dma.c

Revision 1.38 / (download) - annotate - [select for diffs], Thu Mar 28 16:47:49 2002 UTC (21 years, 11 months ago) by thorpej
Branch: MAIN
Changes since 1.37: +1 -2 lines
Diff to previous 1.37 (colored)

Use write-back caching on the Verde.

Revision 1.37 / (download) - annotate - [select for diffs], Wed Mar 27 01:34:47 2002 UTC (21 years, 11 months ago) by thorpej
Branch: MAIN
Changes since 1.36: +28 -18 lines
Diff to previous 1.36 (colored)

The 80321 manual lies; it does have a CPU ID distinct from the 80200.
Add that CPU ID, and add a case for it.

Revision 1.36 / (download) - annotate - [select for diffs], Tue Mar 26 19:29:44 2002 UTC (21 years, 11 months ago) by thorpej
Branch: MAIN
Changes since 1.35: +36 -13 lines
Diff to previous 1.35 (colored)

Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
  CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
  options, and don't let them both be defined at the same time.
  XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
  <arm/xscale/xscalereg.h>.
* Rename a few existing functions.

Revision 1.35 / (download) - annotate - [select for diffs], Sun Mar 24 15:37:46 2002 UTC (22 years ago) by bjh21
Branch: MAIN
Changes since 1.34: +5 -5 lines
Diff to previous 1.34 (colored)

Add ARM610 cache information.  Not yet tested because booting on ARM610s seems
to be broken at present.

Revision 1.34 / (download) - annotate - [select for diffs], Sat Mar 16 18:26:00 2002 UTC (22 years ago) by bjh21
Branch: MAIN
CVS Tags: eeh-devprop-base, eeh-devprop
Changes since 1.33: +43 -60 lines
Diff to previous 1.33 (colored)

Get rid of the #ifdef DEBUG_FAULT_CORRECTION #ifdef mess, and use a
couple of conditionally-defined macros instead.  This makes the
fault-correction code almost readable.

Revision 1.33 / (download) - annotate - [select for diffs], Sat Mar 16 18:11:11 2002 UTC (22 years ago) by bjh21
Branch: MAIN
Changes since 1.32: +1 -3 lines
Diff to previous 1.32 (colored)

Kill some unnecessary settings of arm_dcache_align_mask.

Revision 1.32 / (download) - annotate - [select for diffs], Sat Mar 16 18:02:19 2002 UTC (22 years ago) by bjh21
Branch: MAIN
Changes since 1.31: +72 -12 lines
Diff to previous 1.31 (colored)

For those CPUs which don't have a cache-type register, keep the details
of the cache in a static table.  Note that the table isn't complete --
contributions of cache details for CPUs whose data sheets I haven't got are
welcome.

Revision 1.31 / (download) - annotate - [select for diffs], Sat Mar 16 03:38:28 2002 UTC (22 years ago) by reinoud
Branch: MAIN
Changes since 1.30: +32 -51 lines
Diff to previous 1.30 (colored)

Clean up cpufunc.c so you can really use it for debugging ... the
dependency on DEBUG_PMAP was useless anyway since the PMAP_DEBUG was
printing soooo much garbage cpufunc's debugging stuff was lost anyway.

Revision 1.30 / (download) - annotate - [select for diffs], Sat Mar 9 21:30:57 2002 UTC (22 years ago) by bjh21
Branch: MAIN
CVS Tags: newlock-base, newlock
Changes since 1.29: +22 -14 lines
Diff to previous 1.29 (colored)

Replace cpu_id and cpu_ctrl in struct _cpu with ci_cpuid and ci_ctrl in
struct cpu_info.  Also kill the cpuctrl global while we're here, and make
identify_arm_cpu() take a struct cpu_info * as an argument alongside the CPU
number.

Revision 1.29 / (download) - annotate - [select for diffs], Wed Jan 30 00:37:18 2002 UTC (22 years, 1 month ago) by thorpej
Branch: MAIN
CVS Tags: ifpoll-base
Changes since 1.28: +7 -1 lines
Diff to previous 1.28 (colored)

Set the CPU sleep routine to sa11x0_cpu_sleep() on SA-1100 and SA-1110
processors.

Revision 1.28 / (download) - annotate - [select for diffs], Fri Jan 25 21:33:26 2002 UTC (22 years, 1 month ago) by thorpej
Branch: MAIN
Changes since 1.27: +15 -2 lines
Diff to previous 1.27 (colored)

* Default dcache_inv_range to xscale_cache_flushD_rng for XScale
  cores.
* For i80200 Step-A0 and Step-A1, set dcache_inv_range to
  xscale_cache_purgeD_rng to work around a bug where a D$
  "invalidate by address" doesn't properly clear the dirty
  bits on the cache block (i80200 errata item #25).

Revision 1.27 / (download) - annotate - [select for diffs], Fri Jan 25 19:19:24 2002 UTC (22 years, 1 month ago) by thorpej
Branch: MAIN
Changes since 1.26: +96 -267 lines
Diff to previous 1.26 (colored)

Overhaul of the ARM cache code.  This is mostly a simplification
pass.  Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:

	icache_sync_all         Synchronize I-cache
	icache_sync_range       Synchronize I-cache range

	dcache_wbinv_all        Write-back and Invalidate D-cache
	dcache_wbinv_range      Write-back and Invalidate D-cache range
	dcache_inv_range        Invalidate D-cache range
	dcache_wb_range         Write-back D-cache range

	idcache_wbinv_all       Write-back and Invalidate D-cache,
				Invalidate I-cache
	idcache_wbinv_range     Write-back and Invalidate D-cache,
				Invalidate I-cache range

Note: This does not yet include an overhaul of the actual asm files
that implement the primitives.  Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.

Revision 1.26 / (download) - annotate - [select for diffs], Thu Jan 24 04:23:19 2002 UTC (22 years, 1 month ago) by briggs
Branch: MAIN
Changes since 1.25: +13 -3 lines
Diff to previous 1.25 (colored)

Two changes for XScale:
	1) Add defparam XSCALE_CCLKCFG to define a parameter for the
	   CCLKCFG register.  Default it to '9' on the IQ80310.
	2) Add a sleep call to the xscale CPU function vector (replacing
	   the nullop) which should drop the CPU into "idle" mode when
	   cpu_switch finds nothing on the run queues.

Revision 1.25 / (download) - annotate - [select for diffs], Wed Jan 23 21:03:07 2002 UTC (22 years, 1 month ago) by thorpej
Branch: MAIN
Changes since 1.24: +3 -13 lines
Diff to previous 1.24 (colored)

i80200: Call i80200_intr_init() to initialize the ICU, rather than
doing it ourselves.

Revision 1.24 / (download) - annotate - [select for diffs], Sat Jan 5 22:41:46 2002 UTC (22 years, 2 months ago) by chris
Branch: MAIN
Changes since 1.23: +5 -1 lines
Diff to previous 1.23 (colored)

Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile.  Turned up a few mismatched functions.  Note that this isn't all of the arm32 files.  Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.

Revision 1.23 / (download) - annotate - [select for diffs], Sat Dec 8 21:30:04 2001 UTC (22 years, 3 months ago) by chris
Branch: MAIN
Changes since 1.22: +5 -2 lines
Diff to previous 1.22 (colored)

Improve comment on the clockswitching asm code, it doesn't use r0 at all, it just needs it to make valid asm.

Revision 1.22 / (download) - annotate - [select for diffs], Sat Dec 1 23:06:45 2001 UTC (22 years, 3 months ago) by thorpej
Branch: MAIN
Changes since 1.21: +26 -1 lines
Diff to previous 1.21 (colored)

Reset the i80200 ICU and PMU to a pristine state very early.

Revision 1.21 / (download) - annotate - [select for diffs], Sat Dec 1 14:21:18 2001 UTC (22 years, 3 months ago) by bjh21
Branch: MAIN
Changes since 1.20: +4 -1 lines
Diff to previous 1.20 (colored)

Don't define get_cachetype() unless it's going to be used.

Revision 1.20 / (download) - annotate - [select for diffs], Sat Dec 1 06:33:40 2001 UTC (22 years, 3 months ago) by thorpej
Branch: MAIN
Changes since 1.19: +14 -1 lines
Diff to previous 1.19 (colored)

On the i80200, disable ECC in the Bus Controller Unit early on; we
don't really have code to deal with ECC errors yet.

Revision 1.19 / (download) - annotate - [select for diffs], Thu Nov 29 02:24:58 2001 UTC (22 years, 3 months ago) by thorpej
Branch: MAIN
Changes since 1.18: +91 -1 lines
Diff to previous 1.18 (colored)

Fetch cache info from the Cache Type register on ARM7TDMI and "greater"
processors.  Report this when the processor is attached.

Revision 1.18 / (download) - annotate - [select for diffs], Mon Nov 26 22:26:44 2001 UTC (22 years, 3 months ago) by thorpej
Branch: MAIN
Changes since 1.17: +71 -2 lines
Diff to previous 1.17 (colored)

Add code to run the XScale cache in write-though mode, and do so
for now...

Revision 1.17 / (download) - annotate - [select for diffs], Fri Nov 23 19:17:04 2001 UTC (22 years, 3 months ago) by thorpej
Branch: MAIN
Changes since 1.16: +4 -4 lines
Diff to previous 1.16 (colored)

Disable the BTB by default on the XScale again; there's some early
stepping errata to deal with before we can safely do this.

Revision 1.16 / (download) - annotate - [select for diffs], Mon Nov 19 18:40:15 2001 UTC (22 years, 4 months ago) by thorpej
Branch: MAIN
Changes since 1.15: +17 -9 lines
Diff to previous 1.15 (colored)

Add a "cpwait" cpufunc, currently a nullop on all but XScale.
"cpwait" ensures that all coprocessor operations have completed
before returning.

Revision 1.15 / (download) - annotate - [select for diffs], Wed Nov 14 01:00:05 2001 UTC (22 years, 4 months ago) by thorpej
Branch: MAIN
Branch point for: nathanw_sa
Changes since 1.14: +7 -3 lines
Diff to previous 1.14 (colored)

* Give the XScale its own cpu_control() entry point; we have to flush
  the Branch Target Buffer of the BPRD bit changes.
* Enable Branch Prediction on the XScale by default.
* Don't invalidate the Branch Target Buffer explicitly. the i80200
  manual (section 5.1, Branch Target Buffer Operation) notes that
  manual software management of the BTB is unnecessary; it is flushed
  implicitly when:
     * processor resets
     * FCSE process ID is written
     * I-cache is invalidated

Revision 1.14 / (download) - annotate - [select for diffs], Sat Nov 10 23:12:41 2001 UTC (22 years, 4 months ago) by thorpej
Branch: MAIN
CVS Tags: thorpej-mips-cache-base
Changes since 1.13: +11 -11 lines
Diff to previous 1.13 (colored)

Fix some whitespace.

Revision 1.13 / (download) - annotate - [select for diffs], Wed Nov 7 00:17:36 2001 UTC (22 years, 4 months ago) by thorpej
Branch: MAIN
Changes since 1.12: +138 -2 lines
Diff to previous 1.12 (colored)

First cut at XScale setup code.  Needs more work.

Revision 1.12 / (download) - annotate - [select for diffs], Thu Oct 18 14:10:07 2001 UTC (22 years, 5 months ago) by rearnsha
Branch: MAIN
Branch point for: thorpej-mips-cache
Changes since 1.11: +129 -8 lines
Diff to previous 1.11 (colored)

Add support calls for ARM9.

Where ARM9, StrongARM and XScale share the same function, rename it
as armv4_XXX.

Revision 1.11 / (download) - annotate - [select for diffs], Mon Jul 9 19:51:14 2001 UTC (22 years, 8 months ago) by reinoud
Branch: MAIN
CVS Tags: thorpej-devvp-base3, thorpej-devvp-base2, thorpej-devvp-base, thorpej-devvp, pre-chs-ubcperf, post-chs-ubcperf
Branch point for: kqueue
Changes since 1.10: +2 -2 lines
Diff to previous 1.10 (colored)

Changed the variable within the ARM6 late abort section from cpu_ctrl to
cpuctrl ...

Revision 1.10 / (download) - annotate - [select for diffs], Thu Jun 7 21:07:22 2001 UTC (22 years, 9 months ago) by chris
Branch: MAIN
Changes since 1.9: +2 -2 lines
Diff to previous 1.9 (colored)

Checkin fix to ARM7TDMI support.  As per patch from John Fremlin to
port-arm32.

Revision 1.9 / (download) - annotate - [select for diffs], Sun Jun 3 18:32:33 2001 UTC (22 years, 9 months ago) by chris
Branch: MAIN
Changes since 1.8: +126 -12 lines
Diff to previous 1.8 (colored)

Add support for ARM7TDMI, as provided in a patch from John Fremlin to port-arm32.

Shouldn't effect any currently in tree ports.

Revision 1.8 / (download) - annotate - [select for diffs], Sun Jun 3 13:38:14 2001 UTC (22 years, 9 months ago) by bjh21
Branch: MAIN
Changes since 1.7: +18 -88 lines
Diff to previous 1.7 (colored)

Rather than duplicating the LDM/STM/LDC/STC fixup code between
early_abort_fixup() and late_abort_fixup(), have the latter tail-call the
former.  This saves another 200 bytes, and I've found my ARM710a card now, so
I've even tested it.

Revision 1.7 / (download) - annotate - [select for diffs], Sat Jun 2 22:30:07 2001 UTC (22 years, 9 months ago) by bjh21
Branch: MAIN
Changes since 1.6: +28 -56 lines
Diff to previous 1.6 (colored)

In {early,late}_abort_fixup(), return ABORT_FIXUP_FAILED, rather than
panic'ing, if we hit an instruction we can't fix up.  This saves 250-odd bytes
of code, and should allow the caller to print a more useful message.

Revision 1.6 / (download) - annotate - [select for diffs], Sat Jun 2 22:08:11 2001 UTC (22 years, 9 months ago) by bjh21
Branch: MAIN
Changes since 1.5: +75 -75 lines
Diff to previous 1.5 (colored)

late_abort_fixup: Get the indentation right!

Revision 1.5 / (download) - annotate - [select for diffs], Sat Jun 2 21:03:33 2001 UTC (22 years, 9 months ago) by bjh21
Branch: MAIN
Changes since 1.4: +19 -138 lines
Diff to previous 1.4 (colored)

Replace arm6_dataabt_fixup() and arm7_dataabt_fixup() with early_abort_fixup()
and late_abort_fixup(), based on the abort model in use, rather than the CPU
type.  This cleans up the code and makes it smaller.  Only tested on an
ARM6 -- I can't find my ARM710a card right now.

Revision 1.4 / (download) - annotate - [select for diffs], Sat Jun 2 19:01:03 2001 UTC (22 years, 9 months ago) by bjh21
Branch: MAIN
Changes since 1.3: +79 -1 lines
Diff to previous 1.3 (colored)

Initial cpufunc operations for ARM3.  Not actually used yet.

Revision 1.3 / (download) - annotate - [select for diffs], Sun May 13 14:41:56 2001 UTC (22 years, 10 months ago) by bjh21
Branch: MAIN
Changes since 1.2: +2 -1 lines
Diff to previous 1.2 (colored)

Include opt_cputypes.h, since we use CPU_*.

Revision 1.2 / (download) - annotate - [select for diffs], Sun May 13 13:50:01 2001 UTC (22 years, 10 months ago) by bjh21
Branch: MAIN
Changes since 1.1: +4 -1 lines
Diff to previous 1.1 (colored)

Don't include parse_cpu_options() unless we're going to use it.  This fixes
a warning on arm26.

Revision 1.1 / (download) - annotate - [select for diffs], Sun May 6 18:01:43 2001 UTC (22 years, 10 months ago) by bjh21
Branch: MAIN

Move cpufunc stuff from arm32/arm32 to arm/arm.  The only change involved is
to add recognition of the SA-1100 and SA-1110 for compatibility with hpcarm
(which is now using this code as well).

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