CVS log for src/sys/arch/arm/arm/cpufunc.c

Up to [cvs.NetBSD.org] / src / sys / arch / arm / arm

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

Pull up following revision(s) (requested by ryo in ticket #20):

	sys/arch/arm/arm/cpufunc.c: revision 1.185
	sys/dev/tprof/tprof.c: revision 1.22
	sys/arch/arm/arm32/arm32_boot.c: revision 1.45
	sys/dev/tprof/tprof_armv8.c: revision 1.19
	sys/dev/tprof/tprof_armv7.c: revision 1.12
	sys/arch/aarch64/aarch64/cpu.c: revision 1.71
	sys/arch/aarch64/aarch64/cpu.c: revision 1.72

tprof_lock is not a spin mutex. use mutex_{enter,exit}(). oops

Explicitly disable overflow interrupts before enabling the cycle counter.

PMCR_EL0.LC should be set. ARM deprecates use of PMCR_EL0.LC=0

Even if an overflow interrupt is occured for a counter outside tprof management,
the bit of onverflow status register must be cleared to prevent an interrupt storm.

Explicitly disable overflow interrupts before enabling the cycle counter.

port-arm/50635: arm11_setup() cpuctrlmask value causes CPU_CONTROL_VECRELOC bit to toggle

Fix slightly differently to as suggested in the PR.  Annotate arm10_setup
while I'm here.

Apply some errata workarounds for Cortex A17

Set ACTLR.SMP=1 on Cortex-A17

Sync with HEAD.

Be consistent about #ifndef ARM32_DISABLE_ALIGNMENT_FAULTS.  NFCI.

Sync with HEAD.

One #include "opt_cputypes.h" is enough for anyone

Sync w/ HEAD.

Fix earmv6{,hf}eb start-up routines:

- Turn on U-bit in SCTLR before E-bit is turned on by ``setend be'',
  in order to avoid undefined condition. ARM1176JZF-S, at least, halts
  if only E-bit is turned on.

- Turn on EE-bit in SCTLR instead of B-bit as we've switched to BE8.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Add support for KASAN on ARMv[67]

Thanks to maxv for many pointers and reviews.

Merge changes from current as of 20200406

Sync with head.

Pull up following revision(s) (requested by skrll in ticket #742):

	sys/arch/arm/arm32/pmap.c: revision 1.388
	sys/arch/arm/arm32/armv7_generic_space.c: revision 1.11
	sys/arch/arm/arm/cpufunc.c: revision 1.176
	sys/arch/arm/conf/Makefile.arm: revision 1.54 (via patch)
	sys/arch/arm/include/arm32/pmap.h: revision 1.161

Fix the armv[67] memory attributes for uncached memory.  Previously it was
mapped as strongly-ordered which meant that unaligned accesses would fault.
armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO
bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get
mapped to the correct memory attribute bits for armv[67]

DEVMAP_ENTRY usees a new flag PTE_DEV.

The workaround for the unaligned access faults is now removed.
XXX Other armv[67] boards bus_space implementations should be checked.
XXX There is scope to reduce the difference to aarch64

Fix the armv[67] memory attributes for uncached memory.  Previously it was
mapped as strongly-ordered which meant that unaligned accesses would fault.

armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO

bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get
mapped to the correct memory attribute bits for armv[67]

DEVMAP_ENTRY usees a new flag PTE_DEV.

The workaround for the unaligned access faults is now removed.

XXX Other armv[67] boards bus_space implementations should be checked.
XXX There is scope to reduce the difference to aarch64

Sync with HEAD

Sync with HEAD, resolve a couple of conflicts

Sync with head

Clean up around cpu_ttb and fix a bunch of builds

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors.  AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested.  Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

Whitespace

Sprinkle #include "opt_cputypes.h"

Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.

ok jmcneill@ skrll@

Sync with HEAD

<sys/pmc.h> is gone; don't #include it

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

 * Removes "options PERFCTRS", the associated includes, and the associated
   ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
   good.

 * Removes the PMC code of ARM XSCALE.

 * Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

 * Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
   definitions are put in sysarch.h.

 * Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
   and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
   netbsd32 and rump.

 * Removes the pmc_evid_t and pmc_ctr_t types.

 * Removes all the associated man pages. The sets are marked as obsolete.

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

update from HEAD

KNF

Sync with HEAD

#ifdef whack-a-mole

Fixup CPU_PJ4B for recent armv7 tlb operation changes.

Do runtime detection of MP extensions to allow using a MULTIPROCESSOR
kernel on CPUs without the MP extensions feature (like Cortex-A8).

Sync with HEAD

Sync with HEAD

Sync with HEAD

Drop inadvertent redundant CPU_CONTROL_MMU_ENABLE ((1 < 22)) for PJ4Bv7.

This was intended to be CPU_CONTROL_UNAL_ENABLE, which is already handled.

Should fix PR kern/51921.

Sync with HEAD

Sync with HEAD

Indent.

Pull up following revision(s) (requested by skrll in ticket #1354):
	sys/arch/arm/arm/cpufunc.c: revision 1.159
PR port-arm/50512: Source code condition impossible
Fix condition which broke ARM1136 function selection when ARM1176 support
was added

Sync with HEAD

PR 50669 David Binderman: remove dead code

Sync with HEAD

Rename the cpu_id() define to cpu_idnum() so that it does not conflict with
dtrace and friends.

Pull up following revision(s) (requested by skrll in ticket #1060):
	sys/arch/arm/arm/cpufunc.c: revision 1.159
PR port-arm/50512: Source code condition impossible
Fix condition which broke ARM1136 function selection when ARM1176 support
was added

Pull up following revision(s) (requested by skrll in ticket #1060):
	sys/arch/arm/arm/cpufunc.c: revision 1.159
PR port-arm/50512: Source code condition impossible
Fix condition which broke ARM1136 function selection when ARM1176 support
was added

Sync with HEAD (as of 26th Dec)

PR port-arm/50512: Source code condition impossible

Fix condition which broke ARM1136 function selection when ARM1176 support
was added

G/C TEGRAK1_PMAP_WORKAROUND.

Using XN (eXecute Never) properly means speculative reads from devices
aren't done.  Pretty sure this was the cause of the wedges.

Setting actlr.bit15=1 (Force in order issue in the branch execution unit)
makes my jetson tk1 stable.  Apply this workaround until we figure out
what the real problem is.

Sync with HEAD

Use armreg_*_{read,write} instead of handcrafted asm

No functional change.

Sync with HEAD

initialize sdcache operations for PJ4B.
otherwise the kernel crashes without 'options L2CACHE_ENABLE.'

Pull up following revision(s) (requested by skrll in ticket #805):
	sys/arch/arm/include/arm32/pmap.h: revision 1.138
	sys/arch/arm/arm/cpufunc.c: revision 1.151
	sys/arch/arm/arm32/bus_dma.c: revision 1.90
	sys/arch/arm/broadcom/bcm53xx_pax.c: revision 1.14
	sys/arch/arm/arm32/bus_dma.c: revision 1.91
	sys/arch/arm/samsung/exynos_space.c: revision 1.2
	sys/arch/arm/arm32/db_machdep.c: revision 1.23
	sys/arch/arm/allwinner/awin_space.c: revision 1.4
	sys/arch/arm/include/rwlock.h: revision 1.9
	sys/arch/arm/amlogic/amlogic_space.c: revision 1.2
	sys/arch/arm/zynq/zynq_space.c: revision 1.2
	sys/arch/arm/broadcom/bcm2835_space.c: revision 1.7
	sys/arch/arm/arm32/pmap.c: revision 1.317
	sys/arch/arm/include/locore.h: revision 1.19
	sys/arch/arm/include/mutex.h: revision 1.20
	sys/arch/arm/include/lock.h: revision 1.31
	sys/arch/arm/include/lock.h: revision 1.32
	sys/arch/arm/broadcom/bcmgen_space.c: revision 1.5
- Kill redundant semicolons.
- Indentation.
- Improve inline asm around dsb/dmb/isb:
  - always use volatile and mark them as memory barrier
  - use the common version from locore.h in all places not included from
    userland

add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.

don't call L2 maintance function if L2 cache is disabled.

clean up cpufuncs of CPU_PJ4B.

PJ4B is a ARMv7 compatible CPU, so most of cpufuncs are just redundant.
we need funcs for:
  - Marvell specific registers
  - workaround of errata
  - and Marvell specific L2 cache maintainance
if I/O coherency fabric is enabled(option AURORA_IO_CACHE_COHERENCY),
probaly we don't need to maintain L2 cache by software.

Sync with HEAD

Improve inline asm around dsb/dmb/isb:
- always use volatile and mark them as memory barrier
- use the common version from locore.h in all places not included from
  userland

Rebase to HEAD as of a few days ago.

Rebase.

Trailing whitespace.

Apply some errata workarounds

More fixes as a step towards ARM_MMU_EXTENDED on RPI.

- don't set CPU_CONTROL_SYST_ENABLE in arm11x6_setup for ARM_MMU_EXTENDED

- Use the new MMU defines for V6N

- pull in arm/cpuconf.h in vmparam s that VM_MAXUSER_ADDRESS gets set
  correctly.

Fix tpyo.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Include cpufunc_proto.h before locore.h so that we define cpu_cpwait first.
XXX: this is a mess.

Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.

change cortex_cpufunc to armv7_cpufuncs.  CPU_CORTEX -> CPU_ARMV7

arm11 ARM_MMU_EXTENDED support (setting CPU_CONTROL_XP_ENABLE)

Use arm11_setttb for arm1176 as well.

cortex doesn't need xscale_setup
use arm11_setttb for arm11x6.

Initialize cache way_size and sets

For armv7, enable BE properly.  Make sure UNAL is always set.

For now, don't reset arm_cache_prefer_mask unless both l1 caches are PIPT

Keep track of what each cache is (VIVT/VIPT/PIPT).

cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache

armv7 doens't need to use the arm11 routines anymore.

Make sure AFLT_ENABLE in the cpuctrl mask for armv7_setup.

Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.

For armv7, CPU_CONTROL_UNAL_ENABLE is MBO/SBPO.
Make sure CPU_CONTROL_EX_BEND is set for big endian kernels.
Don't clear bits we aren't setting.

- comment out set but not used variables.
- make commenting out the cpuctrlmask consistent

Improve assembler syntax.

Add missing volatile for hidden side effects of asm.

Add CPU_IS_ARMV6_P() macro

Remove unused variables.

Make sure CPU_CONTROL_UNAL_ENABLE is enabled for armv7 cpus (should be
already but ...)

Add CPU_CONTROL_UNAL_ENABLE. New ABIs demand unaligned accesses!

ifdef notyet code.

Fix PR/48332 by reverting to passing 0xffffffff as the cpuctrlmask.
Comment out the cpuctrlmask that doesn't work for the imx23_olinuxino
leaving it there for reference.

Use cpuctrlmask in the arm1[01] case.

sync with head

Add a CPU_IS_ARMV7_P() macro (nonv7 evals to false, v7 only true, otherwise
cpu_armv7_p is checked (and is set by cpuconf for cortex and pj4b).

Include <arm/locore.h>

resync from head

Only set CPU_CONTROL_VECRELOC if ARM_HAS_VBAR is not defined.

Nuke cpu_pfr, just use the armreg_pfr?_read inlines

If the L1 instruction cache policy is PIPT, don't set the prefer_mask.

Plug support for PJ4B core into our ARM CPU support infrastructure.

Obtained from Marvell, Semihalf.

resync with head

sync with head

sync with (a bit old) head

Pull up following revision(s) (requested by msaitoh in ticket #774):
	sys/arch/arm/arm/cpufunc.c: revision 1.119
Enable DCache Streaming Switch and Write Allocate.
This change improve system performance significantly.

Enable DCache Streaming Switch and Write Allocate for Sheeva CPU.
This change improve system performance significantly.

Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.

Resync to 2012-11-19 00:00:00 UTC

C99 types

sync with head

Add armv7_drain_writebuf (which is just a dsb).

Add secondary cache range ops

Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

Change _l2_ to _log2_ to make sure they don't confused with level 2.

Recode armv7_dcache_wbinv_all in asm.  Add armv7_dcache_inv_all and
armv7_icache_inv_all as well.
Use dsb/dmb/isb instructions

always start PMC cycle counter for ARM11 and Cortex.

Rename ARM options PROCESS_ID_IS_CUR{CPU,LWP} to TPIDRPRW_IS_CUR{CPU,LWP}
since TPIDRPRW is the cp15 register name.
Initialize it early in start along with CI_ARM_CPUID.
Remove other initializations.
We alays have ci_curlwp.
Enable TIPRPRW_IS_CURCPU in std.beagle.
[tested on a beaglboard (cortex-a8)]

Move the standard definitions of the {UND,IRQ,FIQ,ABT}_STACK_SIZE to
<arm32/machdep.h>
Move the extern for cpu_reset_address to the same file.
Add cpu_reset_address_paddr.
Kill cpu_reset_v4_MMU_disable.
if cpu_reset_address is NULL, then the MMU will be disabled.

Pull up revisions:
  src/sys/arch/evbarm/dev/plcomreg.h revisions 1.2,1.3,1.4
  src/sys/arch/evbarm/conf/INTEGRATOR revision 1.65
  src/sys/arch/evbarm/dev/plcom.c revisions 1.34,1.35,1.36,1.37,1.38,1.39,1.40
  src/sys/arch/evbarm/ifpga/plcom_ifpga.c revisions 1.12,1.13,1.14
  src/sys/arch/evbarm/dev/plcomvar.h revisions 1.9,1.10,1.11
  src/sys/arch/evbarm/ifpga/plcom_ifpgavar.h revision 1.2
  src/sys/arch/arm/arm/cpufunc.c revisions 1.105,1.108
  src/sys/arch/arm/arm32/cpu.c revision 1.79
  src/sys/arch/arm/include/armreg.h revisions 1.49,1.54
  src/sys/arch/arm/arm32/pmap.c revision 1.229
  src/sys/arch/arm/arm32/arm32_machdep.c revision 1.77
  src/sys/arch/arm/include/cpu.h revision 1.64
  src/sys/arch/arm/arm/cpufunc_asm_arm1136.S revision 1.3
  src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S revision 1.1
  src/sys/arch/arm/conf/files.arm revision 1.106
  src/sys/arch/arm/include/cpufunc.h revision 1.57
  src/sys/dev/sdmmc/sdhc.c revisions 1.14,1.24
  src/sys/dev/sdmmc/sdhcvar.h revisions 1.7,1.8
  src/sys/arch/evbarm/ifpga/ifpgareg.h revision 1.4
  src/sys/arch/evbarm/integrator/integrator_machdep.c revision 1.69
  src/sys/arch/arm/broadcom/bcm2835_dma.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_emmc.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_intr.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_intr.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_obio.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_plcom.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_pm.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_pmvar.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_space.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_tmr.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835reg.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835var.h revision 1.1
  src/sys/arch/arm/broadcom/bcm_amba.h revision 1.1
  src/sys/arch/arm/broadcom/files.bcm2835 revision 1.1
  src/sys/arch/evbarm/Makefile revision 1.9
  src/sys/arch/evbarm/conf/RPI revision 1.1
  src/sys/arch/evbarm/conf/files.rpi revision 1.1
  src/sys/arch/evbarm/conf/mk.rpi revision 1.1
  src/sys/arch/evbarm/conf/std.rpi revision 1.1
  src/sys/arch/evbarm/rpi/genassym.cf revision 1.1
  src/sys/arch/evbarm/rpi/rpi.h revision 1.1
  src/sys/arch/evbarm/rpi/rpi_machdep.c revision 1.1
  src/sys/arch/evbarm/rpi/rpi_start.S revision 1.1,1.2
  src/etc/etc.evbarm/Makefile.inc revision 1.28
(requested by skrll in ticket #454).

don't mix #define<TAB> and #define<SPACE> in a file.

avoid warning with options PLCOM_DEBUG for INTEGRATOR.

Rename register values. No functional change - same code before and after.

Existing names are prefixed with PL01X_ where they're common between the
PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're
found only on the respective chips.

Replace the simple_lock with a kmutex_t.  Update the locking to match
com(4) in the few places it didn't already.

DOH.  Replace a line that got accidently deleted in the last commit.

device_t/softc split
struct device * -> device_t
struct cfdata * -> cfdata_t

Add the 'Z' to the 1176 cpu product name.

ok matt@

Fix locking botch introduced in 1.36.

Fix a KASSERT. From/OK'ed by matt@

Fix racy softint dispatch that lead to KASSERT(si->si_active) in
softint_execute

Discussed with matt@. "Looks good to me"

Add the documented ARM11[37]6 Auxiliary control register defines.

Add support for the ARM1176JZS

Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that).

Provide a method for attachments to specify capabilites.

Add support for the PL011 to plcom. Pull across a bunch of fixes from
com(4) while I'm here and do some other tidyup.

Tested on a RaspberryPi.

PL010 not tested.

Initial commit of support for the RaspberryPI (www.raspberrypi.org)

This is enough for serial console via the gpio header pins and to get to
multiuser.

A huge thank you to Matt Thomas for all his help.

Add RPI to KERNEL_SETS

Remove #if 0 code.

Make auxiliary register naming consistent for the 1136.

Add support for the ARM1176JZS

Support cpu_sleep() on Sheeva CPUs.

Begin support for Cortex A5, A7, A15 and expand A8 and A9 definitions.
Instead of testing all possible CPUids for a cortex, we know what range
a cortex will be so mask out the insignificant parts and do a single test.

sync to latest -current.

sync with head.

Add the 'Z' to the 1176 cpu product name.

ok matt@

sync with head

merge to -current.

Convert stragglers to use real C89 prototypes.

Sync with HEAD.

sync with head

add MPCore to CPU-ID table
add branch predict bit to arm11_options

Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.

sync with head

Sync with HEAD (-D20101022).

sync with head

Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
  Discovery Innovation not yet.

Replace some whitespaces to Tab.

Sync with HEAD.

sync with head.

Remove unnecessary white-spaces.

Fix set the control register.

sync with head

Fix cache probing on Cortex.  Add missing CORTEX dependency in cpu.c

Cleanup the armv7 changes.  Add ARM_ARCH_7.   Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well.  Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

sync with head

Add write-through cache work-around for ARM11 as well as ARM9/ARM10.  Analyzed
& tested on i.MX35 with help from Tsubai Masanari.

Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.

sync with head.

Sync with HEAD.

ansify function definitions

Change about 4500 of the K&R function definitions to ANSI ones.
There are still about 1600 left, but they have ',' or /* ... */
in the actual variable definitions - which my awk script doesn't handle.
There are also many that need () -> (void).
(The script does handle misordered arguments.)

Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

Sync with HEAD.

Sync with HEAD.

Fix merge botch from april...

Sync with HEAD.

Add fa526_flush_prefetchbuf

Add FA526 support (compile tested only)

Sync with HEAD.

Sync with wrstuden-revivesa-base-2.

Add support Cortex-A8.  Pretend they are ARM11s.  Support new cache sizing
method introduced with Cortex-A8.

Sync with head.

Implement workaround for:
arm11 Errata 364296:Possible Cache Data Corruption with Hit-Under-Miss

Remove hack in userret which is redundant with workaround.

workaround code from <imre.deak@teleca.com>

Sync with head.

Remove repeated setting of cpuctl bit for vectors being high in cpu setup
code.

Pointed out in private email by Kevin Lo.

Sync with HEAD.

sync with head.

sync with head.

Merge kernel changes in matt-armv6 to HEAD.

Sync with HEAD.

sync with head.

sync with HEAD

Sync with head.

sync with head.

Allow detection of VFP devices on ARM11 cores.

Sync with HEAD.

sync with head.

allow arm11 to use high vectors.

Add AT91 support from Sami Kantoluoto
Add TI OMAP2430 support from Marty Fouts @ Danger Inc

Import TI OMAP 2430 and ARM11/ARMv6 support.  Now on ARMv6, the cache is
no longer purged on context switches.

sync with head.

Make arm11 use the armv6 cpufuncs.

Sync with head.

Sync with head.

sync with head.

Convert to cpufunc_* to struct initializers.

Sync with HEAD.

Fix inverted test (cputype != 0) and now my shark boots again!

Finally make cpufuncs work properly on acorn26, since something seems to be
using it.  This entailed adding support for ARM2 and ARM2as, and allowing
for getting CPU IDs other than from CP15, since ARM2(as) doesn't have CP15.

sync with head.

Pull up following revision(s) (requested by matt in ticket #457):
	sys/arch/arm/include/cpufunc.h: revision 1.38
	sys/arch/arm/arm/cpufunc.c: revision 1.78
	sys/arch/arm/arm/cpufunc_asm_arm10.S: revision 1.6
	sys/arch/arm/include/armreg.h: revision 1.37
	sys/arch/arm/arm32/cpu.c: revision 1.64
	sys/arch/arm/arm/cpufunc_asm_armv5.S: revision 1.3
	sys/arch/arm/include/cpuconf.h: revision 1.13
	sys/arch/arm/conf/files.arm: revision 1.82
	sys/arch/arm/arm/cpufunc_asm_armv5_ec.S: revision 1.1
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E

Sync with head.

Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E

sync with head

sync with head.

Sync with head.

sync with head - hopefully this will work

sync with head.

Merge 2006-03-28 NetBSD-current into the "peter-altq" branch.

Report the SA1100 control register state.

From Arnaud Lacombe on port-hpcarm.

bare asm -> __asm

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

Added i80219.

The first step to support Intel PXA270.

kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270.  If both of them are defined,
CPU is determined run-time.

Very basic support for the ARM1136.

This code takes no advantage of any 'new' features provided by
architecture 6 devices (such as physically tagged caches or new
MMU features), and basically runs the chip in a 'legacy v5' mode.

Adapt to shadowing and qualifier-cast warnings.

Detect arm1026ej-s.

Sync with HEAD.

support high vectors on ARM9

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

add an option to force ARM9 dcache to write-through mode.

Switch the ARM9 to using the Dcache in write-back mode.  Avoid an
unknown problem with dcache_inv_range by using a wbinv for now
(similarly for ARM10).

When setting the ARM9 system control register, use the computed
cpuctrlmask value (not 0xffffffff) so that the clocking-mode bits are
not reset to FastBus mode (which isn't very fast).

Add "options ARM32_DISABLE_ALIGNMENT_FAULTS" to forcibly disable
alignment fault checking if necessary.

This option gets the acorn32 port working again.

XXX: Richard Earnshaw suggested enabling alignment faults for
XXX: userland only on acorn32. Need to investigate this.

Enable alignment faults on arm32 for both kernel and userland.

If COMPAT_15 and EXEC_AOUT are defined, support per-process
alignment checking where AFLTs are always enabled when running
kernel code and userland ELF binaries, and dynamically disabled/
enabled when switching to/from a.out binaries. This is necessary
in order to execute older a.out binaries, where gcc made
deliberate use of misaligned loads under certain circumstances.

Support for ARM10.  Extract some additional information about the
dcache so that we can have cache cleaning code that works for any
permitted arm10 cache architecture.

Recognize some TI processors -- not that you'd want to use them.

__KERNEL_RCSID()

About CP14 register, ixp425 does not need xscalereg.h

support IXP425 Intel Network Processor
 running on BigEndian

Some ARM32_PMAP_NEW-related cleanup:
* Define a new "MMU type", ARM_MMU_SA1.  While the SA-1's MMU is basically
  compatible with the generic, the SA-1 cache does not have a write-through
  mode, and it is useful to know have an indication of this.
* Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at
  compile time.  We evaluate it like so:
  - If SA-1-style MMU is the only type configured -> 1
  - If SA-1-style MMU is not configured -> 0
  - Otherwise, defer to a run-time variable.
  If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time
  check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly
  code can include the necessary run-time support.  PMAP_INCLUDE_PTE_SYNC
  largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve
  included with the original new pmap.
* In the new pmap, make pmap_pte_init_generic() check to see if the CPU
  has a write-back cache.  If so, init the PT cache mode to C=1,B=0 to get
  write-through mode.  Otherwise, init the PT cache mode to C=1,B=1.
* Add a new pmap_pte_init_arm8().  Old pmap, same as generic.  New pmap,
  sets page table cacheability to 0 (ARM8 has a write-back cache, but
  flushing it is quite expensive).
* In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to
  C=1,B=0, since the write-back check in generic gets it wrong for ARM9,
  since we use write-through mode all the time on ARM9 right now.  (What
  this really tells me is that the test for write-through cache is less
  than perfect, but we can fix that later.)
* Add a new pmap_pte_init_sa1().  Old pmap, same as generic.  New pmap,
  does generic initialization, then resets page table cache mode to
  C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.

#ifdef, not #if, for XSCALE_NO_COALESCE_WRITES.

- In the various cpu_setup() functions, check if the vector page
  is at ARM_VECTORS_HIGH and set CPU_CONTROL_VECRELOC if so.

- Don't de-ref a NULL args pointer in parse_cpu_options().

simplify CPU ID test for Intel PXA2xx by masking core revision part.

This also allows the kernel to run on pxa255.

Pull up revision 1.53 (requested by thorpej in ticket #703):
  Enable branch prediction and write coalescing on XScale.

Pull up revision 1.51 (requested by thorpej in ticket #685):
  If __ARMEB__ is defined, always set CPU_CONTROL_BEND_ENABLE
  in the CPU control register.

sync kqueue branch with HEAD

catch up with -current.

Sync with -current.

Coalesced writes on xscale systems do not always work.  If
XSCALE_NO_COALESCE_WRITES is set, disable.  Otherwise, enable.

Enable branch prediction and write coalescing on XScale.

Partial (ARM only) sync with trunk -- significant performance improvements
for XScale-based systems.

* Add a new machdep.powersave sysctl, which controls the use of
  the CPU's "sleep" function in the idle loop.
* Default all CPUs to not use powersave, except for the PDA processors
  (SA11x0 and PXA2x0).

This significantly reduces inteterrupt latency in high-performance
applications (and was good to squeeze another ~10% out of an XScale
IOP on a Gig-E benchmark).

If __ARMEB__ is defined, always set CPU_CONTROL_BEND_ENABLE in
the CPU control register.

Catch up to -current.

Implement pmc(9) -- An interface to hardware performance monitoring
counters.  These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface.  Initially, the Intel XScale
counters are the only ones supported.

Catch up to -current.

Pull up revision 1.49 (requested by thorpej in ticket #549):
Handle i80200 step D0 and i80321 step B0

Handle i80200 step D0 and i80321 step B0

catch up with -current.

catch up with -current.

add support for ixp12x0

catch up with -current.

add cpu id for "PXA250/210 3rd version CPUcore".

for using many PDA/xscale-core.

catch up with -current on kqueue branch

Catch up to -current.

pullup-1-6 ticket #208:

syssrc/sys/arch/arm/arm/cpufunc.c 1.46
syssrc/sys/arch/arm/arm32/cpu.c 1.38
syssrc/sys/arch/arm/include/armreg.h 1.19

Original log message:

Add the CPU ID for the 600MHz i80321 part.

Add the CPU ID for the 600MHz i80321 part.

Catch up with -current.

Pull up revision 1.45 (requested by thorpej):
Back out an unintended change.

Back out an unintended change.

Use processor specific versions of ARM cache control functions for SA1100
and SA1110 instead of using SA110 ones.

Rename common StrongARM functions from sa110_* to sa1_*.

Reviewed by Jason Thorpe.

Add support for the Intel PXA210 and PXA250.  From Hiroyuki Bessho, PR 16617.

Catch up to -current.

Default all XScale core processors to the read/write-allocate write-back
cache mode.  Add a new XSCALE_CACHE_WRITE_THROUGH option for people who
are paranoid about the cache-related errata (you *do* have to line up
the planets correctly to trip them, but having the option is useful).

Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel.  What
  you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
  on which ARM architecture versions are configured (based on CPU_*
  options).  Also defines ARM_NARCH to determins how many architecture
  versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
  which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
  to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.

Define 2 classes of ARM MMUs:
1. Generic (compatible with ARM6)
1. XScale (can be used as generic, but also has certainly nifty extensions).

Define abstract PTE bit defintions for each MMU class.  If only one MMU
class is configured into the kernel (based on CPU_* options), then we
get the constants for that MMU class.  Otherwise we indirect through
varaibles set up via set_cpufuncs().

XXX The XScale bits are currently the same as the generic bits.  Baby steps.

* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
  Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h.  While
  doing this, two bugs (as a result of typos) were fixed in

	arm/arm32/bus_dma.c
	evbarm/integrator/int_bus_dma.c

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

Use write-back caching on the Verde.

The 80321 manual lies; it does have a CPU ID distinct from the 80200.
Add that CPU ID, and add a case for it.

Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
  CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
  options, and don't let them both be defined at the same time.
  XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
  <arm/xscale/xscalereg.h>.
* Rename a few existing functions.

Add ARM610 cache information.  Not yet tested because booting on ARM610s seems
to be broken at present.

Get rid of the #ifdef DEBUG_FAULT_CORRECTION #ifdef mess, and use a
couple of conditionally-defined macros instead.  This makes the
fault-correction code almost readable.

Kill some unnecessary settings of arm_dcache_align_mask.

For those CPUs which don't have a cache-type register, keep the details
of the cache in a static table.  Note that the table isn't complete --
contributions of cache details for CPUs whose data sheets I haven't got are
welcome.

Catch up with -current.

Clean up cpufunc.c so you can really use it for debugging ... the
dependency on DEBUG_PMAP was useless anyway since the PMAP_DEBUG was
printing soooo much garbage cpufunc's debugging stuff was lost anyway.

Replace cpu_id and cpu_ctrl in struct _cpu with ci_cpuid and ci_ctrl in
struct cpu_info.  Also kill the cpuctrl global while we're here, and make
identify_arm_cpu() take a struct cpu_info * as an argument alongside the CPU
number.

Catch up to -current.

Sync w/ -current.

Set the CPU sleep routine to sa11x0_cpu_sleep() on SA-1100 and SA-1110
processors.

* Default dcache_inv_range to xscale_cache_flushD_rng for XScale
  cores.
* For i80200 Step-A0 and Step-A1, set dcache_inv_range to
  xscale_cache_purgeD_rng to work around a bug where a D$
  "invalidate by address" doesn't properly clear the dirty
  bits on the cache block (i80200 errata item #25).

Overhaul of the ARM cache code.  This is mostly a simplification
pass.  Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:

	icache_sync_all         Synchronize I-cache
	icache_sync_range       Synchronize I-cache range

	dcache_wbinv_all        Write-back and Invalidate D-cache
	dcache_wbinv_range      Write-back and Invalidate D-cache range
	dcache_inv_range        Invalidate D-cache range
	dcache_wb_range         Write-back D-cache range

	idcache_wbinv_all       Write-back and Invalidate D-cache,
				Invalidate I-cache
	idcache_wbinv_range     Write-back and Invalidate D-cache,
				Invalidate I-cache range

Note: This does not yet include an overhaul of the actual asm files
that implement the primitives.  Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.

Two changes for XScale:
	1) Add defparam XSCALE_CCLKCFG to define a parameter for the
	   CCLKCFG register.  Default it to '9' on the IQ80310.
	2) Add a sleep call to the xscale CPU function vector (replacing
	   the nullop) which should drop the CPU into "idle" mode when
	   cpu_switch finds nothing on the run queues.

i80200: Call i80200_intr_init() to initialize the ICU, rather than
doing it ourselves.

More catchup.

Sync kqueue branch with -current.

Catch up to -current.

Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile.  Turned up a few mismatched functions.  Note that this isn't all of the arm32 files.  Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.

Improve comment on the clockswitching asm code, it doesn't use r0 at all, it just needs it to make valid asm.

Reset the i80200 ICU and PMU to a pristine state very early.

Don't define get_cachetype() unless it's going to be used.

On the i80200, disable ECC in the Bus Controller Unit early on; we
don't really have code to deal with ECC errors yet.

Fetch cache info from the Cache Type register on ARM7TDMI and "greater"
processors.  Report this when the processor is attached.

Add code to run the XScale cache in write-though mode, and do so
for now...

Disable the BTB by default on the XScale again; there's some early
stepping errata to deal with before we can safely do this.

Add a "cpwait" cpufunc, currently a nullop on all but XScale.
"cpwait" ensures that all coprocessor operations have completed
before returning.

file cpufunc.c was added on branch nathanw_sa on 2002-01-08 00:23:06 +0000

* Give the XScale its own cpu_control() entry point; we have to flush
  the Branch Target Buffer of the BPRD bit changes.
* Enable Branch Prediction on the XScale by default.
* Don't invalidate the Branch Target Buffer explicitly. the i80200
  manual (section 5.1, Branch Target Buffer Operation) notes that
  manual software management of the BTB is unnecessary; it is flushed
  implicitly when:
     * processor resets
     * FCSE process ID is written
     * I-cache is invalidated

Sync the thorpej-mips-cache branch with -current.

Fix some whitespace.

First cut at XScale setup code.  Needs more work.

Add support calls for ARM9.

Where ARM9, StrongARM and XScale share the same function, rename it
as armv4_XXX.

Changed the variable within the ARM6 late abort section from cpu_ctrl to
cpuctrl ...

Catch up to -current.

Checkin fix to ARM7TDMI support.  As per patch from John Fremlin to
port-arm32.

Add support for ARM7TDMI, as provided in a patch from John Fremlin to port-arm32.

Shouldn't effect any currently in tree ports.

Rather than duplicating the LDM/STM/LDC/STC fixup code between
early_abort_fixup() and late_abort_fixup(), have the latter tail-call the
former.  This saves another 200 bytes, and I've found my ARM710a card now, so
I've even tested it.

In {early,late}_abort_fixup(), return ABORT_FIXUP_FAILED, rather than
panic'ing, if we hit an instruction we can't fix up.  This saves 250-odd bytes
of code, and should allow the caller to print a more useful message.

late_abort_fixup: Get the indentation right!

Replace arm6_dataabt_fixup() and arm7_dataabt_fixup() with early_abort_fixup()
and late_abort_fixup(), based on the abort model in use, rather than the CPU
type.  This cleans up the code and makes it smaller.  Only tested on an
ARM6 -- I can't find my ARM710a card right now.

Initial cpufunc operations for ARM3.  Not actually used yet.

Include opt_cputypes.h, since we use CPU_*.

Don't include parse_cpu_options() unless we're going to use it.  This fixes
a warning on arm26.

Move cpufunc stuff from arm32/arm32 to arm/arm.  The only change involved is
to add recognition of the SA-1100 and SA-1110 for compatibility with hpcarm
(which is now using this code as well).