version 1.4.2.1, 2001/06/21 19:18:46 |
version 1.5, 2002/08/15 01:38:16 |
Line 64 ENTRY(read_multi_1) |
|
Line 64 ENTRY(read_multi_1) |
|
stmfd sp!, {fp, ip, lr, pc} |
stmfd sp!, {fp, ip, lr, pc} |
sub fp, ip, #4 |
sub fp, ip, #4 |
subs r2, r2, #4 /* r2 = length - 4 */ |
subs r2, r2, #4 /* r2 = length - 4 */ |
blt Lrm1_l4 /* less than 4 bytes */ |
blt .Lrm1_l4 /* less than 4 bytes */ |
ands r12, r1, #3 |
ands r12, r1, #3 |
beq Lrm1_main /* aligned destination */ |
beq .Lrm1_main /* aligned destination */ |
rsb r12, r12, #4 |
rsb r12, r12, #4 |
cmp r12, #2 |
cmp r12, #2 |
ldrb r3, [r0] |
ldrb r3, [r0] |
Line 76 ENTRY(read_multi_1) |
|
Line 76 ENTRY(read_multi_1) |
|
ldrgtb r3, [r0] |
ldrgtb r3, [r0] |
strgtb r3, [r1], #1 |
strgtb r3, [r1], #1 |
subs r2, r2, r12 |
subs r2, r2, r12 |
blt Lrm1_l4 |
blt .Lrm1_l4 |
Lrm1_main: |
.Lrm1_main: |
Lrm1loop: |
.Lrm1loop: |
ldrb r3, [r0] |
ldrb r3, [r0] |
ldrb r12, [r0] |
ldrb r12, [r0] |
orr r3, r3, r12, lsl #8 |
orr r3, r3, r12, lsl #8 |
|
|
orr r3, r3, r12, lsl #24 |
orr r3, r3, r12, lsl #24 |
str r3, [r1], #4 |
str r3, [r1], #4 |
subs r2, r2, #4 |
subs r2, r2, #4 |
bge Lrm1loop |
bge .Lrm1loop |
Lrm1_l4: |
.Lrm1_l4: |
adds r2, r2, #4 /* r2 = length again */ |
adds r2, r2, #4 /* r2 = length again */ |
ldmeqdb fp, {fp, sp, pc} |
ldmeqdb fp, {fp, sp, pc} |
moveq pc, r14 |
moveq pc, r14 |
Line 116 ENTRY(write_multi_1) |
|
Line 116 ENTRY(write_multi_1) |
|
stmfd sp!, {fp, ip, lr, pc} |
stmfd sp!, {fp, ip, lr, pc} |
sub fp, ip, #4 |
sub fp, ip, #4 |
subs r2, r2, #4 /* r2 = length - 4 */ |
subs r2, r2, #4 /* r2 = length - 4 */ |
blt Lwm1_l4 /* less than 4 bytes */ |
blt .Lwm1_l4 /* less than 4 bytes */ |
ands r12, r1, #3 |
ands r12, r1, #3 |
beq Lwm1_main /* aligned source */ |
beq .Lwm1_main /* aligned source */ |
rsb r12, r12, #4 |
rsb r12, r12, #4 |
cmp r12, #2 |
cmp r12, #2 |
ldrb r3, [r1], #1 |
ldrb r3, [r1], #1 |
Line 128 ENTRY(write_multi_1) |
|
Line 128 ENTRY(write_multi_1) |
|
ldrgtb r3, [r1], #1 |
ldrgtb r3, [r1], #1 |
strgtb r3, [r0] |
strgtb r3, [r0] |
subs r2, r2, r12 |
subs r2, r2, r12 |
blt Lwm1_l4 |
blt .Lwm1_l4 |
Lwm1_main: |
.Lwm1_main: |
Lwm1loop: |
.Lwm1loop: |
ldr r3, [r1], #4 |
ldr r3, [r1], #4 |
strb r3, [r0] |
strb r3, [r0] |
mov r3, r3, lsr #8 |
mov r3, r3, lsr #8 |
|
|
mov r3, r3, lsr #8 |
mov r3, r3, lsr #8 |
strb r3, [r0] |
strb r3, [r0] |
subs r2, r2, #4 |
subs r2, r2, #4 |
bge Lwm1loop |
bge .Lwm1loop |
Lwm1_l4: |
.Lwm1_l4: |
adds r2, r2, #4 /* r2 = length again */ |
adds r2, r2, #4 /* r2 = length again */ |
ldmeqdb fp, {fp, sp, pc} |
ldmeqdb fp, {fp, sp, pc} |
cmp r2, #2 |
cmp r2, #2 |
|
|
|
|
tst r2, #0x00000001 |
tst r2, #0x00000001 |
tsteq r1, #0x00000003 |
tsteq r1, #0x00000003 |
beq fastinsw |
beq .Lfastinsw |
|
|
/* Non aligned insw */ |
/* Non aligned insw */ |
|
|
inswloop: |
.Linswloop: |
ldr r3, [r0] |
ldr r3, [r0] |
subs r2, r2, #0x00000001 /* Loop test in load delay slot */ |
subs r2, r2, #0x00000001 /* Loop test in load delay slot */ |
strb r3, [r1], #0x0001 |
strb r3, [r1], #0x0001 |
mov r3, r3, lsr #8 |
mov r3, r3, lsr #8 |
strb r3, [r1], #0x0001 |
strb r3, [r1], #0x0001 |
bgt inswloop |
bgt .Linswloop |
|
|
mov pc, lr |
mov pc, lr |
|
|
/* Word aligned insw */ |
/* Word aligned insw */ |
|
|
fastinsw: |
.Lfastinsw: |
|
|
fastinswloop: |
.Lfastinswloop: |
ldr r3, [r0, #0x0002] /* take advantage of nonaligned |
ldr r3, [r0, #0x0002] /* take advantage of nonaligned |
* word accesses */ |
* word accesses */ |
ldr ip, [r0] |
ldr ip, [r0] |
|
|
orr r3, r3, ip, lsl #16 |
orr r3, r3, ip, lsl #16 |
str r3, [r1], #0x0004 /* Store */ |
str r3, [r1], #0x0004 /* Store */ |
subs r2, r2, #0x00000002 /* Next */ |
subs r2, r2, #0x00000002 /* Next */ |
bgt fastinswloop |
bgt .Lfastinswloop |
|
|
mov pc, lr |
mov pc, lr |
|
|
|
|
|
|
tst r2, #0x00000001 |
tst r2, #0x00000001 |
tsteq r1, #0x00000003 |
tsteq r1, #0x00000003 |
beq fastoutsw |
beq .Lfastoutsw |
|
|
/* Non aligned outsw */ |
/* Non aligned outsw */ |
|
|
outswloop: |
.Loutswloop: |
ldrb r3, [r1], #0x0001 |
ldrb r3, [r1], #0x0001 |
ldrb ip, [r1], #0x0001 |
ldrb ip, [r1], #0x0001 |
subs r2, r2, #0x00000001 /* Loop test in load delay slot */ |
subs r2, r2, #0x00000001 /* Loop test in load delay slot */ |
orr r3, r3, ip, lsl #8 |
orr r3, r3, ip, lsl #8 |
orr r3, r3, r3, lsl #16 |
orr r3, r3, r3, lsl #16 |
str r3, [r0] |
str r3, [r0] |
bgt outswloop |
bgt .Loutswloop |
|
|
mov pc, lr |
mov pc, lr |
|
|
/* Word aligned outsw */ |
/* Word aligned outsw */ |
|
|
fastoutsw: |
.Lfastoutsw: |
|
|
fastoutswloop: |
.Lfastoutswloop: |
ldr r3, [r1], #0x0004 /* r3 = (H)(L) */ |
ldr r3, [r1], #0x0004 /* r3 = (H)(L) */ |
subs r2, r2, #0x00000002 /* Loop test in load delay slot */ |
subs r2, r2, #0x00000002 /* Loop test in load delay slot */ |
|
|
|
|
* str ip, [r0] |
* str ip, [r0] |
*/ |
*/ |
|
|
bgt fastoutswloop |
bgt .Lfastoutswloop |
|
|
mov pc, lr |
mov pc, lr |
|
|
|
|
|
|
stmfd sp!, {r4,r5,lr} |
stmfd sp!, {r4,r5,lr} |
|
|
insw16loop: |
.Linsw16loop: |
ldr r3, [r0, #0x0002] /* take advantage of nonaligned |
ldr r3, [r0, #0x0002] /* take advantage of nonaligned |
* word accesses */ |
* word accesses */ |
ldr lr, [r0] |
ldr lr, [r0] |
|
|
|
|
stmia r1!, {r3-r5,ip} |
stmia r1!, {r3-r5,ip} |
subs r2, r2, #0x00000008 /* Next */ |
subs r2, r2, #0x00000008 /* Next */ |
bgt insw16loop |
bgt .Linsw16loop |
|
|
ldmfd sp!, {r4,r5,pc} /* Restore regs and go home */ |
ldmfd sp!, {r4,r5,pc} /* Restore regs and go home */ |
|
|
|
|
|
|
stmfd sp!, {r4,r5,lr} |
stmfd sp!, {r4,r5,lr} |
|
|
outsw16loop: |
.Loutsw16loop: |
ldmia r1!, {r4,r5,ip,lr} |
ldmia r1!, {r4,r5,ip,lr} |
|
|
eor r3, r4, r4, lsl #16 /* r3 = (A^B)(B) */ |
eor r3, r4, r4, lsl #16 /* r3 = (A^B)(B) */ |
|
|
str lr, [r0] |
str lr, [r0] |
|
|
subs r2, r2, #0x00000008 |
subs r2, r2, #0x00000008 |
bgt outsw16loop |
bgt .Loutsw16loop |
|
|
ldmfd sp!, {r4,r5,pc} /* and go home */ |
ldmfd sp!, {r4,r5,pc} /* and go home */ |
|
|
|
|
mov lr, #0xff000000 |
mov lr, #0xff000000 |
orr lr, lr, #0x00ff0000 |
orr lr, lr, #0x00ff0000 |
|
|
inswm8_loop8: |
.Linswm8_loop8: |
cmp r2, #8 |
cmp r2, #8 |
bcc inswm8_l8 |
bcc .Linswm8_l8 |
|
|
ldmia r0, {r3-r9,ip} |
ldmia r0, {r3-r9,ip} |
|
|
|
|
stmia r1!, {r3-r6} |
stmia r1!, {r3-r6} |
|
|
subs r2, r2, #0x00000008 /* Next */ |
subs r2, r2, #0x00000008 /* Next */ |
bne inswm8_loop8 |
bne .Linswm8_loop8 |
beq inswm8_l1 |
beq .Linswm8_l1 |
|
|
inswm8_l8: |
.Linswm8_l8: |
cmp r2, #4 |
cmp r2, #4 |
bcc inswm8_l4 |
bcc .Linswm8_l4 |
|
|
ldmia r0, {r3-r6} |
ldmia r0, {r3-r6} |
|
|
|
|
stmia r1!, {r3-r4} |
stmia r1!, {r3-r4} |
|
|
subs r2, r2, #0x00000004 |
subs r2, r2, #0x00000004 |
beq inswm8_l1 |
beq .Linswm8_l1 |
|
|
inswm8_l4: |
.Linswm8_l4: |
cmp r2, #2 |
cmp r2, #2 |
bcc inswm8_l2 |
bcc .Linswm8_l2 |
|
|
ldmia r0, {r3-r4} |
ldmia r0, {r3-r4} |
|
|
|
|
str r3, [r1], #0x0004 |
str r3, [r1], #0x0004 |
|
|
subs r2, r2, #0x00000002 |
subs r2, r2, #0x00000002 |
beq inswm8_l1 |
beq .Linswm8_l1 |
|
|
inswm8_l2: |
.Linswm8_l2: |
cmp r2, #1 |
cmp r2, #1 |
bcc inswm8_l1 |
bcc .Linswm8_l1 |
|
|
ldr r3, [r0] |
ldr r3, [r0] |
subs r2, r2, #0x00000001 /* Test in load delay slot */ |
subs r2, r2, #0x00000001 /* Test in load delay slot */ |
|
|
strb r3, [r1], #0x0001 |
strb r3, [r1], #0x0001 |
|
|
|
|
inswm8_l1: |
.Linswm8_l1: |
ldmfd sp!, {r4-r9,pc} /* And go home */ |
ldmfd sp!, {r4-r9,pc} /* And go home */ |
|
|
/* |
/* |
|
|
|
|
stmfd sp!, {r4-r8,lr} |
stmfd sp!, {r4-r8,lr} |
|
|
outswm8_loop8: |
.Loutswm8_loop8: |
cmp r2, #8 |
cmp r2, #8 |
bcc outswm8_l8 |
bcc .Loutswm8_l8 |
|
|
ldmia r1!, {r3,r5,r7,ip} |
ldmia r1!, {r3,r5,r7,ip} |
|
|
|
|
stmia r0, {r3-r8,ip,lr} |
stmia r0, {r3-r8,ip,lr} |
|
|
subs r2, r2, #0x00000008 /* Next */ |
subs r2, r2, #0x00000008 /* Next */ |
bne outswm8_loop8 |
bne .Loutswm8_loop8 |
beq outswm8_l1 |
beq .Loutswm8_l1 |
|
|
outswm8_l8: |
.Loutswm8_l8: |
cmp r2, #4 |
cmp r2, #4 |
bcc outswm8_l4 |
bcc .Loutswm8_l4 |
|
|
ldmia r1!, {r3-r4} |
ldmia r1!, {r3-r4} |
|
|
|
|
stmia r0, {r5-r8} |
stmia r0, {r5-r8} |
|
|
subs r2, r2, #0x00000004 |
subs r2, r2, #0x00000004 |
beq outswm8_l1 |
beq .Loutswm8_l1 |
|
|
outswm8_l4: |
.Loutswm8_l4: |
cmp r2, #2 |
cmp r2, #2 |
bcc outswm8_l2 |
bcc .Loutswm8_l2 |
|
|
ldr r3, [r1], #0x0004 /* r3 = (A)(B) */ |
ldr r3, [r1], #0x0004 /* r3 = (A)(B) */ |
subs r2, r2, #0x00000002 /* Done test in Load delay slot */ |
subs r2, r2, #0x00000002 /* Done test in Load delay slot */ |
|
|
|
|
stmia r0, {r4, r5} |
stmia r0, {r4, r5} |
|
|
beq outswm8_l1 |
beq .Loutswm8_l1 |
|
|
outswm8_l2: |
.Loutswm8_l2: |
cmp r2, #1 |
cmp r2, #1 |
bcc outswm8_l1 |
bcc .Loutswm8_l1 |
|
|
ldrb r3, [r1], #0x0001 |
ldrb r3, [r1], #0x0001 |
ldrb r4, [r1], #0x0001 |
ldrb r4, [r1], #0x0001 |
|
|
orr r3, r3, r3, lsl #16 |
orr r3, r3, r3, lsl #16 |
str r3, [r0] |
str r3, [r0] |
|
|
outswm8_l1: |
.Loutswm8_l1: |
ldmfd sp!, {r4-r8,pc} /* And go home */ |
ldmfd sp!, {r4-r8,pc} /* And go home */ |