Annotation of src/sys/arch/amd64/amd64/spl.S, Revision 1.6.2.1
1.6.2.1 ! ad 1: /* $NetBSD: spl.S,v 1.6 2007/02/09 21:55:01 ad Exp $ */
1.1 fvdl 2:
3: /*
4: * Copyright (c) 2003 Wasabi Systems, Inc.
5: * All rights reserved.
6: *
7: * Written by Frank van der Linden for Wasabi Systems, Inc.
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions and the following disclaimer.
14: * 2. Redistributions in binary form must reproduce the above copyright
15: * notice, this list of conditions and the following disclaimer in the
16: * documentation and/or other materials provided with the distribution.
17: * 3. All advertising materials mentioning features or use of this software
18: * must display the following acknowledgement:
19: * This product includes software developed for the NetBSD Project by
20: * Wasabi Systems, Inc.
21: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22: * or promote products derived from this software without specific prior
23: * written permission.
24: *
25: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35: * POSSIBILITY OF SUCH DAMAGE.
36: */
37:
38: /*
1.6 ad 39: * Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
1.1 fvdl 40: * All rights reserved.
41: *
42: * This code is derived from software contributed to The NetBSD Foundation
1.6 ad 43: * by Charles M. Hannum and Andrew Doran.
1.1 fvdl 44: *
45: * Redistribution and use in source and binary forms, with or without
46: * modification, are permitted provided that the following conditions
47: * are met:
48: * 1. Redistributions of source code must retain the above copyright
49: * notice, this list of conditions and the following disclaimer.
50: * 2. Redistributions in binary form must reproduce the above copyright
51: * notice, this list of conditions and the following disclaimer in the
52: * documentation and/or other materials provided with the distribution.
53: * 3. All advertising materials mentioning features or use of this software
54: * must display the following acknowledgement:
55: * This product includes software developed by the NetBSD
56: * Foundation, Inc. and its contributors.
57: * 4. Neither the name of The NetBSD Foundation nor the names of its
58: * contributors may be used to endorse or promote products derived
59: * from this software without specific prior written permission.
60: *
61: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
62: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
63: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
64: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
65: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
66: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
67: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
68: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
69: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
70: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
71: * POSSIBILITY OF SUCH DAMAGE.
72: */
73:
74: #include "opt_ddb.h"
75:
76: #define ALIGN_TEXT .align 16,0x90
77:
78: #include <machine/asm.h>
79: #include <machine/psl.h>
80: #include <machine/trap.h>
81: #include <machine/segments.h>
82: #include <machine/frameasm.h>
83:
84: #include "assym.h"
85:
86: .data
87: .globl _C_LABEL(netisr)
88: .text
89:
90: #if 0
91: #if defined(PROF) || defined(GPROF)
92: /*
93: * XXXX TODO
94: */
95: .globl _C_LABEL(splhigh), _C_LABEL(splx)
96:
97: ALIGN_TEXT
98: _C_LABEL(splhigh):
1.5 ad 99: movl CPUVAR(ILEVEL), %eax
100: movl $IPL_HIGH, CPUVAR(ILEVEL)
1.1 fvdl 101: ret
102:
103: ALIGN_TEXT
104: _C_LABEL(splx):
1.5 ad 105: movq %rdi, %rcx
106: SPLLOWER(_C_LABEL(Xspllower))
1.1 fvdl 107: ret
108: #endif /* PROF || GPROF */
109: #endif
1.6 ad 110:
111: /*
1.6.2.1 ! ad 112: * int splraise(int s);
! 113: */
! 114: .align 32
! 115:
! 116: ENTRY(splraise)
! 117: movl CPUVAR(ILEVEL),%eax
! 118: cmpl %edi,%eax
! 119: cmoval %eax,%edi
! 120: movl %edi,CPUVAR(ILEVEL)
! 121: ret
! 122:
! 123: /*
! 124: * void softintr(int sir);
! 125: *
! 126: * Software interrupt registration.
! 127: */
! 128: .align 32
! 129:
! 130: ENTRY(softintr)
! 131: movl %edi,%ecx
! 132: movl $1,%eax
! 133: shll %cl,%eax
! 134: orl %eax,CPUVAR(IPENDING)
! 135: ret
! 136:
! 137: /*
1.6 ad 138: * void spllower(int s);
139: *
140: * Must be the same size as i686_spllower(). This must use
141: * pushf/cli/popf as it is used early in boot where interrupts
142: * are disabled via eflags/IE.
143: */
144: .align 64
145:
146: ENTRY(spllower)
147: cmpl CPUVAR(ILEVEL), %edi
148: jae 1f
149: movl CPUVAR(IUNMASK)(,%edi,4), %edx
150: pushf
151: cli
152: testl CPUVAR(IPENDING), %edx
153: jnz 2f
154: movl %edi, CPUVAR(ILEVEL)
155: popf
156: 1:
157: rep
158: ret
159: 2:
160: popf
161: jmp _C_LABEL(Xspllower)
162: .align 64
163: LABEL(spllower_end)
164:
165: /*
166: * void amd64_spllower(int s);
167: *
168: * For cmpxchg8b, edx/ecx are the high words and eax/ebx the low.
169: *
170: * edx : eax = old level / old ipending
171: * ecx : ebx = new level / old ipending
172: */
173: .align 64
174:
175: ENTRY(amd64_spllower)
176: movl CPUVAR(ILEVEL),%edx
177: cmpl %edx,%edi /* new level is lower? */
178: pushq %rbx
179: jae,pn 1f
180: movl CPUVAR(IPENDING),%eax
181: movl %edi,%ecx
182: testl %eax,CPUVAR(IUNMASK)(,%rcx,4)/* deferred interrupts? */
183: movl %eax,%ebx
184: /*
185: * On the P4 this jump is cheaper than patching in junk
186: * using cmov. Is cmpxchg expensive if it fails?
187: */
188: jnz,pn 2f
189: cmpxchg8b CPUVAR(ISTATE) /* swap in new ilevel */
190: jnz,pn 2f
191: 1:
192: popq %rbx
193: ret
194: 2:
195: popq %rbx
196: LABEL(amd64_spllower_patch)
197: jmp _C_LABEL(Xspllower)
198:
199: .align 64
200: LABEL(amd64_spllower_end)
201:
1.1 fvdl 202: /*
1.6 ad 203: * void Xspllower(int s);
204: *
1.1 fvdl 205: * Process pending interrupts.
206: *
207: * Important registers:
208: * ebx - cpl
209: * r13 - address to resume loop at
210: *
211: * It is important that the bit scan instruction is bsr, it will get
212: * the highest 2 bits (currently the IPI and clock handlers) first,
213: * to avoid deadlocks where one CPU sends an IPI, another one is at
214: * splipi() and defers it, lands in here via splx(), and handles
215: * a lower-prio one first, which needs to take the kernel lock -->
216: * the sending CPU will never see the that CPU accept the IPI
217: * (see pmap_tlb_shootnow).
218: */
1.6 ad 219: nop
220: .align 4 /* Avoid confusion with amd64_spllower_end */
221:
1.1 fvdl 222: IDTVEC(spllower)
223: pushq %rbx
224: pushq %r13
225: pushq %r12
226: movl %edi,%ebx
227: leaq 1f(%rip),%r13 # address to resume loop at
228: 1: movl %ebx,%eax # get cpl
229: movl CPUVAR(IUNMASK)(,%rax,4),%eax
230: cli
231: andl CPUVAR(IPENDING),%eax # any non-masked bits left?
232: jz 2f
233: bsrl %eax,%eax
234: btrl %eax,CPUVAR(IPENDING)
235: movq CPUVAR(ISOURCES)(,%rax,8),%rax
236: jmp *IS_RECURSE(%rax)
237: 2:
238: movl %ebx,CPUVAR(ILEVEL)
239: sti
240: popq %r12
241: popq %r13
242: popq %rbx
243: ret
244:
245: /*
246: * Handle return from interrupt after device handler finishes.
247: *
248: * Important registers:
249: * ebx - cpl to restore
250: * r13 - address to resume loop at
251: */
252: IDTVEC(doreti)
253: popq %rbx # get previous priority
254: decl CPUVAR(IDEPTH)
255: leaq 1f(%rip),%r13
256: 1: movl %ebx,%eax
257: movl CPUVAR(IUNMASK)(,%rax,4),%eax
258: cli
259: andl CPUVAR(IPENDING),%eax
260: jz 2f
261: bsrl %eax,%eax # slow, but not worth optimizing
262: btrl %eax,CPUVAR(IPENDING)
263: movq CPUVAR(ISOURCES)(,%rax, 8),%rax
264: jmp *IS_RESUME(%rax)
265: 2: /* Check for ASTs on exit to user mode. */
266: movl %ebx,CPUVAR(ILEVEL)
1.6 ad 267: movq CPUVAR(CURLWP),%r14
268: 5: CHECK_ASTPENDING(%r14)
1.1 fvdl 269: je 3f
270: testb $SEL_RPL,TF_CS(%rsp)
271: jz 3f
1.6 ad 272: CLEAR_ASTPENDING(%r14)
1.1 fvdl 273: sti
274: movl $T_ASTFLT,TF_TRAPNO(%rsp) /* XXX undo later.. */
275: /* Pushed T_ASTFLT into tf_trapno on entry. */
1.2 fvdl 276: movq %rsp,%rdi
1.1 fvdl 277: call _C_LABEL(trap)
278: cli
279: jmp 5b
280: 3: INTRFASTEXIT
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