CVS log for src/sys/arch/amd64/amd64/db_interface.c

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Default branch: MAIN

Pull up following revision(s) (requested by rin in ticket #900):

	sys/arch/amd64/amd64/db_interface.c: revision 1.42
	sys/arch/i386/i386/db_interface.c: revision 1.89

when cpus are paused (spinning) in DDB, call x86_pause() in the loop,
hopefully this can reduce power usage while doing nothing.

ok chs@
XXX: apply to i386

i386: DDB: Call x86_pause() (`pause` insn) when CPUs are paused
as already done for amd64:
https://mail-index.netbsd.org/source-changes/2023/07/31/msg146423.html

`pause` insn has been introduced to Pentium 4. However, its opcode is
consisted of `nop` (0x90) followed by `rep` prefix (0xf3), and therefore
interpreted as `nop` for older processors. Intel assured this behavior [1].

Also note that we already use `pause` unconditionally for i386.

Briefly tested on QEMU.

[1] Intel, ``AP-949 Using Spin-Loops on Intel Pentium 4 Processor and
    Intel Xeon Processor'', Version 2.1, Sec 2.1.1. (2001)

when cpus are paused (spinning) in DDB, call x86_pause() in the loop,
hopefully this can reduce power usage while doing nothing.

ok chs@

XXX: pullup-*
XXX: apply to i386

ddb/db_active.h: New home for extern db_active.

This can be included unconditionally, and db_active can then be
queried unconditionally; if DDB is not in the kernel, then db_active
is a constant zero.  Reduces need for #include opt_ddb.h, #ifdef DDB.

x86: improve error handling related to idt_vec_alloc()

Sync with HEAD.

introduce DDB_END_CMD and replace more than 20 copies of the same
list of NULLs and 0.  idea from rillig@.

all touched ports built, several booted.

Introduce per-cpu IDTs

This is realized by following modifications:
- Add IDT pages and its allocation maps for each cpu in "struct cpu_info"
- Load per-cpu IDTs at cpu_init_idt(struct cpu_info*)
- Copy the IDT entries for cpu0 to other CPUs at attach
   - These are, for example, exceptions, db, system calls, etc.

And, added a kernel option named PCPU_IDT to enable the feature.

Merge changes from current as of 20200406

Pull up following revision(s) (requested by christos in ticket #750):

	sys/arch/amd64/amd64/db_interface.c: revision 1.37

Fix boot -c or -d by avoiding ipi handling before the vector is initialized.

Sync with head.

Fix boot -c or -d by avoiding ipi handling before the vector is initialized.

Sync with HEAD

Fix NLAPIC, NISA and NIOAPIC related conditional compile errors.

This will allow us to now compile an amd64 kernel without PCI.

No functional changes.

We reorganise definitions for XEN source support as follows:

XEN - common sources required for baseline XEN support.
XENPV - sources required for support of XEN in PV mode.
XENPVHVM - sources required for support for XEN in HVM mode.
XENPVH - sources required for support for XEN in PVH mode.

Ssync with HEAD

Make XEN use the same api as native, for idt vector allocation
and registration.

lidt() placed in xenfunc() on maxv@ suggestion.

There should be no functional change due to this commit.

Tested on amd64 native and XEN.

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Pull up following revision(s) (requested by christos in ticket #696):

	sys/arch/amd64/amd64/vector.S: revision 1.62 (patch)
	sys/arch/x86/include/intr.h: revision 1.55
	sys/arch/i386/i386/vector.S: revision 1.77
	sys/arch/i386/i386/db_interface.c: revision 1.82 (patch)
	sys/arch/amd64/amd64/spl.S: revision 1.34 (patch)
	sys/arch/amd64/amd64/db_interface.c: revision 1.33 (patch)
	sys/arch/x86/x86/intr.c: revision 1.125
	sys/arch/i386/i386/spl.S: revision 1.43 (patch)
	sys/arch/i386/i386/machdep.c: revision 1.805 (patch)
	sys/arch/x86/x86/lapic.c: revision 1.66 (patch)

Rename the DDB IPI IDT vectors for consistency. ok maxv@

Rename Xpreempt{recurse,resume} -> X{recurse,resume}_preempt so that
they fit the pattern. Also the debugger trap sniffer matches them
without adding special entries...

XXX: pullup-8.

Rename the DDB IPI IDT vectors for consistency. ok maxv@

Remove double declaration; 'ddb_regs' is already declared as a macro
in db_machdep.h if MULTIPROCESSOR is on, and the macro has higher
priority.

Don't declare 'ddb_regs' locally in this case, because it is misleading.
Part of PR/52964.

Define ddb_regp only if MULTIPROCESSOR (NFC)

Fix NULL pointer dereference via ddb_regs

ddb_regs can be *ddb_regp (see db_machdep.h) so ddb_regp should be NULL-ed
after dereference to ddb_regs.

Also dbreg should be restored to ddb_regp because ddb_regp can be changed
by db_mach_cpu during db_trap.

Fix PR 52964
Helped by nonaka@

make it compile without MULTIPROCESSOR (xen?)

Reset ddb_regp to NULL. Reported by David Binderman in PR/52964.

update from HEAD

Sync with HEAD

Rename intrddb -> intrddbipi, like i386.

Reduce the diff between amd64 and i386.

x86: Add preliminary x2APIC support.

x2APIC is used only when x2APIC is enabled in BIOS/UEFI.
LAPIC ID is not supported above 256.

Sync with HEAD. Most notably: uvm/pmap work done by rmind@, and MP Xen
work of cherry@.

No regression observed on suspend/restore.

make ddb minimally MP aware

grow MP support for i386. boots to single user

Sync with HEAD.

Initial import of xen MP sources, with kernel and userspace tests.
 - this is a source priview.
 - boots to single user.
 - spurious interrupt and pmap related panics are normal

Sync with head.

sync with head

Clean up excessive #ifdef'age of NMI trap handling for amd64/i386/xen.
Handle NMI in all Xen kernels.

sync with head

Sync with HEAD

Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits.  Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

Sync with HEAD

sync with head

Declare trap name array as extern const char *const [] to match how
it's defined in trap.c. (Should really be in a header, of course.)
Compile-tested.

sync with head.

Sync with HEAD.

Match declaration of trap_type in trap.c.

Sync with HEAD.

Sync with HEAD.

- Rename cpu_lookup_byindex() to cpu_lookup(). The hardware ID isn't of
  interest to MI code. No functional change.
- Change /dev/cpu to operate on cpu index, not hardware ID. Now cpuctl
  shouldn't print confused output.

Sync w/ -current. 34 merge conflicts to follow.

sync with head

Sync with HEAD.

Another use of X86_MAXPROCS.

Kill use of X86_MAXPROCS.

sync with head.

sync with head.

- Make cpu_number() return MI index, otherwise the pmap cannot work on
  systems with lapic IDs > X86_MAXPROCS.
- Kill cpu_info[] array and use MI cpu_lookup_byindex().

sync with HEAD

Sync with HEAD.

sync with head

Sync with HEAD.

Sync with HEAD.

Sync with HEAD.

Use the new atomic ops.

Reinclude machine/cpuvar.h lost in bouyer-xenamd64 merge; make GENERIC.MP
kernel build again.

Pull up the bouyer-xenamd64 branch to HEAD. This brings in amd64 support
to NetBSD/Xen, both Dom0 and DomU.

Sync with HEAD.

Sync with HEAD.

Sync with HEAD

Disable TLB shootdown IPIs while in the debugger. Crashdumps may try to
use them, and all but one CPU is paused. Reported and tested by martin@.

sync with HEAD

sync with head.

amd64 (aka x86-64) support for Xen. Based on the OpenBSD port done by
Mathieu Ropert in 2006.
DomU-only for now. An INSTALL_XEN3_DOMU kernel with a ramdisk will boot to
sysinst if you're lucky. Often it panics because a runable LWP has
a NULL stack (really, it's all of l->l_addr which is has been zeroed out
while the process was on the queue !)
TODO:
- bug fixes :)
- Most of the xpq_* functions should be shared with xen/i386
- The xen/i386 assembly bootstrap code should be remplaced with the C
  version in xenamd64/amd64/xpmap.c
- see if a config(5) trick could allow to merge xenamd64 back to xen or amd64.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Sync with head.

sync with head.

Sync with HEAD

Sync with HEAD.

Add verbose help for (the one and only) "mach" command.

Add a new option DDB_VERBOSE_HELP that adds online help to ddb.
From Adam Hamsik.
Minor modifications by me, all bugs are probably mine.

sync with head.

Sync with head.

Sync with HEAD.

Sync with head.

Ansify, de-__P(), unregister.

Convert i386 and amd64 to the new atomic ops API.

- sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.

sync with head.

miscellaneous fallout from the great boolean rototill.

TRUE -> true, FALSE -> false

merge ktrace-lwp.

Sync with HEAD. Here we go again...

adapt to ddb constification

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Uppercase CPU, plural is CPUs.

Make sure to include opt_foo.h if a defflag option FOO is used.

Rename the x86_64 port to amd64, as this is the actual name used for
the processor family now. x86_64 is kept as the MACHINE_ARCH value,
since it's already widely used (by e.g. the toolchain, etc), and
by other operating systems.