CVS log for src/sys/arch/alpha/pci/siovar.h

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Sync with HEAD.

Reduce code duplication among platforms that use the i82378 SIO to
route PCI interrupts to the ISA PIC by refactoring it into a new
sio_pirq_intr_map() function.

Changes to make MPSAFE interrupts work on Alpha:

- Remove the ipl argument to scb_set() and the associated array of
  "mpsafe" booleans initialized based on the ipl.  It was bogus
  anyway; all IPL_{BIO,NET,TTY}, etc. values are aliases of IPL_VM,
  and for all practical purposes, there is really only one device
  interrrupt level on Alpha anyway.  Intead, we now treat all dispatches
  from the SCB vector table as MP-safe, and it is now the handler for
  that vector who is responsible for acquiring the KERNEL_LOCK if needed.

- Update the direct interrupt vector handlers in jensenio and TURBOchannel
  to acquire the KERNEL_LOCK.

- Introduce a new ALPHA_INTR_MPSAFE flag, and add a flags argument to
  alpha_shared_intr_establish().  When it is set, indicate that the
  handler is MP-safe.  Update alpha_shared_intr_dispatch() to pay
  attention and acquire the KERNEL_LOCK (or not) as indicated.

- Re-factor all of the PCI interrupt handling, providing "generic PCI"
  "PCI interrupts through ISA IRQs" implementations to significantly
  reduce code duplication.  Supplement the PCI chipset tag with more
  info to facilitate this, and make the PCI interrupt-related routines
  take a pci_chipset_tag_t argument rather than a void * argument.

- Because PCI interrupts on KN8AE are dispatched directly from the
  SCB, provide a wrapper for non-MPSAFE interrupt handlers that
  acquires the KERNEL_LOCK.

- Change the pci_intr_handle_t type to be a struct rather than an
  integer type in order to catch any direct use of it as a value.
  Add a set of functions to interact with pci_intr_handle_t, including
  setting interrupt flags.

- Implement pci_intr_setattr() so that the PCI_INTR_MPSAFE attribute
  can be set on a pci_intr_handle_t.

- While I'm here, make all of the MI PCI back-end operations call
  through real functions rather than hopping directly through function
  pointers in the chipset tag.

This change looks a lot bigger than it really is because of the re-factor
in the plethora of model-specific PCI interrupt back-ends.  The KN8AE,
KN300, and T2/T3/T4 (Sable) are largely un-changed.

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

gc sprintf; reduce local static usage of interrupt strings that are only
used once for autoconf printing.

Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.

sync with head.

Sync with HEAD.

Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Sync w/ netbsd-1-5-base.

Switch to the new `evcnt' mechanism for counting interrupts.  Maintain
a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.

Implement the more flexiable `evcnt' interface as discussed (briefly) on
tech-kern and now documented in evcnt(9).

Prototype sio_intr_alloc().

Pass the pci_chipset_tag_t to sio_intr_setup().  XXX This code should be
rearranged so that other non-PCI-but-in-all-other-ways-ISA-PIC-like
devices can share code.

sync the nwscons branch up with yesterday's version of the trunk.
Lots of conflicts/changes because of the RCS Id format changes.
Also, a few cleanups and corrections.

clean up NetBSD RCS ID strings

update for new bus.h macros.  bus_io_* and bus_mem_* integrated into
single bus_space_* framework.  Unfortunately, bus_space_{read,write}_*
operations still imply barriers.  That will change soon.

(1)     Clean up interrupt handling slightly.

clean up copyrights and RCS IDs

clean up for new ISA and 'bus' code, etc.

wholesale update from my NetBSD/Alpha source tree.  Includes:
	Support for AXPpci CPUs,
	Support for AlphaStation 600 CPUs,
	new boot block structure, which requires an 'installboot'
	    program and works a lot like the NetBSD/sparc boot blocks.