CVS log for src/sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c

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bus_space_alloc() -- vmem(9) requires an allocation stragegy flag, so
make sure to pass one.

Convert the Alpha port's bus_space back-end to manage address space
with vmem(9) arenas (using statically-allocated private boundary tags
for very early-in-boot) rather than extent(9).

As a side-effect, there's arguments to some initialization functions
that are no longer required, so garbage-collect those, update all the
call sites.

Sync with HEAD.

Moar static.

Revert previous.  PR/48431 claims ALPHA_PHYS_TO_K0SEG() is necessary.

Actually CHIP_MEM_SYS_START(v) seems a physical address per *_mem_map()
function, but I don't think mmap() function should return K0SEG address
(it should return PA cookie IIUC) so I guess there is something wrong
in Titan's bus space functions.  I'll investigate them later.

bus_space_mmap(9) function should return alpha_btop(PA), not alpha_btop(VA).

Pointed out in PR port-alpha/48431 from nullnilaki.

sync with head

merge to -current.

Do a minor cleanup of alpha (this will make applying pullups post branching
easier).
u_int{8,16,32,64}_t -> uint{*}_t
Change all old-style definitions to C89 prototypes.
Whitespace cleanup.
Constification in db_disasm.c

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

change inline to static inline to appease gcc 4.5.

Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.

sync with head.

Sync with HEAD.

Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

Sync with HEAD.

sync with head.

sync with head.

Remove clause 3 and 4 from TNF licenses

sync with head.

Sync with HEAD.

Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

merge ktrace-lwp.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

add __KERNEL_RCSID()  (using 1,  for #included .c files)

Sync kqueue branch with -current.

Catch up with -current.

Catch up to -current.

BWX-addressable space is aways linear, so always allow BUS_SPACE_MAP_LINEAR
requests to succeed (and ignore BUS_SPACE_MAP_PREFETCHABLE, since it makes
no difference in BWX-addressable space).

Update the kqueue branch to HEAD.

Typos, pointed out by Luke Mewburn (gee, I guess I built a kernel
other than GENERIC).

Implement bus_space_mmap().

Revert previous -- we'll do it differently.

Increase the number of static extent descriptors from 8 to 16,
and add a means for calling a chip-specific init hook.

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Update from trunk:
Implement bus_get_window on Tsunami and MCPCIA, and compensate for
the Cool sign-extend hack we use on EV6 when mapping PCI space into
userspace.

Do the previously slightly differently, to avoid confusing the internal
space extent maps.  Pointed out by msaitoh@netbsd.org.  (Someone should
send me an EV6 machine!)

Because of the Cool sign-extension hack we use to access PCI space,
the `get window' method ends up with the wrong physical address to
pass onto userspace (which wants to mmap the space).

Compensate by adding a CHIP_PHYSADDR() macro which un-hacks the address
suitably for mapping with other-than-KSEG.

implement bus_space_vaddr()

- Add a bus space method for getting the translation for a window.
- Add sysarch methods for "get bus window count", "get bus window",
  and "pci conf read/write".

These are a hack, but they're what's necessary in order to make
XFree86 work in its current state.

Add an internal bus space method alpha_bus_space_translate(), which
provides a method to translate an address on an I/O bus into a sysBus
address, along with acccess method information.

Changed cacheable -> prefetchable.  [sync w/ swiz]

Pull up to last week's -current.

Pull in the BWX inlines.  We expect the arch to be set appropriately for
the assembler before these files are pulled in by the chip-sepecific files.

use current bus_space interface names for barrier ops

Revert cdevsw mmap routines to return int.

Provide a hook for bypassing space accounting, needed to support ISA PnP
for now.

Oops, don't forget to fill in *addrp.

Implement bus_space_{alloc,free}() for BWX bus space.

Add support for using BWX for PCI config space and PCI i/o and mem space
on the ALCOR2 and Pyxis.  BWX is enabled iff:
- It hasn't been disabled by the user (patch `cia_use_bwx' or build cia.o
  with the option "CIA_USE_BWX=0"),
- it's enabled in CIA_CSR_CNFG,
- we are running on an EV5-family processor,
- BWX is in the processor's capabilities mask.