Annotation of src/sys/arch/alpha/include/lock.h, Revision 1.12
1.12 ! thorpej 1: /* $NetBSD: lock.h,v 1.11 2000/11/20 20:17:13 thorpej Exp $ */
1.1 thorpej 2:
3: /*-
1.9 thorpej 4: * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
1.1 thorpej 5: * All rights reserved.
6: *
7: * This code is derived from software contributed to The NetBSD Foundation
8: * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9: * NASA Ames Research Center.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
38: */
39:
40: /*
41: * Machine-dependent spin lock operations.
42: */
43:
1.4 thorpej 44: #ifndef _ALPHA_LOCK_H_
45: #define _ALPHA_LOCK_H_
46:
1.6 thorpej 47: typedef __volatile int __cpu_simple_lock_t;
48:
1.5 thorpej 49: #define __SIMPLELOCK_LOCKED 1
50: #define __SIMPLELOCK_UNLOCKED 0
1.4 thorpej 51:
52: static __inline void
1.6 thorpej 53: __cpu_simple_lock_init(__cpu_simple_lock_t *alp)
1.4 thorpej 54: {
55:
56: __asm __volatile(
1.5 thorpej 57: "# BEGIN __cpu_simple_lock_init\n"
1.4 thorpej 58: " stl $31, %0 \n"
59: " mb \n"
1.5 thorpej 60: " # END __cpu_simple_lock_init"
61: : "=m" (*alp));
1.4 thorpej 62: }
63:
64: static __inline void
1.6 thorpej 65: __cpu_simple_lock(__cpu_simple_lock_t *alp)
1.4 thorpej 66: {
67: unsigned long t0;
68:
69: /*
70: * Note, if we detect that the lock is held when
71: * we do the initial load-locked, we spin using
72: * a non-locked load to save the coherency logic
73: * some work.
74: */
75:
76: __asm __volatile(
1.5 thorpej 77: "# BEGIN __cpu_simple_lock\n"
1.4 thorpej 78: "1: ldl_l %0, %3 \n"
79: " bne %0, 2f \n"
80: " bis $31, %2, %0 \n"
81: " stl_c %0, %1 \n"
82: " beq %0, 3f \n"
83: " mb \n"
84: " br 4f \n"
85: "2: ldl %0, %3 \n"
86: " beq %0, 1b \n"
87: " br 2b \n"
88: "3: br 1b \n"
89: "4: \n"
1.5 thorpej 90: " # END __cpu_simple_lock\n"
91: : "=r" (t0), "=m" (*alp)
92: : "i" (__SIMPLELOCK_LOCKED), "1" (*alp));
1.4 thorpej 93: }
94:
95: static __inline int
1.6 thorpej 96: __cpu_simple_lock_try(__cpu_simple_lock_t *alp)
1.4 thorpej 97: {
98: unsigned long t0, v0;
99:
100: __asm __volatile(
1.5 thorpej 101: "# BEGIN __cpu_simple_lock_try\n"
1.4 thorpej 102: "1: ldl_l %0, %4 \n"
103: " bne %0, 2f \n"
104: " bis $31, %3, %0 \n"
105: " stl_c %0, %2 \n"
106: " beq %0, 3f \n"
107: " mb \n"
108: " bis $31, 1, %1 \n"
109: " br 4f \n"
110: "2: bis $31, $31, %1 \n"
111: " br 4f \n"
112: "3: br 1b \n"
113: "4: \n"
1.5 thorpej 114: " # END __cpu_simple_lock_try"
115: : "=r" (t0), "=r" (v0), "=m" (*alp)
116: : "i" (__SIMPLELOCK_LOCKED), "2" (*alp));
1.4 thorpej 117:
1.7 simonb 118: return (v0 != 0);
1.4 thorpej 119: }
120:
121: static __inline void
1.6 thorpej 122: __cpu_simple_unlock(__cpu_simple_lock_t *alp)
1.4 thorpej 123: {
124:
125: __asm __volatile(
1.5 thorpej 126: "# BEGIN __cpu_simple_unlock\n"
1.9 thorpej 127: " mb \n"
1.4 thorpej 128: " stl $31, %0 \n"
1.5 thorpej 129: " # END __cpu_simple_unlock"
130: : "=m" (*alp));
1.4 thorpej 131: }
1.11 thorpej 132:
1.12 ! thorpej 133: #if defined(MULTIPROCESSOR)
1.11 thorpej 134: /*
135: * On the Alpha, interprocessor interrupts come in at device priority
136: * level. This can cause some problems while waiting for r/w spinlocks
137: * from a high'ish priority level: IPIs that come in will not be processed.
138: * This can lead to deadlock.
139: *
140: * This hook allows IPIs to be processed when a spinlock's interlock
141: * is released.
142: */
143: #define SPINLOCK_INTERLOCK_RELEASE_HOOK \
144: do { \
145: struct cpu_info *__ci = curcpu(); \
146: \
147: if (__ci->ci_ipis != 0) \
148: alpha_ipi_process(__ci); \
149: } while (0)
1.12 ! thorpej 150: #endif /* MULTIPROCESSOR */
1.4 thorpej 151:
152: #endif /* _ALPHA_LOCK_H_ */
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