CVS log for src/sys/arch/alpha/include/alpha_cpu.h

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Default branch: MAIN

Make alpha_wmb() actually a WMB rather than an MB (all uses of
alpha_wmb() have been audited and fixed-up as necessary).

In order to prevent _mcount() from being recursively called when built with COPTS=-O0,
sprinkle `__always_inline' to make _mcount() be generated as a single function.

Sync w/ HEAD.

sync with head

Define the arithmetic exception summary bits passed in a0 to entArith.

Fix the bit position for the PMI bit in ALPHA_AMASK_BITS.

Add alpha_pal_wtint(), which invokes the WTINT PALcode call.

- Document all of the various interrupt levels in the Processor Stataus
  register, and provide symbolic names for them as well.
- Use ALPHA_PSL_IPL_* values directly for IPL_*.

sync with head

merge to -current.

Do a minor cleanup of alpha (this will make applying pullups post branching
easier).
u_int{8,16,32,64}_t -> uint{*}_t
Change all old-style definitions to C89 prototypes.
Whitespace cleanup.
Constification in db_disasm.c

sync with head

Sync with HEAD (-D20101022).

sync with head

Enable Pchip and Cchip error interrupts (machine checks) on DEC 6600
systems. Add some basic pretty-printing for those errors. Tested on
a DS20.

sync with head

sync with head.

Sync with head.

sync with head.

Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

Added a new AMASK bit (ALPHA_AMASK_PMI) and a new IMPLVER family ID:
ALPHA_IMPLVER_EV7.

ok christos@

Merge the nathanw_sa branch.

Add alpha_pal_rdunique() and alpha_pal_wrunique().

Sync kqueue branch with -current.

Catch up to -current.

Add a memory clobber to alpha_pal_swapctx() and alpha_pal_swpipl();
the former affects the address space, and the latter can let interrupt
handlers in to clobber memory.

update to -current

file alpha_cpu.h was added on branch nathanw_sa on 2002-01-08 00:22:54 +0000

Protect userland from the inlines and kernel variable decls.

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Sync w/ netbsd-1-5-base.

And more ANSI'ification!

ANSI'ify.

Fix a typo in a previous revision, and add bit names for amask bits for
use with bitmask_snprintf().

Update the amask bits.

Use ANSI-style function declarations for the various inline functions
here.  Addresses port-alpha/9056.

Pull up to last week's -current.

Inline most of the remaining PALcode calls.

Inline the BWX instructions.

Move atomic operations into <machine/atomic.h>, and make them in-line
assembly, rather than function calls.

...except alpha_atomic_testset_l(), which will go away completely once
I commit the new <machine/lock.h>.

After reading the GCC `documentation' a little more, improve the inline
__asm() statements added previously for PALcode operations.

Inline several things from pal.s:
- alpha_rpcc(), alpha_mb(), alpha_wmb() -- these are instructions, and
  we win by inlining them: rpcc is generally used for profiling, and
  the memory barriers really should execute as quickly as possible with
  minimal side-effects (like additional loads/stores required to call the
  functions!)
- alpha_pal_imb(), alpha_pal_rdps(), alpha_pal_swpipl(), alpha_pal_tbi(),
  alpha_pal_whami() -- these are PALcode ops.  We must specify some register
  clobbers for these.

We have a very decent size savings as a result.  My test system:
text    data    bss     dec     hex     filename
2671724 235848  377016  3284588 321e6c  /netbsd.bak
2617708 235736  377016  3230460 314afc  /netbsd

Most of this comes from fewer register saves/restores around spl*() calls
(now that alpha_pal_rdps() and alpha_pal_swpipl() are inlined).

Note that alpha_pal_rdps() and alpha_pal_swpipl() remain in pal.s to
maintain binary compatibility with LKMs that may use spl*() functions.

Implement atomic addition and subtraction on quadwords.

Implement atomic quadword load-and-latch.

The processor unique value in the PCB is used as a backup kernel stack
pointer when booting secondary CPUs.  Add an alias for it.

Implement atomic test-and-set for longwords (32-bit).

"Gee, there was already a function to do that."

Implement a function to recompute the HWRPB checksum.

Implement quadword atomic test-and-set.

Add definitions for the maximum allowable `whami' procssor ID and the
maximum number of processors we'll allow (64, assuming procssor IDs start
at 0).

vm_offset_t -> {paddr_t,vaddr_t}, vm_size_t -> vsize_t

stale beer- place structure in right file

Define a shorthand macro that represents the mask of PTE bits that the
PALcode cares about.

Cosmetic change.

Add machine check type definitions. Structure the expected/received
machine check items.

Implement a set of `atomic' (using load-locked and store-conditional)
operations.  Initial set includes:

alpha_atomic_setbits_q()	set bits in a quad
alpha_atomic_clearbits_q()	clear bits in a quad

Implement alpha_pal_swpctx().

Rewrite the way the platform model string is determined:
- Attempt to find the model string in the HWRPB's DSR area.  Failing that
  (if the HWRPB version is too old)...
- Look up the system variation in a variation/string table.  Failing that
  (unknown variation)...
- Create a default model string using the variation number.

Also, factor out a bunch of common code.

Update marc-pcmcia branch from trunk.

Add some defines for alpha interrupt types.

Prototype alpha_implver(), and fix a think-o in a previous commit.

Add stubs for the Alpha Byte/Word Extension (BWX) instructions, present
on EV56 and later processors that have the "amask BWX" bit clear.  These
instructions will be used to implement non-swizzle bus access functions
on newer systems, such as the new AlphaStation 500s with EV56 and 21172
PCI chipsets.

See "Alpha Architecture Handbook, Version 3", DEC order number EC-QD2KB-TE.

- Define bits used in the "amask" instruction.
- Define processor family IDs returned by the "implver" instruction.
- Prototype alpha_amask().

Update marc-pcmcia branch from trunk.

Add a few more PALcode operations, as documented in pages (II-B) 2-1 through
(II-B) 2-33 of the Alpha AXP Architecture Reference Manual, Second Edition:

* rdps - Read Processor Status, needed by spl* functions.
* cflush - Cache Flush
* rdval - Read System Value
* wripir - Write Interprocessor Interrupt Request
* wrval - Write System Value

cflush, rdval, wripir, and wrval are used in multi-processor environments.

file alpha_cpu.h was added on branch bouyer-scsipi on 1997-09-03 23:09:06 +0000

Add a few more PALcode operations, as documented in pages (II-B) 2-1 through
(II-B) 2-33 of the Alpha AXP Architecture Reference Manual, Second Edition:

* rdps - Read Processor Status, needed by spl* functions.
* cflush - Cache Flush
* rdval - Read System Value
* wripir - Write Interprocessor Interrupt Request
* wrval - Write System Value

cflush, rdval, wripir, and wrval are used in multi-processor environments.

Fix a typo: ALPHA_PTE_WRITE needs to include the "user write" bit.

Repair marc-pcmcia branch.

sync with -current as of August 11, 1997

sync nwscons with trunk

sync the nwscons branch up with yesterday's version of the trunk.
Lots of conflicts/changes because of the RCS Id format changes.
Also, a few cleanups and corrections.

comment out text after #endif.  "Pasto!"  pointed out by Kevin Sullivan
in PR 3529.

clean up NetBSD RCS ID strings

make ALPHA_K0SEG_TO_PHYS and ~0xfffffc00000000000 with the address,
rather than and-ing 16G-1.  That just strips the k0seg bits, rather
than making the false assumption that the physical address is going
to be in the lower 16G.  That doesn't apply for CIA device-space
addresses, for instance.

K0SEG_END is inclusive

rename translation buffer invalidation macros to start with ALPHA_,
like all other macros defined in alpha_cpu.h.

(1)     Remove old trap definitions, define trap and interrupt handling
more naturally in terms of way the OSF/1 PALcode delivers traps and
interrupts.  Clean up fault/exception handling code and system entry
points.  Seperate ASTs into a seperate C function.
(2)     Restructure and improve machine check and correctable error
handling based on information in the 2nd Ed. of the Alpha Architecture
Reference Manual.
(3)     Removed unused (and not likely useful) PALcode assembly stubs.

Instead of treating the trap/syscall/exception frame like a struct
containing a substruct (the hardware frame) and an array of registers,
treat it like one big array of registers, for easier and prettier
access.  Update everything to deal with that.

Add definitions for:
	Process Control Block
	Interrupt/Exception/Syscall Stack Frame
	Machine Check Error Summary Register
	Machine Check Logout Area
clean up some, and add prototypes for all of the CPU instruction and
PALcode function stubs.

definitions and constants which are part of the Alpha AXP
Architecture, and which relate to the OSF/1 PALcode.