CVS log for src/sys/arch/alpha/alpha/locore.s

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Default branch: MAIN

Pull up following revision(s) (requested by riastradh in ticket #264):

        sys/arch/alpha/include/asm.h: revision 1.45 (patch)
        (also applied to locore.s and multiproc.s)

alpha: Add missing barriers in cpu_switchto.
Details in comments.
(accidently missed in original commit for ticket #264)

Pull up following revision(s) (requested by riastradh in ticket #1859):

	sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
	sys/arch/aarch64/aarch64/locore.S: revision 1.91
	sys/arch/mips/include/asm.h: revision 1.74
	sys/arch/hppa/include/cpu.h: revision 1.13
	sys/arch/arm/arm/armv6_start.S: revision 1.38
	 (applied also to sys/arch/arm/cortex/a9_mpsubr.S,
	 sys/arch/arm/cortex/a9_mpsubr.S,
	 sys/arch/arm/cortex/cortex_init.S)
	sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
	sys/arch/mips/mips/locore.S: revision 1.229
	sys/arch/alpha/include/asm.h: revision 1.45
	 (applied to sys/arch/alpha/alpha/multiproc.s)
	sys/arch/sparc64/sparc64/locore.s: revision 1.432
	sys/arch/vax/vax/subr.S: revision 1.42
	sys/arch/mips/mips/locore_mips3.S: revision 1.116
	sys/arch/ia64/ia64/machdep.c: revision 1.44
	sys/arch/arm/arm32/cpuswitch.S: revision 1.106
	sys/arch/sparc/sparc/locore.s: revision 1.284
	(all via patch)

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.

fix some typos and grammar in comments.

Fix a couple of nits with savectx():
- Note that this function is only used by dumpsys().
- Don't safe the PS word; there isn't actually a spot for it in the PCB.
- Don't bother returning anything; savectx() is declared void.

Sync with HEAD.

It's unlikely that a process will be using restartable atomic sequences
on Alpha, and furthermore it's unlikely that any given context switch
will be returning to one even if the process has them.  So, re-arrange
the RAS processing in cpu_switchto() so that the most likely code paths
are predicted by the branch predictor.  On an EV4-class processor, this
will save ~4-6 cycles on just about every context switch.

Pull in pmap_subr.s (missed in prior commit).

Provide a BWX version of alpha_copystr() and patch it into place if
the system supports the BWX extension.  The inner loop of the BWX
version is 42% shorter than the non-BWX version (7 vs 12 insns).

Re-arrange alpha_copystr() so that the the error/unlikely cases are forward
branches (which will be predicted as not-taken), and that the likely cases
are fall-through, with the exception of the loop branch (which is a backward
branch, and thus will be predicted as taken).

Sync w/ HEAD.

sync with head

Fix an error introduced in rev 1.130 where the previous pcb_onfault
handler was not restored properly in the kcopyerr case.  Also add a
comment explaining why it's save for these routines to be wrappers
around memcpy().

Fixes port-alpha/56197.

- The Alpha fast-soft-intrs implementation supports 2 soft interrupt levels,
  so in exception_return() ensure we clear ineligible-at-new-IPL softint
  bits from the SSIR, otherwise we could loop forever in the following
  scenario:

	processing softnet -> clock interrupt -> schedule softclock

- If the softint thread blocks, it's possible to bounce back through
  the softint return trampoline at something other than IPL_HIGH.  This
  is not a problem other than it's contrary to what alpha_softint_dispatch()
  expect, so make alpha_softint_return() go to IPL_HIGH before it does
  anything else.

These two fixes make fast-soft-interrupts work on Alpha.

- Give lwp0 the same kernel thread backstop as all of the others get
  in cpu_lwp_fork().
- Add a bunch of comments to lwp_trampoline() to explain what's going on.
- In alpha_softint_switchto() tweak how we save the RA in the stack frame.

Reduce the __HAVE_FAST_SOFTINTS #ifdef perimeter.

Implement fast soft interrupts for Alpha.  It's not yet enabled, because
there is a bug lurking that causes problems when user space starts up,
so we'll stick with the slow path for now.

Track the SSIR per-cpu, rather than globally.

- Document all of the various interrupt levels in the Processor Stataus
  register, and provide symbolic names for them as well.
- Use ALPHA_PSL_IPL_* values directly for IPL_*.

Save a few instructions every time we manipulate pcb::pcb_onfault.

- Make the GET_CURLWP actually return curlwp, not &curlwp.
- exception_return(): Use GET_CURLWP directly, rather than a dance
  acount GET_CPUINFO.
- Introduce SET_CURLWP(), to set the curlwp value.
- Garbage-collect GET_FPCURLWP.

Garbage-collect the SWITCH_CONTEXT macro, since it now expands to
just "call_pal PAL_OSF1_swpctx".

The only remaining consumer of curpcb was the PROM mapping code, for if
PROM console routines are being used (only on KN8AE).  We have access to
the sam information via curlwp, so use that, and eliminate the need to set
cpu_info::ci_curpcb when context switching, which saves an extra all into
PALcode.

Clean up all of the _PMAP_MAY_USE_PROM_CONSOLE crapola, centralizing the
logic in prom.c, and rename it _PROM_MAY_USE_PROM_CONSOLE in a few places
it's still needed.

Make copystr() a MI C function, part of libkern and shared on all
architectures.

Notes:

 - On alpha and ia64 the function is kept but gets renamed locally to avoid
   symbol collision. This is because on these two arches, I am not sure
   whether the ASM callers do not rely on fixed registers, so I prefer to
   keep the ASM body for now.
 - On Vax, only the symbol is removed, because the body is used from other
   functions.
 - On RISC-V, this change fixes a bug: copystr() was just a wrapper around
   strlcpy(), but strlcpy() makes the operation less safe (strlen on the
   source beyond its size).
 - The kASan, kCSan and kMSan wrappers are removed, because now that
   copystr() is in C, the compiler transformations are applied to it,
   without the need for manual wrappers.

Could test on amd64 only, but should be fine.

Merge changes from current as of 20200406

Sync with head.

oldlwp is always non-NULL in cpu_switchto so remove the test for NULL.

Sync with HEAD

Overhaul the API used to fetch and store individual memory cells in
userspace.  The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms.  The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).

Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.

Welcome to NetBSD 8.99.37.

sync with head

sync to -current.

Remove COMPAT_SA / KERN_SA.  Welcome to 6.99.3!
Approved by core@.

Catchup with rmind-uvmplock merge.

sync with head

Switch alpha to use PCU to manage the FPU.
Tested by mhitch and review by rmind.

sync with head

Sync with HEAD.

sync with head.

implement ucas_* for alpha.

Sync with HEAD.

sync to netbsd-5

sync with head

s/cpu_fork/cpu_lwp_fork/ in comment.

Rename L_ADDR to L_PCB and amend some comments accordingly.

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places.  Reduce sys/user.h inclusions.

Fix error in previous that could cause us to refer to the wrong cpu_info
after handling an AST.

Restructure exception_return() a bit in preparation for some upcoming
changes.

sync with head

Pull up following revision(s) (requested by martin in ticket #798):
	sys/arch/alpha/alpha/locore.s: revision 1.114
	sys/arch/alpha/alpha/vm_machdep.c: revision 1.100
	sys/arch/alpha/include/alpha.h: revision 1.24
Do not use lwp_trampoline for cpu_setfunc, but a simplified setfunc_trampoline
that does not call lwp_startup() instead.

Pull up following revision(s) (requested by martin in ticket #798):
	sys/arch/alpha/alpha/locore.s: revision 1.114
	sys/arch/alpha/alpha/vm_machdep.c: revision 1.100
	sys/arch/alpha/include/alpha.h: revision 1.24
Do not use lwp_trampoline for cpu_setfunc, but a simplified setfunc_trampoline
that does not call lwp_startup() instead.

Do not use lwp_trampoline for cpu_setfunc, but a simplified setfunc_trampoline
that does not call lwp_startup() instead.

Sync with HEAD.

sync with head.

sync with head.

Remove clause 3 and 4 from TNF licenses

sync with HEAD

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

sync with head.

Sync with head.

Sync with head.

Update to HEAD.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

update some comments.
XXX now pmap_activate is never called with sched_mutex held.
XXX what to do for PMAP_NO_LAZY_LEV1MAP?

cpu_switchto:
- update curlwp.
- don't bother to clear ci_want_resched.

adapt alpha.

Sync with HEAD.

Apply fix for boolean_t -> bool changes on uvm.page_idle_zero access.

Thanks Tobias Nygren for help, ok'ed by thorpej, and tested on
1000A by Aaron J. Grier and on PC164 and 3000/300 by me.

sync with head.

Merge newlock2 to head.

For now always call sched_unlock_idle/sched_lock_idle. They will be
removed by yamt's cpu_switchto() changes.

Checkpoint work in progress.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

remove vestigal {,e}intr{names,cnt} symbols now that vmstat doesn't need them.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

as i386 does, propagete errors from uvm_fault() to users of pcb_onfault
via v0 so that eg. read(2) can return more appropriate errors
rather than always EFAULT.

ok'ed by Jason Thorpe.

Remove p_nras from struct proc - use LIST_EMPTY(&p->p_raslist) instead.
Remove p_raslock and rename p_lwplock p_lock (one lock is enough).
Simplify window test when adding a ras and correct test on VM_MAXUSER_ADDRESS.
Avoid unpredictable branch in i386 locore.S
(pad fields left in struct proc to avoid kernel bump)

Siginfo changes for alpha kernel.  Approved by thorpej@netbsd.org.

Merge the nathanw_sa branch.

Merge switch_exit() and switch_lwp_exit().

Rename cpu_preempt() to cpu_switchto(), and make the caller remove the
new process from its run queue before calling cpu_switchto().

While here, make a few cpu_switch() and cpu_switchto() implementations
get the outgoing LWP from the args, rather than looking at the curlwp
variable.

* Fix a bug in the last branch sync: when loading the proc * to check
  for RAS, use ldq, not ldl.  While here, save an instruction by loading
  directly into a0, rather than into s3 and moving to a0 later.
* Reuse the guts of cpu_switch() for cpu_preempt().

Catch up to -current.

sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work

Add support for restartable atomic sequences.  Rearragne the tail
of cpu_switch() slightly so we can reenable interrupts a little
earlier.

sync kqueue branch with HEAD

Catch up to -current.

Don't need upcall trampolines.

catch up with -current.

s/curproc/curlwp/g

When delivering a signal, arrange for the signal handler to be invoked
directly, using the trampoline only for the return path.

catch up with -current on kqueue branch

Catch up to -current.

Make sigcode and proc_trampoline no-profile.

Move call to sched_unlock_idle to later in the context switch to
eliminate a race where another processor could grab the outgoing
process before we were done saving our state into it, with predictable
results.

Bug spotted on i386 by Frank van der Linden <fvdl@wasabisystems.com>.

Allocate proc0 in machine-dependent code (can't specify align(16) in
C code on x86).

Alpha support routines for kernel mutexes.

l_stat is an int now instead of a u_char.  Pointed out by pk in
a commit message.

Adapt to new upcall signature and possible argument copying.

Catch up to -current.

Update the kqueue branch to HEAD.

First cut at LWP and SA support on the alpha.
Doesn't break in ordinary multiuser mode; LWPs and SAs not yet tested.

Correct a comment: The address of the signal handler is passed to the
sigcode trampoline in pv (t12), not a3, and has been since the
beginning of time.

update to -current

file locore.s was added on branch nathanw_sa on 2001-08-30 23:43:40 +0000

Use memcpy() in kcopy(), copyin(), and copyout().  XXX This means we have
to burn 3 insns to swap the arguments.  Need to change the interface to
these routines to match memcpy().

G/C bcopy() from here.  We'll let it be provided by libkern (which is
what provides memcpy()) until bcopy() is exorcised completely.

Catch up to -current.

add missing   #include "opt_kgdb.h"

Add glue for page zero'ing in the idle loop.

o IEEE 754 floating-point completion code.
o Implement the architected FP_C "Floating Point Control Quadword"

Sync with HEAD.

Import and use cpu_info_primary for non-MULTIPROCESSOR.
Hey, it compiles, and it's only -current.

Sync with HEAD

Glue in KGDB.  Needs some more work -- KGDB currently renders
DDB disabled, but it's a start.

Fix a problem with kcopy()/copyin()/copyout() on MP systems
that became apparent when UBC was added: store a pointer to
the process itself, not a pointer to ci->ci_curproc.

This gets us back to where we were before UBC went in: MP
kernels get to single-user mode, and can run processes on
both CPUs, but things go south when we try to come into
multi-user mode.

Clean up soft interrupt related stuff a bit.

g/c transfer_check

Sync with HEAD.

Make ASTs per-process.

Sync with HEAD (for UBC fixes).

Sync with HEAD (for UBC fixes)

Do the md_syscall, __HAVE_MINIMAL_EMUL and __HAVE_SYSCALL_INTERN thangs.

Start cleanup of syscall(), similar to i386 and arm32.  getpid() rate on my
AS200 goes from ~279000/s to ~446000/s.

Sync with HEAD.

split linux signal code off locore.s

Sync with HEAD.

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Delete a block of code that was intended to get the second
CPU to handle interrupts, but prevents a whole slew of things
from working properly on the second CPU.  It is no longer
necessary now that several other bugs have been fixed.

In Idle(), only switch to the idle PCB if we're not already running
on it, and make sure to deactivate the old process's address space,
as this will not otherwise be done by cpu_switch() later once we're
on the idle PCB.

Also, update some comments related to when s0 (i.e. the old process)
is NULL in the context switching code.

Correct conditionalization of last change.

MULTIPROCESSOR: context switch to cpu's idle pcb before unlocking the
scheduler in idle so our stack doesn't get stolen out from underneath us.

Define the biglock perimeter for the Alpha port, and generally clean
up a bunch of the MP code.  Still doens't work properly yet, this is
just a snapshot of work-in-progress.

Add a lock around the scheduler, and use it as necessary, including
in the non-MULTIPROCESSOR case (LOCKDEBUG requires it).  Scheduler
lock is held upon entry to mi_switch() and cpu_switch(), and
cpu_switch() releases the lock before returning.

Largely from Bill Sommerfeld, with some minor bug fixes and
machine-dependent code hacking from me.

In cpu_switch(), load value *after* checking that the base register
is not NULL.

Sync w/ netbsd-1-5-base.

Switch to the new `evcnt' mechanism for counting interrupts.  Maintain
a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.

- Clean up clock interrupt code a bit, and provide a CPU_IS_PRIMARY()
  macro in the MULTIPROCESSOR case (hardclock() wants it).
- Implement __GENERIC_SOFT_INTERRUPTS, and redefine the legacy
  software interrupts in terms of it.  Garbage-collect setsoftserial().

- In the MULTIPROCESSOR case, initialize p_cpu before a process is
  marked SONPROC.
- Always make curproc, fpcurproc, astpending, and want_resched per-CPU
  variables in struct cpu_info.  Restructure code accordingly, and trim
  a few instructions from a few spots in various places in locore.

First sweep at scheduler state cleanup.  Collect MI scheduler
state into global and per-CPU scheduler state:

	- Global state: sched_qs (run queues), sched_whichqs (bitmap
	  of non-empty run queues), sched_slpque (sleep queues).
	  NOTE: These may collectively move into a struct schedstate
	  at some point in the future.

	- Per-CPU state, struct schedstate_percpu: spc_runtime
	  (time process on this CPU started running), spc_flags
	  (replaces struct proc's p_schedflags), and
	  spc_curpriority (usrpri of processes on this CPU).

	- Every platform must now supply a struct cpu_info and
	  a curcpu() macro.  Simplify existing cpu_info declarations
	  where appropriate.

	- All references to per-CPU scheduler state now made through
	  curcpu().  NOTE: this will likely be adjusted in the future
	  after further changes to struct proc are made.

Tested on i386 and Alpha.  Changes are mostly mechanical, but apologies
in advance if it doesn't compile on a particular platform.

Introduce a new process state distinct from SRUN called SONPROC
which indicates that the process is actually running on a
processor.  Test against SONPROC as appropriate rather than
combinations of SRUN and curproc.  Update all context switch code
to properly set SONPROC when the process becomes the current
process on the CPU.

Pull up to last week's -current.

Garbage-collect.

- Remove a misguided attempt to use procs as idle contexts for secondary
  processors.  Instead, allocate separate idle PCBs for them (including
  the primary -- don't use proc0's for its idle context).
- Use SysValue to store the cpu_info for each processor.

Remove now-obsolete atomic operations.

Inline the BWX instructions.

Sync with -current.

in copystr(), be sure to return an error if maxlen == 0.

From Ross Harvey:
- Fix a bug where IPL wasn't being lowered to process SIRs, which
  effectively caused them to be processed at splserial(), and loop
  over the ssir, like we do for astpending.
- Optimize the flow of exception_return().

Fix a race condition in AST processing described by Andrew Gallatin on
the freebsd-alpha mailing list which basically boiled down to increasing
stack depth due to lowering the IPL before checking for an AST.

This changes AST processing to do basically what the i386 port does (as
described by Charles Hannum):

 check_ast:
        if (astpending) {
                lower IPL
                process AST
                raise IPL
                goto check_ast
        }

Centralize the declaration and clearing of `cold'.

Update from trunk.

* Set up a trapframe before calling console_restart(), and just pass it the
  frame instead of a selection from the saved state.
* new macros:   bfalse reg, dst		/* "beq" */
		btrue reg, dst		/* "bne" */

Sync w/ -current.

Convert to traceback-friendly temporary labels.

- Revert previous change to XentIF(), now that we're going to enter the
  debugger differently.
- Pull in debugger glue if DDB is configured.

And one unrelated change, while I was here: Don't create a fake trapframe
for main(); it hasn't been used by main() for quite some time, and panic
if main() returns, because that's not supposed to happen now.

Dispatch to the debugger from the Intruction Fault trap vector directly,
rather than doing it from trap().  This so we can switch to a temporary
stack for the debugger (in a forthcoming commit).

completely remove Mach VM support.  all that is left is the all the
header files as UVM still uses (most of) these.

Enable fuword(9), fuiword(9).

remove ovbcopy references

Now that we have the kthread mechanism, massively clean up the way
additional processors are spun up on multiprocessor Alpha systems.
Now, each processor gets its own idle thread (the primary processor
uses proc0).  This idle thread is used in switch_exit(), rather than
explicitly referencing proc0.

Also, make `curproc', `fpcurproc', and `curpcb' per-cpu values.  This
required some data structure rearrangement; cpu info is now statically
allocated in the BSS, rather than via malloc(), and cpu_softc is gone.
(Modeled somewhat after NetBSD/sparc's multiprocessor info structures.)

Oops, restore pcb_onfault if a fault occures in kcopy().  Pointed out by
Charles Hannum.

Nuke the final holdout of INTRNAMES_DEFINITION.
Do a nice gas.new .rept/.endr loop and also pad each string with spaces
in case a platform actually does want to rewrite the names.

G/C some EVCNT_COUNTERS stuff.

Changes to support fork_kthread():
- cpu_set_kpc() now takes void *arg third argument, passed to the
  entry point.
- cpu_fork() allows parent to be non-curproc iff parent is proc0.
  When forking non-curproc, assume its state has already been saved.
- Adjust various pieces of machine-dependent code to account of all of this.

Add linux signal trampoline code.

In exception_return(), if MULTIPROCESSOR, skip software interrupts, ASTs,
and floating point handling if we're not the primary CPU.

First-cut at code to spin up secondary processors on a multiprocessor
Alpha system, conditional on MULTIPROCESSOR.

NOTE: This does not yet work completely.  The secondary CPU begins the
boot process, but never makes it into the cpu spinup trampoline.  This
is merely a snapshot of a work-in-progress.

Make signal delivery work again.

Adjust for the new "reaper" kernel thread: do not free the vmspace and
u-area in machine-dependent code.  Instead, call exit2() to schedule
the reaper to free them for us, once it is safe to do so (i.e. we are
no longer running on the dead proc's vmspace and stack).

Argh, finish renaming Lev1map to kernel_lev1map.

Implement a set of `atomic' (using load-locked and store-conditional)
operations.  Initial set includes:

alpha_atomic_setbits_q()	set bits in a quad
alpha_atomic_clearbits_q()	clear bits in a quad

- The pmap now includes support for ASNs.  We no longer need to flush
  the TLB and I-cache in the SWITCH_CONTEXT macro.
- Right after switching to proc0's newly-created context at startup time,
  flush the TLB and I-cache; this is the only place where it's not done
  automatically.
- Fix a nasty bug in a critical section of cpu_switch(); change the
  pmap_activate -> SWITCH_CONTEXT -> pmap_deactivate sequence to
  pmap_deactivate -> pmap_activate -> SWITCH_CONTEXT.  This prevents
  erroneously marking a pmap inactive if switching to a process that
  shares it's address space (and thus its pmap) with the oldproc!  Noticed
  by Chris Demetriou.

Nuke swpctxt(); it's only used by the Mach pmap, which we will only ever
use for reference.

Don't call pmap_deactivate() if we jumped into the middle of cpu_switch()
from switch_exit(), since by this time, the vmspace will have already
been deactivated and freed.

Fix think'o in last kcopy() change.

In kcopy(), make sure we save and restore the old fault handler; kcopy()
is called from uiomove(), which may be in the code path of servicing
a non-fatal page fault caused by a copyin() or copyout().

Several changes related to all pmaps having their own level 1
page table:
- Update the current hwpcb pointer in the SWITCH_CONTEXT macro, so that
  we know it's always correct.
- Optimize cpu_switch(): if we're switching to ourselves, skip the
  actual context swap.
- Clean up some comments and remove some code rendered obsolete by
  the fact that address spaces are now selected by switching to a
  new level 1 page table.

Add support for UVM.

clean up the way bootinfo information is passed and used: move the version
number passed by the boot block into a register, change the kernel's
bootinfo handing so that it always uses bootinfo to get bootinfo-ish values
(filling them in if the boot blocks didn't pass them), and make versioning
a small bit more sane.

Sync w/ trunk: ability to traceback past PALcode entry vectors.

--Add handcrafted stack frame directives to locore.s palcode vector
--entries / remove kernel entry from locore / reorganize vector entry
--code. Enables access to stack frames transitively w.r.t. palcode
--vectors, e.g. upward traceback works, inverting (possibly several)
--kernel vectors. Until now, all trackbacks ended at the first-reached
--instance of trap(), which was totally useless as there is no mystery
--to trap->panic->cpu_reboot

Update marc-pcmcia branch from trunk.

Add stubs for the Alpha Byte/Word Extension (BWX) instructions, present
on EV56 and later processors that have the "amask BWX" bit clear.  These
instructions will be used to implement non-swizzle bus access functions
on newer systems, such as the new AlphaStation 500s with EV56 and 21172
PCI chipsets.

See "Alpha Architecture Handbook, Version 3", DEC order number EC-QD2KB-TE.

From page 6-9 of "Alpha AXP Architecture Reference Manual, Second Edition":

	An IMB intruction must be executed after software or I/O devices
	write into the instruction stream or modify the instruction
	stream virtual address mapping, and before the new value is
	fetched as an instruction.

We were missing calls to IMB after mappings were changed, which caused
systems with large I-caches (e.g. my AlphaStation 500) to fail miserably
when mapping in new pages of program text, or when context switching
(I couldn't even get the shell from init!).

Update marc-pcmcia branch from trunk.

Clean up the context switching code a bit:
- Marco-ize the 3 instructions that actually switch to the new process
  context.
- Unify (except for the pmap_deactivate() call) the NEW_PMAP and not-NEW_PMAP
  versions of cpu_switch(), and clean up some comments.
- Tidy up the not-NEW_PMAP bits of switch_exit().

Note that a2 and a3 contain bootinfo information passed from the boot
program to alpha_init().

Nuke the idea of <machine/options.h>.  It completely defeats the purpose
of fine-grain option dependencies.

file locore.s was added on branch bouyer-scsipi on 1997-09-02 13:18:19 +0000

Nuke the idea of <machine/options.h>.  It completely defeats the purpose
of fine-grain option dependencies.

Repair marc-pcmcia branch.

sync with -current as of August 11, 1997

sync the nwscons branch up with yesterday's version of the trunk.
Lots of conflicts/changes because of the RCS Id format changes.
Also, a few cleanups and corrections.

include RCS IDs for assembler files, disabled with NO_KERNEL_RCSIDS

clean up options.h inclusion slightly

include machine/options.h

clean up NetBSD RCS ID strings

clean up a bit, add kernel setjmp and longjmp definitions.

do_sir lowers the IPL itself, now

update for changes in asm.h

add an XentRestart, pointed to by the retore_term HWRPB vector (and maybe,
eventually, the restart HWRPB vector), which calls console_restart.  This
is invoked when the console halt switch is used and the user enters 'c'
at the console prompt, and eventually causes a system crash dump to be
generated.

use assembler directives and labels that make both the ELF- and ECOFF-
targeted assemblers happy.

OLD_PMAP -> NEW_PMAP

do TBIA rather than TBIAP after initial context switch

(1)     Remove old trap definitions, define trap and interrupt handling
more naturally in terms of way the OSF/1 PALcode delivers traps and
interrupts.  Clean up fault/exception handling code and system entry
points.  Seperate ASTs into a seperate C function.
(2)     Clean up interrupt handling slightly.
(3)     Add machinery to make [fs]uswintr be a bit more careful when
determining if a fault was actually their fault.  (Unfortunately, they're
not actually implemented now, anyway.)
(4)     Minor cleanup.

rename rei() to exception_return(). rename proc_trampoline() to
switch_trampoline(). clean up trap/exception/syscall entries and
eliminate common code where appropriate.  clean up bootstrapping
code.

don't save and set the USP at every trap entry and exit.  It's
unnecessary, and given that there's no reason to waste time and
add complexity in trap handlers.  This means that code which sets and
uses the USP has to be a bit more careful, but that doesn't happen much.

Instead of treating the trap/syscall/exception frame like a struct
containing a substruct (the hardware frame) and an array of registers,
treat it like one big array of registers, for easier and prettier
access.  Update everything to deal with that.

update for new alpha_cpu.h definitions, -Wall cleanups, and make
things compile with the new work-in-progress pmap code.

fix a few botched names

clean and update for new defintions, prototypes, etc.

pull up from trunk:
>don't pass "argc," "argv," and "envp" from boot blocks to kernel;
>they're unnecessary and there's no reason to use them.  Have the
>kernel get necessary values from the PROM directly.

don't pass "argc," "argv," and "envp" from boot blocks to kernel;
they're unnecessary and there's no reason to use them.  Have the
kernel get necessary values from the PROM directly.

add 'kernel_text' symbol, for use by kvm_mkdb

clean up copyrights and RCS IDs

add rpcc entry point

Don't define _LOCORE here.

assym.s -> assym.h
(Some ports did this already.)

LOCORE -> _LOCORE

wholesale update from my NetBSD/Alpha source tree.  Includes:
	Support for AXPpci CPUs,
	Support for AlphaStation 600 CPUs,
	new boot block structure, which requires an 'installboot'
	    program and works a lot like the NetBSD/sparc boot blocks.

kill alpha_mb(); it's now inlined.  make copy functions' frame sizes
more easily adjustable.

oops; this got mangled.

sync with my current Alpha sources

remove support for double-mapping the user area and kernel stack.

copy*str() should use size_t.

preliminary Alpha support.  note that NOT ALL OF THE MODIFICATIONS TO
THE REST OF THE KERNEL ARE IN THE TREE YET.  Also, some of this is
_incredibly_ hack-ish, etc., but it works.