![[BACK]](/icons/back.gif){kind=icon}
Up to [cvs.NetBSD.org] / src / sys / arch / aarch64 / include
Request diff between arbitrary revisions
Default branch: MAIN
Revision 1.8 / (download) - annotate - [select for diffs], Wed Aug 12 13:19:35 2020 UTC (2 years, 9 months ago) by skrll
Branch: MAIN
CVS Tags: thorpej-i2c-spi-conf2-base,
thorpej-i2c-spi-conf2,
thorpej-i2c-spi-conf-base,
thorpej-i2c-spi-conf,
thorpej-futex2-base,
thorpej-futex2,
thorpej-futex-base,
thorpej-futex,
thorpej-cfargs2-base,
thorpej-cfargs2,
thorpej-cfargs-base,
thorpej-cfargs,
netbsd-10-base,
netbsd-10,
cjep_sun2x-base1,
cjep_sun2x-base,
cjep_sun2x,
cjep_staticlib_x-base1,
cjep_staticlib_x-base,
cjep_staticlib_x,
bouyer-sunxi-drm-base,
bouyer-sunxi-drm,
HEAD
Changes since 1.7: +2 -1
lines
Diff to previous 1.7 (colored)
Part II of ad's aarch64 performance improvements (cpu_switch.S bugs are all mine) - Use tpidr_el1 to hold curlwp and not curcpu, because curlwp is accessed much more often by MI code. It also makes curlwp preemption safe and allows aarch64_curlwp() to be a const function (curcpu must be volatile). - Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs can see spurious ASTs (which doesn't cause a problem, it just means some time may be wasted). - Use plain stores to set/clear ASTs. Make sure ASTs are always set on the same CPU as the target LWP, and delivered via IPI if posted from a remote CPU so that they are resolved quickly. - Add some cache line padding to struct cpu_info, to match x86. - Add a memory barrier in a couple of places where ci_curlwp is set. This is needed whenever an LWP that is resuming on the CPU could hold an adaptive mutex. The barrier needs to drain the CPU's store buffer, so that the update to ci_curlwp becomes globally visible before the LWP can resume and call mutex_exit(). By my reading of the ARM docs it looks like the instruction I used will do the right thing, but I'm not 100% sure.
Revision 1.7 / (download) - annotate - [select for diffs], Sat May 23 18:08:59 2020 UTC (3 years ago) by ryo
Branch: MAIN
Changes since 1.6: +7 -6
lines
Diff to previous 1.6 (colored)
Not only the kernel thread, but also the userland PAC keys (APIA,APIB,APDA,APDB,APGA) are now randomly initialized at exec, and switched when context switch. userland programs are able to perform pointer authentication on ARMv8.3+PAC cpu. reviewd by maxv@, thanks.
Revision 1.2.2.3 / (download) - annotate - [select for diffs], Tue Apr 21 18:42:02 2020 UTC (3 years, 1 month ago) by martin
Branch: phil-wifi
Changes since 1.2.2.2: +6 -0
lines
Diff to previous 1.2.2.2 (colored) to branchpoint 1.2 (colored) next main 1.3 (colored)
Sync with HEAD
Revision 1.5.6.1 / (download) - annotate - [select for diffs], Mon Apr 20 11:28:51 2020 UTC (3 years, 1 month ago) by bouyer
Branch: bouyer-xenpvh
Changes since 1.5: +7 -1
lines
Diff to previous 1.5 (colored) next main 1.6 (colored)
Sync with HEAD
Revision 1.6 / (download) - annotate - [select for diffs], Sun Apr 12 07:49:58 2020 UTC (3 years, 1 month ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20200421,
bouyer-xenpvh-base2,
bouyer-xenpvh-base1
Changes since 1.5: +7 -1
lines
Diff to previous 1.5 (colored)
Add support for Pointer Authentication (PAC). We use the "pac-ret" option, to sign the return instruction pointer on function entry, and authenticate it on function exit. This acts as a mitigation against ROP. The authentication uses a per-lwp (secret) I-A key stored in the 128bit APIAKey register and part of the lwp context. During lwp creation, the kernel generates a random key, and during context switches, it installs the key of the target lwp on the CPU. Userland cannot read the APIAKey register directly. However, it can sign its pointers with it, because the register is architecturally shared between userland and the kernel. Although part of the CPU design, it is a bit of an undesired behavior, because it allows to forge valid kernel pointers from userland. To avoid that, we don't share the key with userland, and rather switch it in EL0<->EL1 transitions. This means that when userland executes, a different key is loaded in APIAKey than the one the kernel uses. For now the userland key is a fixed 128bit zero value. The DDB stack unwinder is changed to strip the authentication code from the pointers in lr. Two problems are known: * Currently the idlelwps' keys are not really secret. This is because the RNG is not yet available when we spawn these lwps. Not overly important, but would be nice to fix with UEFI RNG. * The key switching in EL0<->EL1 transitions is not the most optimized code on the planet. Instead of checking aarch64_pac_enabled, it would be better to hot-patch the code at boot time, but there currently is no hot-patch support on aarch64. Tested on Qemu.
Revision 1.2.2.2 / (download) - annotate - [select for diffs], Wed Apr 8 14:07:24 2020 UTC (3 years, 1 month ago) by martin
Branch: phil-wifi
Changes since 1.2.2.1: +10 -1
lines
Diff to previous 1.2.2.1 (colored) to branchpoint 1.2 (colored)
Merge changes from current as of 20200406
Revision 1.5 / (download) - annotate - [select for diffs], Sun Nov 24 11:28:40 2019 UTC (3 years, 6 months ago) by rin
Branch: MAIN
CVS Tags: phil-wifi-20200411,
phil-wifi-20200406,
is-mlppp-base,
is-mlppp,
bouyer-xenpvh-base,
ad-namecache-base3,
ad-namecache-base2,
ad-namecache-base1,
ad-namecache-base,
ad-namecache
Branch point for: bouyer-xenpvh
Changes since 1.4: +1 -3
lines
Diff to previous 1.4 (colored)
part of PR port-arm/54702 Having md_march32 unconditionally in struct mdproc, in order to make libkvm happy. XXX pullup to netbsd-9
Revision 1.4 / (download) - annotate - [select for diffs], Sun Nov 24 04:08:36 2019 UTC (3 years, 6 months ago) by rin
Branch: MAIN
Changes since 1.3: +12 -1
lines
Diff to previous 1.3 (colored)
PR port-arm/54702 Add support for earmv6hf binaries on COMPAT_NETBSD32 for aarch64: - Emulate ARMv6 instructions with cache operations register (c7), that are deprecated since ARMv7, and disabled on ARMv8 with LP64 kernel. - ep_machine_arch (default: earmv7hf) is copied from executables, as we do for mips64. "uname -p" reports earmv6hf if compiled for earmv6hf; configure scripts etc can determine the appropriate architecture. Many thanks to ryo@ for helping me to add support of Thumb-mode, as well as providing exhaustive test cases: https://github.com/ryo/mcr_test/ We've confirmed: - Emulation works in Thumb-mode. - T32 16-bit length illegal instruction results in SIGILL, even if it is located nearby a boundary b/w mapped and unmapped pages. - T32 32-bit instruction results in SIGSEGV if it is located across a boundary b/w mapped and unmapped pages. XXX pullup to netbsd-9
Revision 1.2.2.1 / (download) - annotate - [select for diffs], Mon Jun 10 22:05:43 2019 UTC (3 years, 11 months ago) by christos
Branch: phil-wifi
Changes since 1.2: +1 -2
lines
Diff to previous 1.2 (colored)
Sync with HEAD
Revision 1.1.28.2 / (download) - annotate - [select for diffs], Fri Jan 18 08:50:13 2019 UTC (4 years, 4 months ago) by pgoyette
Branch: pgoyette-compat
CVS Tags: pgoyette-compat-merge-20190127
Changes since 1.1.28.1: +1 -2
lines
Diff to previous 1.1.28.1 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored)
Synch with HEAD
Revision 1.3 / (download) - annotate - [select for diffs], Thu Dec 27 09:55:27 2018 UTC (4 years, 5 months ago) by mrg
Branch: MAIN
CVS Tags: phil-wifi-20191119,
phil-wifi-20190609,
pgoyette-compat-20190127,
pgoyette-compat-20190118,
netbsd-9-base,
netbsd-9-3-RELEASE,
netbsd-9-2-RELEASE,
netbsd-9-1-RELEASE,
netbsd-9-0-RELEASE,
netbsd-9-0-RC2,
netbsd-9-0-RC1,
netbsd-9,
isaki-audio2-base,
isaki-audio2
Changes since 1.2: +1 -2
lines
Diff to previous 1.2 (colored)
make savecore for arm64 basically work. - move MD lwp "md_ktf" member into struct pcb. the pcb is used by the gdb "bsd-kvm" target code to find the stack of each thread and needs to be available in a well known location. - implement aarch64_nbsd_supply_pcb() in GDB. makes basic gdb work on a crash dump. - remove '#if L_MD_KTF + 8 == L_MD_CPACR' conditional code, as there is no more L_MD_KTF. with this gdb has minimal working functionality with "target kvm", and crash can at least "ps" on a crash dump. ok skrll.
Revision 1.1.28.1 / (download) - annotate - [select for diffs], Sat Apr 7 04:12:11 2018 UTC (5 years, 1 month ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1: +2 -2
lines
Diff to previous 1.1 (colored)
Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
Revision 1.2 / (download) - annotate - [select for diffs], Sun Apr 1 04:35:03 2018 UTC (5 years, 1 month ago) by ryo
Branch: MAIN
CVS Tags: phil-wifi-base,
pgoyette-compat-1226,
pgoyette-compat-1126,
pgoyette-compat-1020,
pgoyette-compat-0930,
pgoyette-compat-0906,
pgoyette-compat-0728,
pgoyette-compat-0625,
pgoyette-compat-0521,
pgoyette-compat-0502,
pgoyette-compat-0422,
pgoyette-compat-0415,
pgoyette-compat-0407
Branch point for: phil-wifi
Changes since 1.1: +2 -2
lines
Diff to previous 1.1 (colored)
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@) - sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@) - add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
Revision 1.1.4.2 / (download) - annotate - [select for diffs], Wed Aug 20 00:02:39 2014 UTC (8 years, 9 months ago) by tls
Branch: tls-maxphys
Changes since 1.1.4.1: +55 -0
lines
Diff to previous 1.1.4.1 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored)
Rebase to HEAD as of a few days ago.
Revision 1.1.4.1, Sun Aug 10 05:47:38 2014 UTC (8 years, 9 months ago) by tls
Branch: tls-maxphys
Changes since 1.1: +0 -55
lines
FILE REMOVED
file proc.h was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000
Revision 1.1 / (download) - annotate - [select for diffs], Sun Aug 10 05:47:38 2014 UTC (8 years, 9 months ago) by matt
Branch: MAIN
CVS Tags: tls-maxphys-base-20171202,
tls-maxphys-base,
prg-localcount2-base3,
prg-localcount2-base2,
prg-localcount2-base1,
prg-localcount2-base,
prg-localcount2,
pgoyette-localcount-base,
pgoyette-localcount-20170426,
pgoyette-localcount-20170320,
pgoyette-localcount-20170107,
pgoyette-localcount-20161104,
pgoyette-localcount-20160806,
pgoyette-localcount-20160726,
pgoyette-localcount,
pgoyette-compat-base,
pgoyette-compat-0330,
pgoyette-compat-0322,
pgoyette-compat-0315,
perseant-stdc-iso10646-base,
perseant-stdc-iso10646,
nick-nhusb-base-20170825,
nick-nhusb-base-20170204,
nick-nhusb-base-20161204,
nick-nhusb-base-20161004,
nick-nhusb-base-20160907,
nick-nhusb-base-20160529,
nick-nhusb-base-20160422,
nick-nhusb-base-20160319,
nick-nhusb-base-20151226,
nick-nhusb-base-20150921,
nick-nhusb-base-20150606,
nick-nhusb-base-20150406,
nick-nhusb-base,
nick-nhusb,
netbsd-8-base,
netbsd-8-2-RELEASE,
netbsd-8-1-RELEASE,
netbsd-8-1-RC1,
netbsd-8-0-RELEASE,
netbsd-8-0-RC2,
netbsd-8-0-RC1,
netbsd-8,
netbsd-7-nhusb-base-20170116,
netbsd-7-nhusb-base,
netbsd-7-nhusb,
netbsd-7-base,
netbsd-7-2-RELEASE,
netbsd-7-1-RELEASE,
netbsd-7-1-RC2,
netbsd-7-1-RC1,
netbsd-7-1-2-RELEASE,
netbsd-7-1-1-RELEASE,
netbsd-7-1,
netbsd-7-0-RELEASE,
netbsd-7-0-RC3,
netbsd-7-0-RC2,
netbsd-7-0-RC1,
netbsd-7-0-2-RELEASE,
netbsd-7-0-1-RELEASE,
netbsd-7-0,
netbsd-7,
matt-nb8-mediatek-base,
matt-nb8-mediatek,
localcount-20160914,
jdolecek-ncq-base,
jdolecek-ncq,
bouyer-socketcan-base1,
bouyer-socketcan-base,
bouyer-socketcan
Branch point for: tls-maxphys,
pgoyette-compat
Preliminary files for AARCH64 (64-bit ARM) support. Enough for a distribution build.