CVS log for src/sys/arch/aarch64/include/locore.h

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Default branch: MAIN

Sync with HEAD.

Add DISABLE_INTERRUPT_SAVE(), like DISABLE_INTERRUPT() but also returns
the previous state.

Use DISABLE_INTERRUPT_SAVE()/ENABLE_INTERRUPT() in pic_splfuncs instead
of cpsid()/cpsie(). The difference here is the caller no longer specifies
which bits to disable and enable; on arm32 we continue to use I32_bit and
on aarch64 we now consistently toggle both IRQ and FIQ state.

daif_disable: since we read bits before setting them, if the current state
matches the desired state we can skip the daif write

Use reg_daif{set,clr}_write directly instead of daif_{en,dis}able for
ENABLE_INTERRUPT() and DISABLE_INTERRUPT() macros, to avoid an unnecessary
reg_daif_read().

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Sync with HEAD

Sync with HEAD

Include aarch64/machdep.h for arm32 compat.

add MULTIPROCESSOR support

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

update from HEAD

Sync with HEAD

Sync with HEAD

Sync with HEAD

allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

Rebase to HEAD as of a few days ago.

file locore.h was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000

Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.