Annotation of src/sys/arch/aarch64/include/armreg.h, Revision 1.63
1.63 ! ryo 1: /* $NetBSD: armreg.h,v 1.62 2022/12/01 00:29:10 ryo Exp $ */
1.1 matt 2:
3: /*-
4: * Copyright (c) 2014 The NetBSD Foundation, Inc.
5: * All rights reserved.
6: *
7: * This code is derived from software contributed to The NetBSD Foundation
8: * by Matt Thomas of 3am Software Foundry.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: *
19: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29: * POSSIBILITY OF SUCH DAMAGE.
30: */
31:
32: #ifndef _AARCH64_ARMREG_H_
33: #define _AARCH64_ARMREG_H_
34:
1.8 ryo 35: #include <arm/cputypes.h>
1.1 matt 36: #include <sys/types.h>
37:
1.42 ryo 38: #ifdef __clang__
39: #define ATTR_ARCH(arch) ".arch " arch ";"
40: #define ATTR_TARGET_ARCH(x)
41: #define ASM_ARCH(x) x
42: #else
43: #define ATTR_ARCH(arch) __attribute__((target("arch=" arch)))
44: #define ATTR_TARGET_ARCH(x) x
45: #define ASM_ARCH(x)
46: #endif
47:
48: #define AARCH64REG_READ_INLINE3(regname, regdesc, arch) \
49: static __inline uint64_t ATTR_TARGET_ARCH(arch) \
1.7 skrll 50: reg_##regname##_read(void) \
51: { \
52: uint64_t __rv; \
1.42 ryo 53: __asm __volatile( \
54: ASM_ARCH(arch) \
55: "mrs %0, " #regdesc : "=r"(__rv) \
56: ); \
1.7 skrll 57: return __rv; \
1.1 matt 58: }
59:
1.33 maxv 60: #define AARCH64REG_READ_INLINE2(regname, regdesc) \
61: AARCH64REG_READ_INLINE3(regname, regdesc, )
62:
1.42 ryo 63: #define AARCH64REG_WRITE_INLINE3(regname, regdesc, arch) \
64: static __inline void ATTR_TARGET_ARCH(arch) \
1.7 skrll 65: reg_##regname##_write(uint64_t __val) \
66: { \
1.42 ryo 67: __asm __volatile( \
68: ASM_ARCH(arch) \
1.51 maxv 69: "msr " #regdesc ", %0" :: "r"(__val) : "memory" \
1.42 ryo 70: ); \
1.1 matt 71: }
72:
1.33 maxv 73: #define AARCH64REG_WRITE_INLINE2(regname, regdesc) \
74: AARCH64REG_WRITE_INLINE3(regname, regdesc, )
75:
1.7 skrll 76: #define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc) \
1.59 ryo 77: static __inline void __always_inline \
78: reg_##regname##_write(const uint64_t __val) \
1.7 skrll 79: { \
1.51 maxv 80: __asm __volatile( \
81: "msr " #regdesc ", %0" :: "n"(__val) : "memory" \
82: ); \
1.1 matt 83: }
84:
1.7 skrll 85: #define AARCH64REG_READ_INLINE(regname) \
1.1 matt 86: AARCH64REG_READ_INLINE2(regname, regname)
87:
1.7 skrll 88: #define AARCH64REG_WRITE_INLINE(regname) \
1.1 matt 89: AARCH64REG_WRITE_INLINE2(regname, regname)
90:
1.7 skrll 91: #define AARCH64REG_WRITEIMM_INLINE(regname) \
1.1 matt 92: AARCH64REG_WRITEIMM_INLINE2(regname, regname)
1.15 jmcneill 93:
94: #define AARCH64REG_READWRITE_INLINE2(regname, regdesc) \
95: AARCH64REG_READ_INLINE2(regname, regdesc) \
96: AARCH64REG_WRITE_INLINE2(regname, regdesc)
97:
1.24 ryo 98: #define AARCH64REG_ATWRITE_INLINE2(regname, regdesc) \
99: static __inline void \
100: reg_##regname##_write(uint64_t __val) \
101: { \
1.51 maxv 102: __asm __volatile( \
103: "at " #regdesc ", %0" :: "r"(__val) : "memory" \
104: ); \
1.24 ryo 105: }
106:
107: #define AARCH64REG_ATWRITE_INLINE(regname) \
108: AARCH64REG_ATWRITE_INLINE2(regname, regname)
109:
1.1 matt 110: /*
111: * System registers available at EL0 (user)
112: */
113: AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register
114:
1.48 skrll 115: #define CTR_EL0_TMIN_LINE __BITS(37,32) // Tag MIN LINE size
116: #define CTR_EL0_DIC __BIT(29) // Instruction cache requirement
117: #define CTR_EL0_IDC __BIT(28) // Data Cache clean requirement
1.13 skrll 118: #define CTR_EL0_CWG_LINE __BITS(27,24) // Cacheback Writeback Granule
119: #define CTR_EL0_ERG_LINE __BITS(23,20) // Exclusives Reservation Granule
120: #define CTR_EL0_DMIN_LINE __BITS(19,16) // Dcache MIN LINE size (log2 - 2)
1.12 christos 121: #define CTR_EL0_L1IP_MASK __BITS(15,14)
1.37 ryo 122: #define CTR_EL0_L1IP_VPIPT 0 // VMID-aware Physical Index, Physical Tag
1.13 skrll 123: #define CTR_EL0_L1IP_AIVIVT 1 // ASID-tagged Virtual Index, Virtual Tag
124: #define CTR_EL0_L1IP_VIPT 2 // Virtual Index, Physical Tag
125: #define CTR_EL0_L1IP_PIPT 3 // Physical Index, Physical Tag
126: #define CTR_EL0_IMIN_LINE __BITS(3,0) // Icache MIN LINE size (log2 - 2)
1.1 matt 127:
1.14 skrll 128: AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register
1.1 matt 129:
1.13 skrll 130: #define DCZID_DZP __BIT(4) // Data Zero Prohibited
131: #define DCZID_BS __BITS(3,0) // Block Size (log2 - 2)
1.1 matt 132:
1.14 skrll 133: AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register
1.1 matt 134: AARCH64REG_WRITE_INLINE(fpcr)
135:
1.13 skrll 136: #define FPCR_AHP __BIT(26) // Alternative Half Precision
137: #define FPCR_DN __BIT(25) // Default Nan Control
138: #define FPCR_FZ __BIT(24) // Flush-To-Zero
139: #define FPCR_RMODE __BITS(23,22) // Rounding Mode
140: #define FPCR_RN 0 // Round Nearest
141: #define FPCR_RP 1 // Round towards Plus infinity
142: #define FPCR_RM 2 // Round towards Minus infinity
143: #define FPCR_RZ 3 // Round towards Zero
144: #define FPCR_STRIDE __BITS(21,20)
1.20 riastrad 145: #define FPCR_FZ16 __BIT(19) // Flush-To-Zero for FP16
1.13 skrll 146: #define FPCR_LEN __BITS(18,16)
147: #define FPCR_IDE __BIT(15) // Input Denormal Exception enable
148: #define FPCR_IXE __BIT(12) // IneXact Exception enable
149: #define FPCR_UFE __BIT(11) // UnderFlow Exception enable
150: #define FPCR_OFE __BIT(10) // OverFlow Exception enable
151: #define FPCR_DZE __BIT(9) // Divide by Zero Exception enable
152: #define FPCR_IOE __BIT(8) // Invalid Operation Exception enable
153: #define FPCR_ESUM 0x1F00
1.1 matt 154:
155: AARCH64REG_READ_INLINE(fpsr) // Floating Point Status Register
156: AARCH64REG_WRITE_INLINE(fpsr)
157:
1.13 skrll 158: #define FPSR_N32 __BIT(31) // AARCH32 Negative
159: #define FPSR_Z32 __BIT(30) // AARCH32 Zero
160: #define FPSR_C32 __BIT(29) // AARCH32 Carry
161: #define FPSR_V32 __BIT(28) // AARCH32 Overflow
162: #define FPSR_QC __BIT(27) // SIMD Saturation
163: #define FPSR_IDC __BIT(7) // Input Denormal Cumulative status
164: #define FPSR_IXC __BIT(4) // IneXact Cumulative status
165: #define FPSR_UFC __BIT(3) // UnderFlow Cumulative status
166: #define FPSR_OFC __BIT(2) // OverFlow Cumulative status
167: #define FPSR_DZC __BIT(1) // Divide by Zero Cumulative status
168: #define FPSR_IOC __BIT(0) // Invalid Operation Cumulative status
169: #define FPSR_CSUM 0x1F
1.1 matt 170:
171: AARCH64REG_READ_INLINE(nzcv) // condition codes
172: AARCH64REG_WRITE_INLINE(nzcv)
173:
1.13 skrll 174: #define NZCV_N __BIT(31) // Negative
175: #define NZCV_Z __BIT(30) // Zero
176: #define NZCV_C __BIT(29) // Carry
177: #define NZCV_V __BIT(28) // Overflow
1.1 matt 178:
179: AARCH64REG_READ_INLINE(tpidr_el0) // Thread Pointer ID Register (RW)
180: AARCH64REG_WRITE_INLINE(tpidr_el0)
181:
1.9 ryo 182: AARCH64REG_READ_INLINE(tpidrro_el0) // Thread Pointer ID Register (RO)
183:
1.3 skrll 184: /*
1.1 matt 185: * From here on, these can only be accessed at EL1 (kernel)
186: */
187:
188: /*
189: * These are readonly registers
190: */
1.9 ryo 191: AARCH64REG_READ_INLINE(aidr_el1)
192:
1.14 skrll 193: AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57
1.1 matt 194:
1.13 skrll 195: #define CBAR_PA __BITS(47,18)
1.1 matt 196:
1.9 ryo 197: AARCH64REG_READ_INLINE(ccsidr_el1)
198:
1.46 ryo 199: /* 32bit format CCSIDR_EL1 */
1.37 ryo 200: #define CCSIDR_WT __BIT(31) // OBSOLETE: Write-through supported
201: #define CCSIDR_WB __BIT(30) // OBSOLETE: Write-back supported
202: #define CCSIDR_RA __BIT(29) // OBSOLETE: Read-allocation supported
203: #define CCSIDR_WA __BIT(28) // OBSOLETE: Write-allocation supported
1.13 skrll 204: #define CCSIDR_NUMSET __BITS(27,13) // (Number of sets in cache) - 1
205: #define CCSIDR_ASSOC __BITS(12,3) // (Associativity of cache) - 1
206: #define CCSIDR_LINESIZE __BITS(2,0) // Number of bytes in cache line
1.9 ryo 207:
1.46 ryo 208: /* 64bit format CCSIDR_EL1 (ARMv8.3-CCIDX is implemented) */
209: #define CCSIDR64_NUMSET __BITS(55,32) // (Number of sets in cache) - 1
210: #define CCSIDR64_ASSOC __BITS(23,3) // (Associativity of cache) - 1
211: #define CCSIDR64_LINESIZE __BITS(2,0) // Number of bytes in cache line
212:
1.1 matt 213: AARCH64REG_READ_INLINE(clidr_el1)
1.9 ryo 214:
1.37 ryo 215: #define CLIDR_ICB __BITS(32,30) // Inner cache boundary
1.13 skrll 216: #define CLIDR_LOUU __BITS(29,27) // Level of Unification Uniprocessor
217: #define CLIDR_LOC __BITS(26,24) // Level of Coherency
218: #define CLIDR_LOUIS __BITS(23,21) // Level of Unification InnerShareable*/
219: #define CLIDR_CTYPE7 __BITS(20,18) // Cache Type field for level7
220: #define CLIDR_CTYPE6 __BITS(17,15) // Cache Type field for level6
221: #define CLIDR_CTYPE5 __BITS(14,12) // Cache Type field for level5
222: #define CLIDR_CTYPE4 __BITS(11,9) // Cache Type field for level4
223: #define CLIDR_CTYPE3 __BITS(8,6) // Cache Type field for level3
224: #define CLIDR_CTYPE2 __BITS(5,3) // Cache Type field for level2
225: #define CLIDR_CTYPE1 __BITS(2,0) // Cache Type field for level1
226: #define CLIDR_TYPE_NOCACHE 0 // No cache
227: #define CLIDR_TYPE_ICACHE 1 // Instruction cache only
228: #define CLIDR_TYPE_DCACHE 2 // Data cache only
229: #define CLIDR_TYPE_IDCACHE 3 // Separate inst and data caches
230: #define CLIDR_TYPE_UNIFIEDCACHE 4 // Unified cache
1.9 ryo 231:
232: AARCH64REG_READ_INLINE(currentel)
233: AARCH64REG_READ_INLINE(id_aa64afr0_el1)
234: AARCH64REG_READ_INLINE(id_aa64afr1_el1)
235: AARCH64REG_READ_INLINE(id_aa64dfr0_el1)
236:
1.37 ryo 237: #define ID_AA64DFR0_EL1_TRACEFILT __BITS(43,40)
238: #define ID_AA64DFR0_EL1_TRACEFILT_NONE 0
239: #define ID_AA64DFR0_EL1_TRACEFILT_IMPL 1
1.38 ryo 240: #define ID_AA64DFR0_EL1_DBLLOCK __BITS(39,36)
1.37 ryo 241: #define ID_AA64DFR0_EL1_DBLLOCK_IMPL 0
242: #define ID_AA64DFR0_EL1_DBLLOCK_NONE 15
243: #define ID_AA64DFR0_EL1_PMSVER __BITS(35,32)
1.13 skrll 244: #define ID_AA64DFR0_EL1_CTX_CMPS __BITS(31,28)
245: #define ID_AA64DFR0_EL1_WRPS __BITS(20,23)
246: #define ID_AA64DFR0_EL1_BRPS __BITS(12,15)
247: #define ID_AA64DFR0_EL1_PMUVER __BITS(8,11)
248: #define ID_AA64DFR0_EL1_PMUVER_NONE 0
1.12 christos 249: #define ID_AA64DFR0_EL1_PMUVER_V3 1
1.13 skrll 250: #define ID_AA64DFR0_EL1_PMUVER_NOV3 2
1.63 ! ryo 251: #define ID_AA64DFR0_EL1_PMUVER_V3P1 4
! 252: #define ID_AA64DFR0_EL1_PMUVER_V3P4 5
! 253: #define ID_AA64DFR0_EL1_PMUVER_V3P5 6
! 254: #define ID_AA64DFR0_EL1_PMUVER_V3P7 7
1.57 jmcneill 255: #define ID_AA64DFR0_EL1_PMUVER_IMPL 15
1.13 skrll 256: #define ID_AA64DFR0_EL1_TRACEVER __BITS(4,7)
257: #define ID_AA64DFR0_EL1_TRACEVER_NONE 0
258: #define ID_AA64DFR0_EL1_TRACEVER_IMPL 1
259: #define ID_AA64DFR0_EL1_DEBUGVER __BITS(0,3)
260: #define ID_AA64DFR0_EL1_DEBUGVER_V8A 6
1.9 ryo 261:
262: AARCH64REG_READ_INLINE(id_aa64dfr1_el1)
263:
264: AARCH64REG_READ_INLINE(id_aa64isar0_el1)
265:
1.41 riastrad 266: #define ID_AA64ISAR0_EL1_RNDR __BITS(63,60)
1.37 ryo 267: #define ID_AA64ISAR0_EL1_RNDR_NONE 0
268: #define ID_AA64ISAR0_EL1_RNDR_RNDRRS 1
269: #define ID_AA64ISAR0_EL1_TLB __BITS(59,56)
270: #define ID_AA64ISAR0_EL1_TLB_NONE 0
271: #define ID_AA64ISAR0_EL1_TLB_OS 1
272: #define ID_AA64ISAR0_EL1_TLB_OS_TLB 2
273: #define ID_AA64ISAR0_EL1_TS __BITS(55,52)
274: #define ID_AA64ISAR0_EL1_TS_NONE 0
275: #define ID_AA64ISAR0_EL1_TS_CFINV 1
276: #define ID_AA64ISAR0_EL1_TS_AXFLAG 2
277: #define ID_AA64ISAR0_EL1_FHM __BITS(51,48)
278: #define ID_AA64ISAR0_EL1_FHM_NONE 0
279: #define ID_AA64ISAR0_EL1_FHM_FMLAL 1
280: #define ID_AA64ISAR0_EL1_DP __BITS(47,44)
281: #define ID_AA64ISAR0_EL1_DP_NONE 0
282: #define ID_AA64ISAR0_EL1_DP_UDOT 1
283: #define ID_AA64ISAR0_EL1_SM4 __BITS(43,40)
284: #define ID_AA64ISAR0_EL1_SM4_NONE 0
285: #define ID_AA64ISAR0_EL1_SM4_SM4 1
286: #define ID_AA64ISAR0_EL1_SM3 __BITS(39,36)
287: #define ID_AA64ISAR0_EL1_SM3_NONE 0
288: #define ID_AA64ISAR0_EL1_SM3_SM3 1
289: #define ID_AA64ISAR0_EL1_SHA3 __BITS(35,32)
290: #define ID_AA64ISAR0_EL1_SHA3_NONE 0
291: #define ID_AA64ISAR0_EL1_SHA3_EOR3 1
292: #define ID_AA64ISAR0_EL1_RDM __BITS(31,28)
293: #define ID_AA64ISAR0_EL1_RDM_NONE 0
294: #define ID_AA64ISAR0_EL1_RDM_SQRDML 1
295: #define ID_AA64ISAR0_EL1_ATOMIC __BITS(23,20)
296: #define ID_AA64ISAR0_EL1_ATOMIC_NONE 0
1.60 ryo 297: #define ID_AA64ISAR0_EL1_ATOMIC_SWP 2
1.13 skrll 298: #define ID_AA64ISAR0_EL1_CRC32 __BITS(19,16)
299: #define ID_AA64ISAR0_EL1_CRC32_NONE 0
300: #define ID_AA64ISAR0_EL1_CRC32_CRC32X 1
301: #define ID_AA64ISAR0_EL1_SHA2 __BITS(15,12)
1.12 christos 302: #define ID_AA64ISAR0_EL1_SHA2_NONE 0
303: #define ID_AA64ISAR0_EL1_SHA2_SHA256HSU 1
1.37 ryo 304: #define ID_AA64ISAR0_EL1_SHA2_SHA512HSU 2
1.13 skrll 305: #define ID_AA64ISAR0_EL1_SHA1 __BITS(11,8)
1.12 christos 306: #define ID_AA64ISAR0_EL1_SHA1_NONE 0
307: #define ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU 1
1.13 skrll 308: #define ID_AA64ISAR0_EL1_AES __BITS(7,4)
1.12 christos 309: #define ID_AA64ISAR0_EL1_AES_NONE 0
310: #define ID_AA64ISAR0_EL1_AES_AES 1
311: #define ID_AA64ISAR0_EL1_AES_PMUL 2
1.9 ryo 312:
313: AARCH64REG_READ_INLINE(id_aa64isar1_el1)
1.31 maxv 314:
1.54 ryo 315: #define ID_AA64ISAR1_EL1_I8MM __BITS(55,52)
316: #define ID_AA64ISAR1_EL1_I8MM_NONE 0
317: #define ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
318: #define ID_AA64ISAR1_EL1_DGH __BITS(51,48)
319: #define ID_AA64ISAR1_EL1_DGH_NONE 0
320: #define ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
321: #define ID_AA64ISAR1_EL1_BF16 __BITS(47,44)
322: #define ID_AA64ISAR1_EL1_BF16_NONE 0
323: #define ID_AA64ISAR1_EL1_BF16_BFDOT 1
1.31 maxv 324: #define ID_AA64ISAR1_EL1_SPECRES __BITS(43,40)
325: #define ID_AA64ISAR1_EL1_SPECRES_NONE 0
326: #define ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
327: #define ID_AA64ISAR1_EL1_SB __BITS(39,36)
328: #define ID_AA64ISAR1_EL1_SB_NONE 0
329: #define ID_AA64ISAR1_EL1_SB_SUPPORTED 1
330: #define ID_AA64ISAR1_EL1_FRINTTS __BITS(35,32)
331: #define ID_AA64ISAR1_EL1_FRINTTS_NONE 0
332: #define ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
333: #define ID_AA64ISAR1_EL1_GPI __BITS(31,28)
334: #define ID_AA64ISAR1_EL1_GPI_NONE 0
335: #define ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
336: #define ID_AA64ISAR1_EL1_GPA __BITS(27,24)
337: #define ID_AA64ISAR1_EL1_GPA_NONE 0
338: #define ID_AA64ISAR1_EL1_GPA_QARMA 1
339: #define ID_AA64ISAR1_EL1_LRCPC __BITS(23,20)
340: #define ID_AA64ISAR1_EL1_LRCPC_NONE 0
341: #define ID_AA64ISAR1_EL1_LRCPC_PR 1
342: #define ID_AA64ISAR1_EL1_LRCPC_PR_UR 2
343: #define ID_AA64ISAR1_EL1_FCMA __BITS(19,16)
344: #define ID_AA64ISAR1_EL1_FCMA_NONE 0
345: #define ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
346: #define ID_AA64ISAR1_EL1_JSCVT __BITS(15,12)
347: #define ID_AA64ISAR1_EL1_JSCVT_NONE 0
348: #define ID_AA64ISAR1_EL1_JSCVT_SUPPORTED 1
349: #define ID_AA64ISAR1_EL1_API __BITS(11,8)
350: #define ID_AA64ISAR1_EL1_API_NONE 0
351: #define ID_AA64ISAR1_EL1_API_SUPPORTED 1
352: #define ID_AA64ISAR1_EL1_API_ENHANCED 2
353: #define ID_AA64ISAR1_EL1_APA __BITS(7,4)
354: #define ID_AA64ISAR1_EL1_APA_NONE 0
355: #define ID_AA64ISAR1_EL1_APA_QARMA 1
356: #define ID_AA64ISAR1_EL1_APA_QARMA_ENH 2
357: #define ID_AA64ISAR1_EL1_DPB __BITS(3,0)
358: #define ID_AA64ISAR1_EL1_DPB_NONE 0
359: #define ID_AA64ISAR1_EL1_DPB_CVAP 1
360: #define ID_AA64ISAR1_EL1_DPB_CVAP_CVADP 2
361:
1.9 ryo 362: AARCH64REG_READ_INLINE(id_aa64mmfr0_el1)
363:
1.37 ryo 364: #define ID_AA64MMFR0_EL1_EXS __BITS(43,40)
1.13 skrll 365: #define ID_AA64MMFR0_EL1_TGRAN4 __BITS(31,28)
366: #define ID_AA64MMFR0_EL1_TGRAN4_4KB 0
367: #define ID_AA64MMFR0_EL1_TGRAN4_NONE 15
368: #define ID_AA64MMFR0_EL1_TGRAN64 __BITS(24,27)
369: #define ID_AA64MMFR0_EL1_TGRAN64_64KB 0
370: #define ID_AA64MMFR0_EL1_TGRAN64_NONE 15
371: #define ID_AA64MMFR0_EL1_TGRAN16 __BITS(20,23)
372: #define ID_AA64MMFR0_EL1_TGRAN16_NONE 0
373: #define ID_AA64MMFR0_EL1_TGRAN16_16KB 1
374: #define ID_AA64MMFR0_EL1_BIGENDEL0 __BITS(16,19)
1.12 christos 375: #define ID_AA64MMFR0_EL1_BIGENDEL0_NONE 0
1.13 skrll 376: #define ID_AA64MMFR0_EL1_BIGENDEL0_MIX 1
377: #define ID_AA64MMFR0_EL1_SNSMEM __BITS(12,15)
378: #define ID_AA64MMFR0_EL1_SNSMEM_NONE 0
379: #define ID_AA64MMFR0_EL1_SNSMEM_SNSMEM 1
380: #define ID_AA64MMFR0_EL1_BIGEND __BITS(8,11)
381: #define ID_AA64MMFR0_EL1_BIGEND_NONE 0
382: #define ID_AA64MMFR0_EL1_BIGEND_MIX 1
383: #define ID_AA64MMFR0_EL1_ASIDBITS __BITS(4,7)
384: #define ID_AA64MMFR0_EL1_ASIDBITS_8BIT 0
1.12 christos 385: #define ID_AA64MMFR0_EL1_ASIDBITS_16BIT 2
1.13 skrll 386: #define ID_AA64MMFR0_EL1_PARANGE __BITS(0,3)
387: #define ID_AA64MMFR0_EL1_PARANGE_4G 0
388: #define ID_AA64MMFR0_EL1_PARANGE_64G 1
389: #define ID_AA64MMFR0_EL1_PARANGE_1T 2
390: #define ID_AA64MMFR0_EL1_PARANGE_4T 3
391: #define ID_AA64MMFR0_EL1_PARANGE_16T 4
392: #define ID_AA64MMFR0_EL1_PARANGE_256T 5
1.37 ryo 393: #define ID_AA64MMFR0_EL1_PARANGE_4P 6
1.9 ryo 394:
395: AARCH64REG_READ_INLINE(id_aa64mmfr1_el1)
1.31 maxv 396:
397: #define ID_AA64MMFR1_EL1_XNX __BITS(31,28)
398: #define ID_AA64MMFR1_EL1_XNX_NONE 0
399: #define ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
400: #define ID_AA64MMFR1_EL1_SPECSEI __BITS(27,24)
401: #define ID_AA64MMFR1_EL1_SPECSEI_NONE 0
402: #define ID_AA64MMFR1_EL1_SPECSEI_EXTINT 1
403: #define ID_AA64MMFR1_EL1_PAN __BITS(23,20)
404: #define ID_AA64MMFR1_EL1_PAN_NONE 0
405: #define ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
406: #define ID_AA64MMFR1_EL1_PAN_S1E1 2
407: #define ID_AA64MMFR1_EL1_LO __BITS(19,16)
408: #define ID_AA64MMFR1_EL1_LO_NONE 0
409: #define ID_AA64MMFR1_EL1_LO_SUPPORTED 1
410: #define ID_AA64MMFR1_EL1_HPDS __BITS(15,12)
411: #define ID_AA64MMFR1_EL1_HPDS_NONE 0
412: #define ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
413: #define ID_AA64MMFR1_EL1_HPDS_EXTRA_PTD 2
414: #define ID_AA64MMFR1_EL1_VH __BITS(11,8)
415: #define ID_AA64MMFR1_EL1_VH_NONE 0
416: #define ID_AA64MMFR1_EL1_VH_SUPPORTED 1
417: #define ID_AA64MMFR1_EL1_VMIDBITS __BITS(7,4)
418: #define ID_AA64MMFR1_EL1_VMIDBITS_8BIT 0
419: #define ID_AA64MMFR1_EL1_VMIDBITS_16BIT 2
420: #define ID_AA64MMFR1_EL1_HAFDBS __BITS(3,0)
421: #define ID_AA64MMFR1_EL1_HAFDBS_NONE 0
422: #define ID_AA64MMFR1_EL1_HAFDBS_A 1
423: #define ID_AA64MMFR1_EL1_HAFDBS_AD 2
424:
1.33 maxv 425: AARCH64REG_READ_INLINE3(id_aa64mmfr2_el1, id_aa64mmfr2_el1,
1.42 ryo 426: ATTR_ARCH("armv8.2-a"))
1.31 maxv 427:
428: #define ID_AA64MMFR2_EL1_E0PD __BITS(63,60)
429: #define ID_AA64MMFR2_EL1_E0PD_NONE 0
430: #define ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
431: #define ID_AA64MMFR2_EL1_EVT __BITS(59,56)
432: #define ID_AA64MMFR2_EL1_EVT_NONE 0
433: #define ID_AA64MMFR2_EL1_EVT_TO_TI 1
434: #define ID_AA64MMFR2_EL1_EVT_TO_TI_TTL 2
435: #define ID_AA64MMFR2_EL1_BBM __BITS(55,52)
436: #define ID_AA64MMFR2_EL1_BBM_L0 0
437: #define ID_AA64MMFR2_EL1_BBM_L1 1
438: #define ID_AA64MMFR2_EL1_BBM_L2 2
439: #define ID_AA64MMFR2_EL1_TTL __BITS(51,48)
440: #define ID_AA64MMFR2_EL1_TTL_NONE 0
441: #define ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
442: #define ID_AA64MMFR2_EL1_FWB __BITS(43,40)
443: #define ID_AA64MMFR2_EL1_FWB_NONE 0
444: #define ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
445: #define ID_AA64MMFR2_EL1_IDS __BITS(39,36)
446: #define ID_AA64MMFR2_EL1_IDS_0X0 0
447: #define ID_AA64MMFR2_EL1_IDS_0X18 1
448: #define ID_AA64MMFR2_EL1_AT __BITS(35,32)
449: #define ID_AA64MMFR2_EL1_AT_NONE 0
450: #define ID_AA64MMFR2_EL1_AT_16BIT 1
451: #define ID_AA64MMFR2_EL1_ST __BITS(31,28)
452: #define ID_AA64MMFR2_EL1_ST_39 0
453: #define ID_AA64MMFR2_EL1_ST_48 1
454: #define ID_AA64MMFR2_EL1_NV __BITS(27,24)
455: #define ID_AA64MMFR2_EL1_NV_NONE 0
456: #define ID_AA64MMFR2_EL1_NV_HCR 1
457: #define ID_AA64MMFR2_EL1_NV_HCR_VNCR 2
458: #define ID_AA64MMFR2_EL1_CCIDX __BITS(23,20)
459: #define ID_AA64MMFR2_EL1_CCIDX_32BIT 0
460: #define ID_AA64MMFR2_EL1_CCIDX_64BIT 1
461: #define ID_AA64MMFR2_EL1_VARANGE __BITS(19,16)
462: #define ID_AA64MMFR2_EL1_VARANGE_48BIT 0
463: #define ID_AA64MMFR2_EL1_VARANGE_52BIT 1
464: #define ID_AA64MMFR2_EL1_IESB __BITS(15,12)
465: #define ID_AA64MMFR2_EL1_IESB_NONE 0
466: #define ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
467: #define ID_AA64MMFR2_EL1_LSM __BITS(11,8)
468: #define ID_AA64MMFR2_EL1_LSM_NONE 0
469: #define ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
470: #define ID_AA64MMFR2_EL1_UAO __BITS(7,4)
471: #define ID_AA64MMFR2_EL1_UAO_NONE 0
472: #define ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
473: #define ID_AA64MMFR2_EL1_CNP __BITS(3,0)
474: #define ID_AA64MMFR2_EL1_CNP_NONE 0
475: #define ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
476:
477: AARCH64REG_READ_INLINE2(a72_cpuactlr_el1, s3_1_c15_c2_0)
1.9 ryo 478: AARCH64REG_READ_INLINE(id_aa64pfr0_el1)
479: AARCH64REG_READ_INLINE(id_aa64pfr1_el1)
1.31 maxv 480:
481: #define ID_AA64PFR1_EL1_RASFRAC __BITS(15,12)
482: #define ID_AA64PFR1_EL1_RASFRAC_NORMAL 0
483: #define ID_AA64PFR1_EL1_RASFRAC_EXTRA 1
484: #define ID_AA64PFR1_EL1_MTE __BITS(11,8)
485: #define ID_AA64PFR1_EL1_MTE_NONE 0
486: #define ID_AA64PFR1_EL1_MTE_PARTIAL 1
487: #define ID_AA64PFR1_EL1_MTE_SUPPORTED 2
488: #define ID_AA64PFR1_EL1_SSBS __BITS(7,4)
489: #define ID_AA64PFR1_EL1_SSBS_NONE 0
490: #define ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
491: #define ID_AA64PFR1_EL1_SSBS_MSR_MRS 2
492: #define ID_AA64PFR1_EL1_BT __BITS(3,0)
493: #define ID_AA64PFR1_EL1_BT_NONE 0
494: #define ID_AA64PFR1_EL1_BT_SUPPORTED 1
495:
1.21 mrg 496: AARCH64REG_READ_INLINE(id_aa64zfr0_el1)
1.9 ryo 497: AARCH64REG_READ_INLINE(id_pfr1_el1)
1.1 matt 498: AARCH64REG_READ_INLINE(isr_el1)
499: AARCH64REG_READ_INLINE(midr_el1)
500: AARCH64REG_READ_INLINE(mpidr_el1)
1.9 ryo 501:
1.21 mrg 502: #define MIDR_EL1_IMPL __BITS(31,24) // Implementor
503: #define MIDR_EL1_VARIANT __BITS(23,20) // CPU Variant
504: #define MIDR_EL1_ARCH __BITS(19,16) // Architecture
505: #define MIDR_EL1_PARTNUM __BITS(15,4) // PartNum
506: #define MIDR_EL1_REVISION __BITS(3,0) // Revision
507:
1.13 skrll 508: #define MPIDR_AFF3 __BITS(32,39)
509: #define MPIDR_U __BIT(30) // 1 = Uni-Processor System
510: #define MPIDR_MT __BIT(24) // 1 = SMT(AFF0 is logical)
511: #define MPIDR_AFF2 __BITS(16,23)
512: #define MPIDR_AFF1 __BITS(8,15)
513: #define MPIDR_AFF0 __BITS(0,7)
1.9 ryo 514:
1.1 matt 515: AARCH64REG_READ_INLINE(mvfr0_el1)
1.9 ryo 516:
1.14 skrll 517: #define MVFR0_FPROUND __BITS(31,28)
518: #define MVFR0_FPROUND_NEAREST 0
1.12 christos 519: #define MVFR0_FPROUND_ALL 1
1.14 skrll 520: #define MVFR0_FPSHVEC __BITS(27,24)
1.12 christos 521: #define MVFR0_FPSHVEC_NONE 0
1.14 skrll 522: #define MVFR0_FPSHVEC_SHVEC 1
523: #define MVFR0_FPSQRT __BITS(23,20)
1.12 christos 524: #define MVFR0_FPSQRT_NONE 0
525: #define MVFR0_FPSQRT_VSQRT 1
1.14 skrll 526: #define MVFR0_FPDIVIDE __BITS(19,16)
527: #define MVFR0_FPDIVIDE_NONE 0
528: #define MVFR0_FPDIVIDE_VDIV 1
529: #define MVFR0_FPTRAP __BITS(15,12)
1.12 christos 530: #define MVFR0_FPTRAP_NONE 0
531: #define MVFR0_FPTRAP_TRAP 1
1.14 skrll 532: #define MVFR0_FPDP __BITS(11,8)
1.12 christos 533: #define MVFR0_FPDP_NONE 0
534: #define MVFR0_FPDP_VFPV2 1
535: #define MVFR0_FPDP_VFPV3 2
1.14 skrll 536: #define MVFR0_FPSP __BITS(7,4)
1.12 christos 537: #define MVFR0_FPSP_NONE 0
538: #define MVFR0_FPSP_VFPV2 1
539: #define MVFR0_FPSP_VFPV3 2
1.14 skrll 540: #define MVFR0_SIMDREG __BITS(3,0)
1.12 christos 541: #define MVFR0_SIMDREG_NONE 0
1.14 skrll 542: #define MVFR0_SIMDREG_16x64 1
543: #define MVFR0_SIMDREG_32x64 2
1.9 ryo 544:
1.1 matt 545: AARCH64REG_READ_INLINE(mvfr1_el1)
1.9 ryo 546:
1.14 skrll 547: #define MVFR1_SIMDFMAC __BITS(31,28)
548: #define MVFR1_SIMDFMAC_NONE 0
549: #define MVFR1_SIMDFMAC_FMAC 1
550: #define MVFR1_FPHP __BITS(27,24)
1.12 christos 551: #define MVFR1_FPHP_NONE 0
1.14 skrll 552: #define MVFR1_FPHP_HALF_SINGLE 1
553: #define MVFR1_FPHP_HALF_DOUBLE 2
1.20 riastrad 554: #define MVFR1_FPHP_HALF_ARITH 3
1.14 skrll 555: #define MVFR1_SIMDHP __BITS(23,20)
1.12 christos 556: #define MVFR1_SIMDHP_NONE 0
557: #define MVFR1_SIMDHP_HALF 1
1.20 riastrad 558: #define MVFR1_SIMDHP_HALF_ARITH 3
1.14 skrll 559: #define MVFR1_SIMDSP __BITS(19,16)
1.12 christos 560: #define MVFR1_SIMDSP_NONE 0
1.14 skrll 561: #define MVFR1_SIMDSP_SINGLE 1
562: #define MVFR1_SIMDINT __BITS(15,12)
1.12 christos 563: #define MVFR1_SIMDINT_NONE 0
1.14 skrll 564: #define MVFR1_SIMDINT_INTEGER 1
565: #define MVFR1_SIMDLS __BITS(11,8)
1.12 christos 566: #define MVFR1_SIMDLS_NONE 0
1.14 skrll 567: #define MVFR1_SIMDLS_LOADSTORE 1
568: #define MVFR1_FPDNAN __BITS(7,4)
1.12 christos 569: #define MVFR1_FPDNAN_NONE 0
570: #define MVFR1_FPDNAN_NAN 1
1.14 skrll 571: #define MVFR1_FPFTZ __BITS(3,0)
1.12 christos 572: #define MVFR1_FPFTZ_NONE 0
1.14 skrll 573: #define MVFR1_FPFTZ_DENORMAL 1
1.9 ryo 574:
1.1 matt 575: AARCH64REG_READ_INLINE(mvfr2_el1)
1.9 ryo 576:
1.14 skrll 577: #define MVFR2_FPMISC __BITS(7,4)
1.12 christos 578: #define MVFR2_FPMISC_NONE 0
579: #define MVFR2_FPMISC_SEL 1
1.14 skrll 580: #define MVFR2_FPMISC_DROUND 2
581: #define MVFR2_FPMISC_ROUNDINT 3
582: #define MVFR2_FPMISC_MAXMIN 4
583: #define MVFR2_SIMDMISC __BITS(3,0)
584: #define MVFR2_SIMDMISC_NONE 0
585: #define MVFR2_SIMDMISC_DROUND 1
1.12 christos 586: #define MVFR2_SIMDMISC_ROUNDINT 2
1.14 skrll 587: #define MVFR2_SIMDMISC_MAXMIN 3
1.9 ryo 588:
1.1 matt 589: AARCH64REG_READ_INLINE(revidr_el1)
590:
591: /*
592: * These are read/write registers
593: */
1.42 ryo 594: AARCH64REG_READ_INLINE3(APIAKeyLo_EL1, apiakeylo_el1, ATTR_ARCH("armv8.3-a"))
595: AARCH64REG_WRITE_INLINE3(APIAKeyLo_EL1, apiakeylo_el1, ATTR_ARCH("armv8.3-a"))
596: AARCH64REG_READ_INLINE3(APIAKeyHi_EL1, apiakeyhi_el1, ATTR_ARCH("armv8.3-a"))
597: AARCH64REG_WRITE_INLINE3(APIAKeyHi_EL1, apiakeyhi_el1, ATTR_ARCH("armv8.3-a"))
598:
1.45 ryo 599: AARCH64REG_READ_INLINE3(APIBKeyLo_EL1, apibkeylo_el1, ATTR_ARCH("armv8.3-a"))
600: AARCH64REG_WRITE_INLINE3(APIBKeyLo_EL1, apibkeylo_el1, ATTR_ARCH("armv8.3-a"))
601: AARCH64REG_READ_INLINE3(APIBKeyHi_EL1, apibkeyhi_el1, ATTR_ARCH("armv8.3-a"))
602: AARCH64REG_WRITE_INLINE3(APIBKeyHi_EL1, apibkeyhi_el1, ATTR_ARCH("armv8.3-a"))
603:
604: AARCH64REG_READ_INLINE3(APDAKeyLo_EL1, apdakeylo_el1, ATTR_ARCH("armv8.3-a"))
605: AARCH64REG_WRITE_INLINE3(APDAKeyLo_EL1, apdakeylo_el1, ATTR_ARCH("armv8.3-a"))
606: AARCH64REG_READ_INLINE3(APDAKeyHi_EL1, apdakeyhi_el1, ATTR_ARCH("armv8.3-a"))
607: AARCH64REG_WRITE_INLINE3(APDAKeyHi_EL1, apdakeyhi_el1, ATTR_ARCH("armv8.3-a"))
608:
609: AARCH64REG_READ_INLINE3(APDBKeyLo_EL1, apdbkeylo_el1, ATTR_ARCH("armv8.3-a"))
610: AARCH64REG_WRITE_INLINE3(APDBKeyLo_EL1, apdbkeylo_el1, ATTR_ARCH("armv8.3-a"))
611: AARCH64REG_READ_INLINE3(APDBKeyHi_EL1, apdbkeyhi_el1, ATTR_ARCH("armv8.3-a"))
612: AARCH64REG_WRITE_INLINE3(APDBKeyHi_EL1, apdbkeyhi_el1, ATTR_ARCH("armv8.3-a"))
613:
614: AARCH64REG_READ_INLINE3(APGAKeyLo_EL1, apgakeylo_el1, ATTR_ARCH("armv8.3-a"))
615: AARCH64REG_WRITE_INLINE3(APGAKeyLo_EL1, apgakeylo_el1, ATTR_ARCH("armv8.3-a"))
616: AARCH64REG_READ_INLINE3(APGAKeyHi_EL1, apgakeyhi_el1, ATTR_ARCH("armv8.3-a"))
617: AARCH64REG_WRITE_INLINE3(APGAKeyHi_EL1, apgakeyhi_el1, ATTR_ARCH("armv8.3-a"))
618:
1.52 maxv 619: AARCH64REG_READ_INLINE3(pan, pan, ATTR_ARCH("armv8.1-a"))
620: AARCH64REG_WRITE_INLINE3(pan, pan, ATTR_ARCH("armv8.1-a"))
621:
1.1 matt 622: AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser
623: AARCH64REG_WRITE_INLINE(cpacr_el1)
624:
1.14 skrll 625: #define CPACR_TTA __BIT(28) // System Register Access Traps
626: #define CPACR_FPEN __BITS(21,20)
627: #define CPACR_FPEN_NONE __SHIFTIN(0, CPACR_FPEN)
628: #define CPACR_FPEN_EL1 __SHIFTIN(1, CPACR_FPEN)
629: #define CPACR_FPEN_NONE_2 __SHIFTIN(2, CPACR_FPEN)
630: #define CPACR_FPEN_ALL __SHIFTIN(3, CPACR_FPEN)
1.1 matt 631:
1.9 ryo 632: AARCH64REG_READ_INLINE(csselr_el1) // Cache Size Selection Register
633: AARCH64REG_WRITE_INLINE(csselr_el1)
634:
1.14 skrll 635: #define CSSELR_LEVEL __BITS(3,1) // Cache level of required cache
636: #define CSSELR_IND __BIT(0) // Instruction not Data bit
1.9 ryo 637:
638: AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register
639: AARCH64REG_WRITE_INLINE(daif)
640: AARCH64REG_WRITEIMM_INLINE(daifclr)
641: AARCH64REG_WRITEIMM_INLINE(daifset)
642:
1.14 skrll 643: #define DAIF_D __BIT(9) // Debug Exception Mask
644: #define DAIF_A __BIT(8) // SError Abort Mask
645: #define DAIF_I __BIT(7) // IRQ Mask
646: #define DAIF_F __BIT(6) // FIQ Mask
647: #define DAIF_SETCLR_SHIFT 6 // for daifset/daifclr #imm shift
1.9 ryo 648:
1.1 matt 649: AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register
650: AARCH64REG_WRITE_INLINE(elr_el1)
651:
652: AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register
653: AARCH64REG_WRITE_INLINE(esr_el1)
654:
1.14 skrll 655: #define ESR_EC __BITS(31,26) // Exception Cause
656: #define ESR_EC_UNKNOWN 0x00 // AXX: Unknown Reason
657: #define ESR_EC_WFX 0x01 // AXX: WFI or WFE instruction execution
658: #define ESR_EC_CP15_RT 0x03 // A32: MCR/MRC access to CP15 !EC=0
659: #define ESR_EC_CP15_RRT 0x04 // A32: MCRR/MRRC access to CP15 !EC=0
660: #define ESR_EC_CP14_RT 0x05 // A32: MCR/MRC access to CP14
661: #define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14
662: #define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers
663: #define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7
664: #define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14
1.35 maxv 665: #define ESR_EC_BTE_A64 0x0d // A64: Branch Target Exception (V8.5)
1.14 skrll 666: #define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State
667: #define ESR_EC_SVC_A32 0x11 // A32: SVC Instruction Execution
668: #define ESR_EC_HVC_A32 0x12 // A32: HVC Instruction Execution
669: #define ESR_EC_SMC_A32 0x13 // A32: SMC Instruction Execution
670: #define ESR_EC_SVC_A64 0x15 // A64: SVC Instruction Execution
671: #define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution
672: #define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution
673: #define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7)
674: #define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0)
675: #define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1)
676: #define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC
677: #define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0)
678: #define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1)
679: #define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP
680: #define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception
681: #define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception
682: #define ESR_EC_SERROR 0x2f // AXX: SError Interrupt
683: #define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0)
684: #define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1)
685: #define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0)
686: #define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1)
687: #define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0)
688: #define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1)
689: #define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution
690: #define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception
691: #define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution
692: #define ESR_IL __BIT(25) // Instruction Length (1=32-bit)
693: #define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome
1.12 christos 694: #define ESR_ISS_CV __BIT(24) // common
695: #define ESR_ISS_COND __BITS(23,20) // common
696: #define ESR_ISS_WFX_TRAP_INSN __BIT(0) // for ESR_EC_WFX
697: #define ESR_ISS_MRC_OPC2 __BITS(19,17) // for ESR_EC_CP15_RT
698: #define ESR_ISS_MRC_OPC1 __BITS(16,14) // for ESR_EC_CP15_RT
699: #define ESR_ISS_MRC_CRN __BITS(13,10) // for ESR_EC_CP15_RT
700: #define ESR_ISS_MRC_RT __BITS(9,5) // for ESR_EC_CP15_RT
701: #define ESR_ISS_MRC_CRM __BITS(4,1) // for ESR_EC_CP15_RT
702: #define ESR_ISS_MRC_DIRECTION __BIT(0) // for ESR_EC_CP15_RT
703: #define ESR_ISS_MCRR_OPC1 __BITS(19,16) // for ESR_EC_CP15_RRT
704: #define ESR_ISS_MCRR_RT2 __BITS(14,10) // for ESR_EC_CP15_RRT
705: #define ESR_ISS_MCRR_RT __BITS(9,5) // for ESR_EC_CP15_RRT
706: #define ESR_ISS_MCRR_CRM __BITS(4,1) // for ESR_EC_CP15_RRT
707: #define ESR_ISS_MCRR_DIRECTION __BIT(0) // for ESR_EC_CP15_RRT
708: #define ESR_ISS_HVC_IMM16 __BITS(15,0) // for ESR_EC_{SVC,HVC}
709: // ...
710: #define ESR_ISS_INSNABORT_EA __BIT(9) // for ESC_RC_INSN_ABT_EL[01]
711: #define ESR_ISS_INSNABORT_S1PTW __BIT(7) // for ESC_RC_INSN_ABT_EL[01]
712: #define ESR_ISS_INSNABORT_IFSC __BITS(0,5) // for ESC_RC_INSN_ABT_EL[01]
713: #define ESR_ISS_DATAABORT_ISV __BIT(24) // for ESC_RC_DATA_ABT_EL[01]
714: #define ESR_ISS_DATAABORT_SAS __BITS(23,22) // for ESC_RC_DATA_ABT_EL[01]
715: #define ESR_ISS_DATAABORT_SSE __BIT(21) // for ESC_RC_DATA_ABT_EL[01]
716: #define ESR_ISS_DATAABORT_SRT __BITS(19,16) // for ESC_RC_DATA_ABT_EL[01]
717: #define ESR_ISS_DATAABORT_SF __BIT(15) // for ESC_RC_DATA_ABT_EL[01]
718: #define ESR_ISS_DATAABORT_AR __BIT(14) // for ESC_RC_DATA_ABT_EL[01]
719: #define ESR_ISS_DATAABORT_EA __BIT(9) // for ESC_RC_DATA_ABT_EL[01]
720: #define ESR_ISS_DATAABORT_CM __BIT(8) // for ESC_RC_DATA_ABT_EL[01]
721: #define ESR_ISS_DATAABORT_S1PTW __BIT(7) // for ESC_RC_DATA_ABT_EL[01]
722: #define ESR_ISS_DATAABORT_WnR __BIT(6) // for ESC_RC_DATA_ABT_EL[01]
723: #define ESR_ISS_DATAABORT_DFSC __BITS(0,5) // for ESC_RC_DATA_ABT_EL[01]
724:
1.14 skrll 725: #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_0 0x00
726: #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_1 0x01
727: #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_2 0x02
728: #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_3 0x03
729: #define ESR_ISS_FSC_TRANSLATION_FAULT_0 0x04
730: #define ESR_ISS_FSC_TRANSLATION_FAULT_1 0x05
731: #define ESR_ISS_FSC_TRANSLATION_FAULT_2 0x06
732: #define ESR_ISS_FSC_TRANSLATION_FAULT_3 0x07
733: #define ESR_ISS_FSC_ACCESS_FAULT_0 0x08
734: #define ESR_ISS_FSC_ACCESS_FAULT_1 0x09
735: #define ESR_ISS_FSC_ACCESS_FAULT_2 0x0a
736: #define ESR_ISS_FSC_ACCESS_FAULT_3 0x0b
737: #define ESR_ISS_FSC_PERM_FAULT_0 0x0c
738: #define ESR_ISS_FSC_PERM_FAULT_1 0x0d
739: #define ESR_ISS_FSC_PERM_FAULT_2 0x0e
740: #define ESR_ISS_FSC_PERM_FAULT_3 0x0f
741: #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT 0x10
742: #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_0 0x14
743: #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_1 0x15
744: #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_2 0x16
745: #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_3 0x17
746: #define ESR_ISS_FSC_SYNC_PARITY_ERROR 0x18
747: #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_0 0x1c
748: #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_1 0x1d
749: #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_2 0x1e
750: #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_3 0x1f
751: #define ESR_ISS_FSC_ALIGNMENT_FAULT 0x21
752: #define ESR_ISS_FSC_TLB_CONFLICT_FAULT 0x30
753: #define ESR_ISS_FSC_LOCKDOWN_ABORT 0x34
754: #define ESR_ISS_FSC_UNSUPPORTED_EXCLUSIVE 0x35
755: #define ESR_ISS_FSC_FIRST_LEVEL_DOMAIN_FAULT 0x3d
756: #define ESR_ISS_FSC_SECOND_LEVEL_DOMAIN_FAULT 0x3e
1.1 matt 757:
758:
759: AARCH64REG_READ_INLINE(far_el1) // Fault Address Register
760: AARCH64REG_WRITE_INLINE(far_el1)
761:
1.9 ryo 762: AARCH64REG_READ_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73
763: AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73
764:
1.12 christos 765: #define L2CTLR_NUMOFCORE __BITS(25,24) // Number of cores
766: #define L2CTLR_CPUCACHEPROT __BIT(22) // CPU Cache Protection
767: #define L2CTLR_SCUL2CACHEPROT __BIT(21) // SCU-L2 Cache Protection
768: #define L2CTLR_L2_INPUT_LATENCY __BIT(5) // L2 Data RAM input latency
769: #define L2CTLR_L2_OUTPUT_LATENCY __BIT(0) // L2 Data RAM output latency
1.9 ryo 770:
771: AARCH64REG_READ_INLINE(mair_el1) // Memory Attribute Indirection Register
1.1 matt 772: AARCH64REG_WRITE_INLINE(mair_el1)
773:
1.14 skrll 774: #define MAIR_ATTR0 __BITS(7,0)
775: #define MAIR_ATTR1 __BITS(15,8)
776: #define MAIR_ATTR2 __BITS(23,16)
777: #define MAIR_ATTR3 __BITS(31,24)
778: #define MAIR_ATTR4 __BITS(39,32)
779: #define MAIR_ATTR5 __BITS(47,40)
780: #define MAIR_ATTR6 __BITS(55,48)
781: #define MAIR_ATTR7 __BITS(63,56)
782: #define MAIR_DEVICE_nGnRnE 0x00 // NoGathering,NoReordering,NoEarlyWriteAck.
1.29 jmcneill 783: #define MAIR_DEVICE_nGnRE 0x04 // NoGathering,NoReordering,EarlyWriteAck.
1.14 skrll 784: #define MAIR_NORMAL_NC 0x44
785: #define MAIR_NORMAL_WT 0xbb
786: #define MAIR_NORMAL_WB 0xff
1.9 ryo 787:
1.1 matt 788: AARCH64REG_READ_INLINE(par_el1) // Physical Address Register
789: AARCH64REG_WRITE_INLINE(par_el1)
790:
1.14 skrll 791: #define PAR_ATTR __BITS(63,56) // F=0 memory attributes
1.36 ryo 792: #define PAR_PA __BITS(51,12) // F=0 physical address
793: #define PAR_PA_SHIFT 12
1.14 skrll 794: #define PAR_NS __BIT(9) // F=0 non-secure
1.61 skrll 795: #define PAR_SH __BITS(8,7) // F=0 shareability attribute
796: #define PAR_SH_NONE 0
797: #define PAR_SH_OUTER 2
798: #define PAR_SH_INNER 3
799:
1.14 skrll 800: #define PAR_S __BIT(9) // F=1 failure stage
801: #define PAR_PTW __BIT(8) // F=1 partial table walk
802: #define PAR_FST __BITS(6,1) // F=1 fault status code
803: #define PAR_F __BIT(0) // translation failed
1.1 matt 804:
805: AARCH64REG_READ_INLINE(rmr_el1) // Reset Management Register
806: AARCH64REG_WRITE_INLINE(rmr_el1)
807:
808: AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register
809: AARCH64REG_WRITE_INLINE(rvbar_el1)
810:
1.24 ryo 811: AARCH64REG_ATWRITE_INLINE(s1e0r); // Address Translate Stages 1
812: AARCH64REG_ATWRITE_INLINE(s1e0w);
813: AARCH64REG_ATWRITE_INLINE(s1e1r);
814: AARCH64REG_ATWRITE_INLINE(s1e1w);
815:
1.2 skrll 816: AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register
817: AARCH64REG_WRITE_INLINE(sctlr_el1)
1.1 matt 818:
1.14 skrll 819: #define SCTLR_RES0 0xc8222400 // Reserved ARMv8.0, write 0
820: #define SCTLR_RES1 0x30d00800 // Reserved ARMv8.0, write 1
821: #define SCTLR_M __BIT(0)
822: #define SCTLR_A __BIT(1)
823: #define SCTLR_C __BIT(2)
824: #define SCTLR_SA __BIT(3)
825: #define SCTLR_SA0 __BIT(4)
826: #define SCTLR_CP15BEN __BIT(5)
1.32 maxv 827: #define SCTLR_nAA __BIT(6)
1.14 skrll 828: #define SCTLR_ITD __BIT(7)
829: #define SCTLR_SED __BIT(8)
830: #define SCTLR_UMA __BIT(9)
1.34 maxv 831: #define SCTLR_EnRCTX __BIT(10)
832: #define SCTLR_EOS __BIT(11)
1.14 skrll 833: #define SCTLR_I __BIT(12)
1.34 maxv 834: #define SCTLR_EnDB __BIT(13)
1.14 skrll 835: #define SCTLR_DZE __BIT(14)
836: #define SCTLR_UCT __BIT(15)
837: #define SCTLR_nTWI __BIT(16)
838: #define SCTLR_nTWE __BIT(18)
839: #define SCTLR_WXN __BIT(19)
1.34 maxv 840: #define SCTLR_TSCXT __BIT(20)
1.14 skrll 841: #define SCTLR_IESB __BIT(21)
1.34 maxv 842: #define SCTLR_EIS __BIT(22)
1.14 skrll 843: #define SCTLR_SPAN __BIT(23)
1.53 ryo 844: #define SCTLR_E0E __BIT(24)
1.14 skrll 845: #define SCTLR_EE __BIT(25)
846: #define SCTLR_UCI __BIT(26)
1.34 maxv 847: #define SCTLR_EnDA __BIT(27)
1.14 skrll 848: #define SCTLR_nTLSMD __BIT(28)
849: #define SCTLR_LSMAOE __BIT(29)
1.34 maxv 850: #define SCTLR_EnIB __BIT(30)
851: #define SCTLR_EnIA __BIT(31)
852: #define SCTLR_BT0 __BIT(35)
853: #define SCTLR_BT1 __BIT(36)
854: #define SCTLR_ITFSB __BIT(37)
855: #define SCTLR_TCF0 __BITS(39,38)
856: #define SCTLR_TCF __BITS(41,40)
857: #define SCTLR_ATA0 __BIT(42)
858: #define SCTLR_ATA __BIT(43)
859: #define SCTLR_DSSBS __BIT(44)
1.9 ryo 860:
861: // current EL stack pointer
1.12 christos 862: static __inline uint64_t
1.9 ryo 863: reg_sp_read(void)
864: {
865: uint64_t __rv;
866: __asm __volatile ("mov %0, sp" : "=r"(__rv));
867: return __rv;
868: }
869:
870: AARCH64REG_READ_INLINE(sp_el0) // EL0 Stack Pointer
1.1 matt 871: AARCH64REG_WRITE_INLINE(sp_el0)
872:
1.9 ryo 873: AARCH64REG_READ_INLINE(spsel) // Stack Pointer Select
874: AARCH64REG_WRITE_INLINE(spsel)
1.1 matt 875:
1.14 skrll 876: #define SPSEL_SP __BIT(0); // use SP_EL0 at all exception levels
1.1 matt 877:
878: AARCH64REG_READ_INLINE(spsr_el1) // Saved Program Status Register
879: AARCH64REG_WRITE_INLINE(spsr_el1)
880:
1.14 skrll 881: #define SPSR_NZCV __BITS(31,28) // mask of N Z C V
882: #define SPSR_N __BIT(31) // Negative
883: #define SPSR_Z __BIT(30) // Zero
884: #define SPSR_C __BIT(29) // Carry
885: #define SPSR_V __BIT(28) // oVerflow
886: #define SPSR_A32_Q __BIT(27) // A32: Overflow
1.32 maxv 887: #define SPSR_A32_IT1 __BIT(26) // A32: IT[1]
888: #define SPSR_A32_IT0 __BIT(25) // A32: IT[0]
1.52 maxv 889: #define SPSR_PAN __BIT(22) // Privileged Access Never
1.14 skrll 890: #define SPSR_SS __BIT(21) // Software Step
1.22 ryo 891: #define SPSR_SS_SHIFT 21
1.14 skrll 892: #define SPSR_IL __BIT(20) // Instruction Length
893: #define SPSR_GE __BITS(19,16) // A32: SIMD GE
894: #define SPSR_IT7 __BIT(15) // A32: IT[7]
895: #define SPSR_IT6 __BIT(14) // A32: IT[6]
896: #define SPSR_IT5 __BIT(13) // A32: IT[5]
897: #define SPSR_IT4 __BIT(12) // A32: IT[4]
898: #define SPSR_IT3 __BIT(11) // A32: IT[3]
899: #define SPSR_IT2 __BIT(10) // A32: IT[2]
1.44 ryo 900: #define SPSR_A64_BTYPE __BITS(11,10) // A64: BTYPE
1.14 skrll 901: #define SPSR_A64_D __BIT(9) // A64: Debug Exception Mask
902: #define SPSR_A32_E __BIT(9) // A32: BE Endian Mode
903: #define SPSR_A __BIT(8) // Async abort (SError) Mask
904: #define SPSR_I __BIT(7) // IRQ Mask
905: #define SPSR_F __BIT(6) // FIQ Mask
906: #define SPSR_A32_T __BIT(5) // A32 Thumb Mode
1.19 ryo 907: #define SPSR_A32 __BIT(4) // A32 Mode (a part of SPSR_M)
1.14 skrll 908: #define SPSR_M __BITS(4,0) // Execution State
909: #define SPSR_M_EL3H 0x0d
910: #define SPSR_M_EL3T 0x0c
911: #define SPSR_M_EL2H 0x09
912: #define SPSR_M_EL2T 0x08
913: #define SPSR_M_EL1H 0x05
914: #define SPSR_M_EL1T 0x04
915: #define SPSR_M_EL0T 0x00
916: #define SPSR_M_SYS32 0x1f
917: #define SPSR_M_UND32 0x1b
918: #define SPSR_M_ABT32 0x17
919: #define SPSR_M_SVC32 0x13
920: #define SPSR_M_IRQ32 0x12
921: #define SPSR_M_FIQ32 0x11
922: #define SPSR_M_USR32 0x10
1.1 matt 923:
924: AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register
925: AARCH64REG_WRITE_INLINE(tcr_el1)
926:
1.27 skrll 927:
928: /* TCR_EL1 - Translation Control Register */
1.47 ryo 929: #define TCR_TCMA1 __BIT(58) /* ARMv8.5-MemTag control when ADDR[59:55] = 0b11111 */
930: #define TCR_TCMA0 __BIT(57) /* ARMv8.5-MemTag control when ADDR[59:55] = 0b00000 */
931: #define TCR_E0PD1 __BIT(56) /* ARMv8.5-E0PD Faulting control for EL0 by TTBR1 */
932: #define TCR_E0PD0 __BIT(55) /* ARMv8.5-E0PD Faulting control for EL0 by TTBR0 */
933: #define TCR_NFD1 __BIT(54) /* SVE Non-fault translation table walk disable (TTBR1) */
934: #define TCR_NFD0 __BIT(53) /* SVE Non-fault translation table walk disable (TTBR0) */
935: #define TCR_TBID1 __BIT(52) /* ARMv8.3-PAuth TBI for instruction addr (TTBR1) */
936: #define TCR_TBID0 __BIT(51) /* ARMv8.3-PAuth TBI for instruction addr (TTBR0) */
937: #define TCR_HWU162 __BIT(50) /* ARMv8.1-TTPBHA bit[62] of PTE (TTBR1) */
938: #define TCR_HWU161 __BIT(49) /* ARMv8.1-TTPBHA bit[61] of PTE (TTBR1) */
939: #define TCR_HWU160 __BIT(48) /* ARMv8.1-TTPBHA bit[60] of PTE (TTBR1) */
940: #define TCR_HWU159 __BIT(47) /* ARMv8.1-TTPBHA bit[59] of PTE (TTBR1) */
941: #define TCR_HWU062 __BIT(46) /* ARMv8.1-TTPBHA bit[62] of PTE (TTBR0) */
942: #define TCR_HWU061 __BIT(45) /* ARMv8.1-TTPBHA bit[61] of PTE (TTBR0) */
943: #define TCR_HWU060 __BIT(44) /* ARMv8.1-TTPBHA bit[60] of PTE (TTBR0) */
944: #define TCR_HWU059 __BIT(43) /* ARMv8.1-TTPBHA bit[59] of PTE (TTBR0) */
945: #define TCR_HPD1 __BIT(42) /* ARMv8.1-HPD Hierarchical Permission (TTBR1) */
946: #define TCR_HPD0 __BIT(41) /* ARMv8.1-HPD Hierarchical Permission (TTBR0) */
947: #define TCR_HD __BIT(40) /* ARMv8.1-TTHM Hardware Dirty flag */
948: #define TCR_HA __BIT(39) /* ARMv8.1-TTHM Hardware Access flag */
1.27 skrll 949: #define TCR_TBI1 __BIT(38) /* ignore Top Byte TTBR1_EL1 */
950: #define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */
951: #define TCR_AS64K __BIT(36) /* Use 64K ASIDs */
952: #define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */
953: #define TCR_IPS_4PB __SHIFTIN(6,TCR_IPS) /* 52 bits ( 4 PB) */
954: #define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */
955: #define TCR_IPS_16TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */
956: #define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */
957: #define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */
958: #define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */
959: #define TCR_IPS_4GB __SHIFTIN(0,TCR_IPS) /* 32 bits (4 GB) */
960: #define TCR_TG1 __BITS(31,30) /* TTBR1 Page Granule Size */
961: #define TCR_TG1_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */
962: #define TCR_TG1_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */
963: #define TCR_TG1_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */
964: #define TCR_SH1 __BITS(29,28)
965: #define TCR_SH1_NONE __SHIFTIN(0,TCR_SH1)
966: #define TCR_SH1_OUTER __SHIFTIN(2,TCR_SH1)
967: #define TCR_SH1_INNER __SHIFTIN(3,TCR_SH1)
968: #define TCR_ORGN1 __BITS(27,26) /* TTBR1 Outer cacheability */
969: #define TCR_ORGN1_NC __SHIFTIN(0,TCR_ORGN1) /* Non Cacheable */
970: #define TCR_ORGN1_WB_WA __SHIFTIN(1,TCR_ORGN1) /* WriteBack WriteAllocate */
971: #define TCR_ORGN1_WT __SHIFTIN(2,TCR_ORGN1) /* WriteThrough */
972: #define TCR_ORGN1_WB __SHIFTIN(3,TCR_ORGN1) /* WriteBack */
973: #define TCR_IRGN1 __BITS(25,24) /* TTBR1 Inner cacheability */
974: #define TCR_IRGN1_NC __SHIFTIN(0,TCR_IRGN1) /* Non Cacheable */
975: #define TCR_IRGN1_WB_WA __SHIFTIN(1,TCR_IRGN1) /* WriteBack WriteAllocate */
976: #define TCR_IRGN1_WT __SHIFTIN(2,TCR_IRGN1) /* WriteThrough */
977: #define TCR_IRGN1_WB __SHIFTIN(3,TCR_IRGN1) /* WriteBack */
978: #define TCR_EPD1 __BIT(23) /* Walk Disable for TTBR1_EL1 */
979: #define TCR_A1 __BIT(22) /* ASID is in TTBR1_EL1 */
980: #define TCR_T1SZ __BITS(21,16) /* Size offset for TTBR1_EL1 */
981: #define TCR_TG0 __BITS(15,14) /* TTBR0 Page Granule Size */
982: #define TCR_TG0_4KB __SHIFTIN(0,TCR_TG0) /* 4KB page size */
983: #define TCR_TG0_64KB __SHIFTIN(1,TCR_TG0) /* 64KB page size */
984: #define TCR_TG0_16KB __SHIFTIN(2,TCR_TG0) /* 16KB page size */
985: #define TCR_SH0 __BITS(13,12)
986: #define TCR_SH0_NONE __SHIFTIN(0,TCR_SH0)
987: #define TCR_SH0_OUTER __SHIFTIN(2,TCR_SH0)
988: #define TCR_SH0_INNER __SHIFTIN(3,TCR_SH0)
989: #define TCR_ORGN0 __BITS(11,10) /* TTBR0 Outer cacheability */
990: #define TCR_ORGN0_NC __SHIFTIN(0,TCR_ORGN0) /* Non Cacheable */
991: #define TCR_ORGN0_WB_WA __SHIFTIN(1,TCR_ORGN0) /* WriteBack WriteAllocate */
992: #define TCR_ORGN0_WT __SHIFTIN(2,TCR_ORGN0) /* WriteThrough */
993: #define TCR_ORGN0_WB __SHIFTIN(3,TCR_ORGN0) /* WriteBack */
994: #define TCR_IRGN0 __BITS(9,8) /* TTBR0 Inner cacheability */
995: #define TCR_IRGN0_NC __SHIFTIN(0,TCR_IRGN0) /* Non Cacheable */
996: #define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */
997: #define TCR_IRGN0_WT __SHIFTIN(2,TCR_IRGN0) /* WriteThrough */
998: #define TCR_IRGN0_WB __SHIFTIN(3,TCR_IRGN0) /* WriteBack */
999: #define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */
1000: #define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */
1.1 matt 1001:
1002: AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1)
1003: AARCH64REG_WRITE_INLINE(tpidr_el1)
1004:
1005: AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0)
1006:
1.9 ryo 1007: AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL1
1.1 matt 1008: AARCH64REG_WRITE_INLINE(ttbr0_el1)
1009:
1.9 ryo 1010: AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1
1.1 matt 1011: AARCH64REG_WRITE_INLINE(ttbr1_el1)
1012:
1.27 skrll 1013: #define TTBR_ASID __BITS(63,48)
1014: #define TTBR_BADDR __BITS(47,0)
1015:
1.1 matt 1016: AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register
1017: AARCH64REG_WRITE_INLINE(vbar_el1)
1018:
1.9 ryo 1019: /*
1020: * From here on, these are DEBUG registers
1021: */
1022: AARCH64REG_READ_INLINE(dbgbcr0_el1) // Debug Breakpoint Control Register 0
1023: AARCH64REG_WRITE_INLINE(dbgbcr0_el1)
1024: AARCH64REG_READ_INLINE(dbgbcr1_el1) // Debug Breakpoint Control Register 1
1025: AARCH64REG_WRITE_INLINE(dbgbcr1_el1)
1026: AARCH64REG_READ_INLINE(dbgbcr2_el1) // Debug Breakpoint Control Register 2
1027: AARCH64REG_WRITE_INLINE(dbgbcr2_el1)
1028: AARCH64REG_READ_INLINE(dbgbcr3_el1) // Debug Breakpoint Control Register 3
1029: AARCH64REG_WRITE_INLINE(dbgbcr3_el1)
1030: AARCH64REG_READ_INLINE(dbgbcr4_el1) // Debug Breakpoint Control Register 4
1031: AARCH64REG_WRITE_INLINE(dbgbcr4_el1)
1032: AARCH64REG_READ_INLINE(dbgbcr5_el1) // Debug Breakpoint Control Register 5
1033: AARCH64REG_WRITE_INLINE(dbgbcr5_el1)
1034: AARCH64REG_READ_INLINE(dbgbcr6_el1) // Debug Breakpoint Control Register 6
1035: AARCH64REG_WRITE_INLINE(dbgbcr6_el1)
1036: AARCH64REG_READ_INLINE(dbgbcr7_el1) // Debug Breakpoint Control Register 7
1037: AARCH64REG_WRITE_INLINE(dbgbcr7_el1)
1038: AARCH64REG_READ_INLINE(dbgbcr8_el1) // Debug Breakpoint Control Register 8
1039: AARCH64REG_WRITE_INLINE(dbgbcr8_el1)
1040: AARCH64REG_READ_INLINE(dbgbcr9_el1) // Debug Breakpoint Control Register 9
1041: AARCH64REG_WRITE_INLINE(dbgbcr9_el1)
1042: AARCH64REG_READ_INLINE(dbgbcr10_el1) // Debug Breakpoint Control Register 10
1043: AARCH64REG_WRITE_INLINE(dbgbcr10_el1)
1044: AARCH64REG_READ_INLINE(dbgbcr11_el1) // Debug Breakpoint Control Register 11
1045: AARCH64REG_WRITE_INLINE(dbgbcr11_el1)
1046: AARCH64REG_READ_INLINE(dbgbcr12_el1) // Debug Breakpoint Control Register 12
1047: AARCH64REG_WRITE_INLINE(dbgbcr12_el1)
1048: AARCH64REG_READ_INLINE(dbgbcr13_el1) // Debug Breakpoint Control Register 13
1049: AARCH64REG_WRITE_INLINE(dbgbcr13_el1)
1050: AARCH64REG_READ_INLINE(dbgbcr14_el1) // Debug Breakpoint Control Register 14
1051: AARCH64REG_WRITE_INLINE(dbgbcr14_el1)
1052: AARCH64REG_READ_INLINE(dbgbcr15_el1) // Debug Breakpoint Control Register 15
1053: AARCH64REG_WRITE_INLINE(dbgbcr15_el1)
1054:
1.14 skrll 1055: #define DBGBCR_BT __BITS(23,20)
1056: #define DBGBCR_LBN __BITS(19,16)
1057: #define DBGBCR_SSC __BITS(15,14)
1058: #define DBGBCR_HMC __BIT(13)
1059: #define DBGBCR_BAS __BITS(8,5)
1060: #define DBGBCR_PMC __BITS(2,1)
1061: #define DBGBCR_E __BIT(0)
1.9 ryo 1062:
1063: AARCH64REG_READ_INLINE(dbgbvr0_el1) // Debug Breakpoint Value Register 0
1064: AARCH64REG_WRITE_INLINE(dbgbvr0_el1)
1065: AARCH64REG_READ_INLINE(dbgbvr1_el1) // Debug Breakpoint Value Register 1
1066: AARCH64REG_WRITE_INLINE(dbgbvr1_el1)
1067: AARCH64REG_READ_INLINE(dbgbvr2_el1) // Debug Breakpoint Value Register 2
1068: AARCH64REG_WRITE_INLINE(dbgbvr2_el1)
1069: AARCH64REG_READ_INLINE(dbgbvr3_el1) // Debug Breakpoint Value Register 3
1070: AARCH64REG_WRITE_INLINE(dbgbvr3_el1)
1071: AARCH64REG_READ_INLINE(dbgbvr4_el1) // Debug Breakpoint Value Register 4
1072: AARCH64REG_WRITE_INLINE(dbgbvr4_el1)
1073: AARCH64REG_READ_INLINE(dbgbvr5_el1) // Debug Breakpoint Value Register 5
1074: AARCH64REG_WRITE_INLINE(dbgbvr5_el1)
1075: AARCH64REG_READ_INLINE(dbgbvr6_el1) // Debug Breakpoint Value Register 6
1076: AARCH64REG_WRITE_INLINE(dbgbvr6_el1)
1077: AARCH64REG_READ_INLINE(dbgbvr7_el1) // Debug Breakpoint Value Register 7
1078: AARCH64REG_WRITE_INLINE(dbgbvr7_el1)
1079: AARCH64REG_READ_INLINE(dbgbvr8_el1) // Debug Breakpoint Value Register 8
1080: AARCH64REG_WRITE_INLINE(dbgbvr8_el1)
1081: AARCH64REG_READ_INLINE(dbgbvr9_el1) // Debug Breakpoint Value Register 9
1082: AARCH64REG_WRITE_INLINE(dbgbvr9_el1)
1083: AARCH64REG_READ_INLINE(dbgbvr10_el1) // Debug Breakpoint Value Register 10
1084: AARCH64REG_WRITE_INLINE(dbgbvr10_el1)
1085: AARCH64REG_READ_INLINE(dbgbvr11_el1) // Debug Breakpoint Value Register 11
1086: AARCH64REG_WRITE_INLINE(dbgbvr11_el1)
1087: AARCH64REG_READ_INLINE(dbgbvr12_el1) // Debug Breakpoint Value Register 12
1088: AARCH64REG_WRITE_INLINE(dbgbvr12_el1)
1089: AARCH64REG_READ_INLINE(dbgbvr13_el1) // Debug Breakpoint Value Register 13
1090: AARCH64REG_WRITE_INLINE(dbgbvr13_el1)
1091: AARCH64REG_READ_INLINE(dbgbvr14_el1) // Debug Breakpoint Value Register 14
1092: AARCH64REG_WRITE_INLINE(dbgbvr14_el1)
1093: AARCH64REG_READ_INLINE(dbgbvr15_el1) // Debug Breakpoint Value Register 15
1094: AARCH64REG_WRITE_INLINE(dbgbvr15_el1)
1095:
1.55 ryo 1096: #define DBGBVR_MASK __BITS(63,2)
1097:
1.9 ryo 1098: AARCH64REG_READ_INLINE(dbgwcr0_el1) // Debug Watchpoint Control Register 0
1099: AARCH64REG_WRITE_INLINE(dbgwcr0_el1)
1100: AARCH64REG_READ_INLINE(dbgwcr1_el1) // Debug Watchpoint Control Register 1
1101: AARCH64REG_WRITE_INLINE(dbgwcr1_el1)
1102: AARCH64REG_READ_INLINE(dbgwcr2_el1) // Debug Watchpoint Control Register 2
1103: AARCH64REG_WRITE_INLINE(dbgwcr2_el1)
1104: AARCH64REG_READ_INLINE(dbgwcr3_el1) // Debug Watchpoint Control Register 3
1105: AARCH64REG_WRITE_INLINE(dbgwcr3_el1)
1106: AARCH64REG_READ_INLINE(dbgwcr4_el1) // Debug Watchpoint Control Register 4
1107: AARCH64REG_WRITE_INLINE(dbgwcr4_el1)
1108: AARCH64REG_READ_INLINE(dbgwcr5_el1) // Debug Watchpoint Control Register 5
1109: AARCH64REG_WRITE_INLINE(dbgwcr5_el1)
1110: AARCH64REG_READ_INLINE(dbgwcr6_el1) // Debug Watchpoint Control Register 6
1111: AARCH64REG_WRITE_INLINE(dbgwcr6_el1)
1112: AARCH64REG_READ_INLINE(dbgwcr7_el1) // Debug Watchpoint Control Register 7
1113: AARCH64REG_WRITE_INLINE(dbgwcr7_el1)
1114: AARCH64REG_READ_INLINE(dbgwcr8_el1) // Debug Watchpoint Control Register 8
1115: AARCH64REG_WRITE_INLINE(dbgwcr8_el1)
1116: AARCH64REG_READ_INLINE(dbgwcr9_el1) // Debug Watchpoint Control Register 9
1117: AARCH64REG_WRITE_INLINE(dbgwcr9_el1)
1118: AARCH64REG_READ_INLINE(dbgwcr10_el1) // Debug Watchpoint Control Register 10
1119: AARCH64REG_WRITE_INLINE(dbgwcr10_el1)
1120: AARCH64REG_READ_INLINE(dbgwcr11_el1) // Debug Watchpoint Control Register 11
1121: AARCH64REG_WRITE_INLINE(dbgwcr11_el1)
1122: AARCH64REG_READ_INLINE(dbgwcr12_el1) // Debug Watchpoint Control Register 12
1123: AARCH64REG_WRITE_INLINE(dbgwcr12_el1)
1124: AARCH64REG_READ_INLINE(dbgwcr13_el1) // Debug Watchpoint Control Register 13
1125: AARCH64REG_WRITE_INLINE(dbgwcr13_el1)
1126: AARCH64REG_READ_INLINE(dbgwcr14_el1) // Debug Watchpoint Control Register 14
1127: AARCH64REG_WRITE_INLINE(dbgwcr14_el1)
1128: AARCH64REG_READ_INLINE(dbgwcr15_el1) // Debug Watchpoint Control Register 15
1129: AARCH64REG_WRITE_INLINE(dbgwcr15_el1)
1130:
1.14 skrll 1131: #define DBGWCR_MASK __BITS(28,24)
1132: #define DBGWCR_WT __BIT(20)
1133: #define DBGWCR_LBN __BITS(19,16)
1134: #define DBGWCR_SSC __BITS(15,14)
1135: #define DBGWCR_HMC __BIT(13)
1136: #define DBGWCR_BAS __BITS(12,5)
1137: #define DBGWCR_LSC __BITS(4,3)
1138: #define DBGWCR_PAC __BITS(2,1)
1139: #define DBGWCR_E __BIT(0)
1.9 ryo 1140:
1141: AARCH64REG_READ_INLINE(dbgwvr0_el1) // Debug Watchpoint Value Register 0
1142: AARCH64REG_WRITE_INLINE(dbgwvr0_el1)
1143: AARCH64REG_READ_INLINE(dbgwvr1_el1) // Debug Watchpoint Value Register 1
1144: AARCH64REG_WRITE_INLINE(dbgwvr1_el1)
1145: AARCH64REG_READ_INLINE(dbgwvr2_el1) // Debug Watchpoint Value Register 2
1146: AARCH64REG_WRITE_INLINE(dbgwvr2_el1)
1147: AARCH64REG_READ_INLINE(dbgwvr3_el1) // Debug Watchpoint Value Register 3
1148: AARCH64REG_WRITE_INLINE(dbgwvr3_el1)
1149: AARCH64REG_READ_INLINE(dbgwvr4_el1) // Debug Watchpoint Value Register 4
1150: AARCH64REG_WRITE_INLINE(dbgwvr4_el1)
1151: AARCH64REG_READ_INLINE(dbgwvr5_el1) // Debug Watchpoint Value Register 5
1152: AARCH64REG_WRITE_INLINE(dbgwvr5_el1)
1153: AARCH64REG_READ_INLINE(dbgwvr6_el1) // Debug Watchpoint Value Register 6
1154: AARCH64REG_WRITE_INLINE(dbgwvr6_el1)
1155: AARCH64REG_READ_INLINE(dbgwvr7_el1) // Debug Watchpoint Value Register 7
1156: AARCH64REG_WRITE_INLINE(dbgwvr7_el1)
1157: AARCH64REG_READ_INLINE(dbgwvr8_el1) // Debug Watchpoint Value Register 8
1158: AARCH64REG_WRITE_INLINE(dbgwvr8_el1)
1159: AARCH64REG_READ_INLINE(dbgwvr9_el1) // Debug Watchpoint Value Register 9
1160: AARCH64REG_WRITE_INLINE(dbgwvr9_el1)
1161: AARCH64REG_READ_INLINE(dbgwvr10_el1) // Debug Watchpoint Value Register 10
1162: AARCH64REG_WRITE_INLINE(dbgwvr10_el1)
1163: AARCH64REG_READ_INLINE(dbgwvr11_el1) // Debug Watchpoint Value Register 11
1164: AARCH64REG_WRITE_INLINE(dbgwvr11_el1)
1165: AARCH64REG_READ_INLINE(dbgwvr12_el1) // Debug Watchpoint Value Register 12
1166: AARCH64REG_WRITE_INLINE(dbgwvr12_el1)
1167: AARCH64REG_READ_INLINE(dbgwvr13_el1) // Debug Watchpoint Value Register 13
1168: AARCH64REG_WRITE_INLINE(dbgwvr13_el1)
1169: AARCH64REG_READ_INLINE(dbgwvr14_el1) // Debug Watchpoint Value Register 14
1170: AARCH64REG_WRITE_INLINE(dbgwvr14_el1)
1171: AARCH64REG_READ_INLINE(dbgwvr15_el1) // Debug Watchpoint Value Register 15
1172: AARCH64REG_WRITE_INLINE(dbgwvr15_el1)
1173:
1.55 ryo 1174: #define DBGWVR_MASK __BITS(63,2)
1.9 ryo 1175:
1176:
1177: AARCH64REG_READ_INLINE(mdscr_el1) // Monitor Debug System Control Register
1178: AARCH64REG_WRITE_INLINE(mdscr_el1)
1179:
1.22 ryo 1180: #define MDSCR_RXFULL __BIT(30) // for EDSCR.RXfull
1181: #define MDSCR_TXFULL __BIT(29) // for EDSCR.TXfull
1182: #define MDSCR_RXO __BIT(27) // for EDSCR.RXO
1183: #define MDSCR_TXU __BIT(26) // for EDSCR.TXU
1184: #define MDSCR_INTDIS __BITS(32,22) // for EDSCR.INTdis
1185: #define MDSCR_TDA __BIT(21) // for EDSCR.TDA
1186: #define MDSCR_MDE __BIT(15) // Monitor debug events
1187: #define MDSCR_HDE __BIT(14) // for EDSCR.HDE
1188: #define MDSCR_KDE __BIT(13) // Local debug enable
1189: #define MDSCR_TDCC __BIT(12) // Trap Debug CommCh access
1190: #define MDSCR_ERR __BIT(6) // for EDSCR.ERR
1191: #define MDSCR_SS __BIT(0) // Software step
1192:
1.9 ryo 1193: AARCH64REG_WRITE_INLINE(oslar_el1) // OS Lock Access Register
1194:
1195: AARCH64REG_READ_INLINE(oslsr_el1) // OS Lock Status Register
1196:
1197: /*
1198: * From here on, these are PMC registers
1199: */
1200:
1.1 matt 1201: AARCH64REG_READ_INLINE(pmccfiltr_el0)
1202: AARCH64REG_WRITE_INLINE(pmccfiltr_el0)
1203:
1.14 skrll 1204: #define PMCCFILTR_P __BIT(31) // Don't count cycles in EL1
1205: #define PMCCFILTR_U __BIT(30) // Don't count cycles in EL0
1206: #define PMCCFILTR_NSK __BIT(29) // Don't count cycles in NS EL1
1207: #define PMCCFILTR_NSU __BIT(28) // Don't count cycles in NS EL0
1208: #define PMCCFILTR_NSH __BIT(27) // Don't count cycles in NS EL2
1209: #define PMCCFILTR_M __BIT(26) // Don't count cycles in EL3
1.1 matt 1210:
1211: AARCH64REG_READ_INLINE(pmccntr_el0)
1212:
1.12 christos 1213: AARCH64REG_READ_INLINE(pmceid0_el0)
1214: AARCH64REG_READ_INLINE(pmceid1_el0)
1.11 jmcneill 1215:
1.12 christos 1216: AARCH64REG_WRITE_INLINE(pmcntenclr_el0)
1217: AARCH64REG_WRITE_INLINE(pmcntenset_el0)
1.11 jmcneill 1218:
1.39 jmcneill 1219: #define PMCNTEN_C __BIT(31) // Enable the cycle counter
1220: #define PMCNTEN_P __BITS(30,0) // Enable event counter bits
1221:
1.11 jmcneill 1222: AARCH64REG_READ_INLINE(pmcr_el0)
1223: AARCH64REG_WRITE_INLINE(pmcr_el0)
1224:
1.14 skrll 1225: #define PMCR_IMP __BITS(31,24) // Implementor code
1226: #define PMCR_IDCODE __BITS(23,16) // Identification code
1227: #define PMCR_N __BITS(15,11) // Number of event counters
1.63 ! ryo 1228: #define PMCR_LP __BIT(7) // Long event counter enable
1.14 skrll 1229: #define PMCR_LC __BIT(6) // Long cycle counter enable
1230: #define PMCR_DP __BIT(5) // Disable cycle counter when event
1231: // counting is prohibited
1232: #define PMCR_X __BIT(4) // Enable export of events
1233: #define PMCR_D __BIT(3) // Clock divider
1234: #define PMCR_C __BIT(2) // Cycle counter reset
1235: #define PMCR_P __BIT(1) // Event counter reset
1236: #define PMCR_E __BIT(0) // Enable
1.11 jmcneill 1237:
1238:
1.12 christos 1239: AARCH64REG_READ_INLINE(pmevcntr1_el0)
1240: AARCH64REG_WRITE_INLINE(pmevcntr1_el0)
1.11 jmcneill 1241:
1242: AARCH64REG_READ_INLINE(pmevtyper1_el0)
1243: AARCH64REG_WRITE_INLINE(pmevtyper1_el0)
1244:
1.14 skrll 1245: #define PMEVTYPER_P __BIT(31) // Don't count events in EL1
1246: #define PMEVTYPER_U __BIT(30) // Don't count events in EL0
1247: #define PMEVTYPER_NSK __BIT(29) // Don't count events in NS EL1
1248: #define PMEVTYPER_NSU __BIT(28) // Don't count events in NS EL0
1249: #define PMEVTYPER_NSH __BIT(27) // Count events in NS EL2
1250: #define PMEVTYPER_M __BIT(26) // Don't count events in EL3
1251: #define PMEVTYPER_MT __BIT(25) // Count events on all CPUs with same
1252: // aff1 level
1253: #define PMEVTYPER_EVTCOUNT __BITS(15,0) // Event to count
1.11 jmcneill 1254:
1.12 christos 1255: AARCH64REG_WRITE_INLINE(pmintenclr_el1)
1256: AARCH64REG_WRITE_INLINE(pmintenset_el1)
1.11 jmcneill 1257:
1.62 ryo 1258: #define PMINTEN_C __BIT(31) // for the cycle counter
1259: #define PMINTEN_P __BITS(30,0) // for event counters (0-30)
1260:
1.12 christos 1261: AARCH64REG_WRITE_INLINE(pmovsclr_el0)
1262: AARCH64REG_READ_INLINE(pmovsset_el0)
1263: AARCH64REG_WRITE_INLINE(pmovsset_el0)
1.11 jmcneill 1264:
1.62 ryo 1265: #define PMOVS_C __BIT(31) // for the cycle counter
1266: #define PMOVS_P __BITS(30,0) // for event counters (0-30)
1267:
1.12 christos 1268: AARCH64REG_WRITE_INLINE(pmselr_el0)
1.11 jmcneill 1269:
1.12 christos 1270: AARCH64REG_WRITE_INLINE(pmswinc_el0)
1.11 jmcneill 1271:
1.12 christos 1272: AARCH64REG_READ_INLINE(pmuserenr_el0)
1273: AARCH64REG_WRITE_INLINE(pmuserenr_el0)
1.11 jmcneill 1274:
1.12 christos 1275: AARCH64REG_READ_INLINE(pmxevcntr_el0)
1276: AARCH64REG_WRITE_INLINE(pmxevcntr_el0)
1.11 jmcneill 1277:
1.12 christos 1278: AARCH64REG_READ_INLINE(pmxevtyper_el0)
1279: AARCH64REG_WRITE_INLINE(pmxevtyper_el0)
1.11 jmcneill 1280:
1281: /*
1282: * Generic timer registers
1283: */
1284:
1.1 matt 1285: AARCH64REG_READ_INLINE(cntfrq_el0)
1286:
1.9 ryo 1287: AARCH64REG_READ_INLINE(cnthctl_el2)
1288: AARCH64REG_WRITE_INLINE(cnthctl_el2)
1289:
1.14 skrll 1290: #define CNTHCTL_EVNTDIR __BIT(3)
1291: #define CNTHCTL_EVNTEN __BIT(2)
1292: #define CNTHCTL_EL1PCEN __BIT(1)
1293: #define CNTHCTL_EL1PCTEN __BIT(0)
1.9 ryo 1294:
1.1 matt 1295: AARCH64REG_READ_INLINE(cntkctl_el1)
1296: AARCH64REG_WRITE_INLINE(cntkctl_el1)
1297:
1.14 skrll 1298: #define CNTKCTL_EL0PTEN __BIT(9) // EL0 access for CNTP CVAL/TVAL/CTL
1299: #define CNTKCTL_PL0PTEN CNTKCTL_EL0PTEN
1300: #define CNTKCTL_EL0VTEN __BIT(8) // EL0 access for CNTV CVAL/TVAL/CTL
1301: #define CNTKCTL_PL0VTEN CNTKCTL_EL0VTEN
1302: #define CNTKCTL_ELNTI __BITS(7,4)
1303: #define CNTKCTL_EVNTDIR __BIT(3)
1304: #define CNTKCTL_EVNTEN __BIT(2)
1305: #define CNTKCTL_EL0VCTEN __BIT(1) // EL0 access for CNTVCT and CNTFRQ
1306: #define CNTKCTL_PL0VCTEN CNTKCTL_EL0VCTEN
1307: #define CNTKCTL_EL0PCTEN __BIT(0) // EL0 access for CNTPCT and CNTFRQ
1308: #define CNTKCTL_PL0PCTEN CNTKCTL_EL0PCTEN
1.1 matt 1309:
1310: AARCH64REG_READ_INLINE(cntp_ctl_el0)
1311: AARCH64REG_WRITE_INLINE(cntp_ctl_el0)
1312: AARCH64REG_READ_INLINE(cntp_cval_el0)
1313: AARCH64REG_WRITE_INLINE(cntp_cval_el0)
1314: AARCH64REG_READ_INLINE(cntp_tval_el0)
1315: AARCH64REG_WRITE_INLINE(cntp_tval_el0)
1316: AARCH64REG_READ_INLINE(cntpct_el0)
1317: AARCH64REG_WRITE_INLINE(cntpct_el0)
1318:
1319: AARCH64REG_READ_INLINE(cntps_ctl_el1)
1320: AARCH64REG_WRITE_INLINE(cntps_ctl_el1)
1321: AARCH64REG_READ_INLINE(cntps_cval_el1)
1322: AARCH64REG_WRITE_INLINE(cntps_cval_el1)
1323: AARCH64REG_READ_INLINE(cntps_tval_el1)
1324: AARCH64REG_WRITE_INLINE(cntps_tval_el1)
1325:
1326: AARCH64REG_READ_INLINE(cntv_ctl_el0)
1327: AARCH64REG_WRITE_INLINE(cntv_ctl_el0)
1328: AARCH64REG_READ_INLINE(cntv_cval_el0)
1329: AARCH64REG_WRITE_INLINE(cntv_cval_el0)
1330: AARCH64REG_READ_INLINE(cntv_tval_el0)
1331: AARCH64REG_WRITE_INLINE(cntv_tval_el0)
1332: AARCH64REG_READ_INLINE(cntvct_el0)
1333: AARCH64REG_WRITE_INLINE(cntvct_el0)
1334:
1.14 skrll 1335: #define CNTCTL_ISTATUS __BIT(2) // Interrupt Asserted
1336: #define CNTCTL_IMASK __BIT(1) // Timer Interrupt is Masked
1337: #define CNTCTL_ENABLE __BIT(0) // Timer Enabled
1.1 matt 1338:
1.9 ryo 1339: // ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0
1.49 riastrad 1340: #define ID_AA64PFR0_EL1_CSV3 __BITS(63,60) // Speculative fault data
1341: #define ID_AA64PFR0_EL1_CSV3_NONE 0
1342: #define ID_AA64PFR0_EL1_CSV3_IMPL 1
1343: #define ID_AA64PFR0_EL1_CSV2 __BITS(59,56) // Speculative branches
1344: #define ID_AA64PFR0_EL1_CSV2_NONE 0
1345: #define ID_AA64PFR0_EL1_CSV2_IMPL 1
1346: // reserved [55:52]
1347: #define ID_AA64PFR0_EL1_DIT __BITS(51,48) // Data-indep. timing
1348: #define ID_AA64PFR0_EL1_DIT_NONE 0
1349: #define ID_AA64PFR0_EL1_DIT_IMPL 1
1350: #define ID_AA64PFR0_EL1_AMU __BITS(47,44) // Activity monitors ext.
1351: #define ID_AA64PFR0_EL1_AMU_NONE 0
1352: #define ID_AA64PFR0_EL1_AMU_IMPLv8_4 1
1353: #define ID_AA64PFR0_EL1_AMU_IMPLv8_6 2
1354: #define ID_AA64PFR0_EL1_MPAM __BITS(43,40) // MPAM Extension
1355: #define ID_AA64PFR0_EL1_MPAM_NONE 0
1356: #define ID_AA64PFR0_EL1_MPAM_IMPL 1
1357: #define ID_AA64PFR0_EL1_SEL2 __BITS(43,40) // Secure EL2
1358: #define ID_AA64PFR0_EL1_SEL2_NONE 0
1359: #define ID_AA64PFR0_EL1_SEL2_IMPL 1
1.37 ryo 1360: #define ID_AA64PFR0_EL1_SVE __BITS(35,32) // Scalable Vector
1361: #define ID_AA64PFR0_EL1_SVE_NONE 0
1362: #define ID_AA64PFR0_EL1_SVE_IMPL 1
1363: #define ID_AA64PFR0_EL1_RAS __BITS(31,28) // RAS Extension
1364: #define ID_AA64PFR0_EL1_RAS_NONE 0
1365: #define ID_AA64PFR0_EL1_RAS_IMPL 1
1366: #define ID_AA64PFR0_EL1_RAS_ERX 2
1.12 christos 1367: #define ID_AA64PFR0_EL1_GIC __BITS(24,27) // GIC CPU IF
1368: #define ID_AA64PFR0_EL1_GIC_SHIFT 24
1.14 skrll 1369: #define ID_AA64PFR0_EL1_GIC_CPUIF_EN 1
1370: #define ID_AA64PFR0_EL1_GIC_CPUIF_NONE 0
1.12 christos 1371: #define ID_AA64PFR0_EL1_ADVSIMD __BITS(23,20) // SIMD
1.14 skrll 1372: #define ID_AA64PFR0_EL1_ADV_SIMD_IMPL 0x0
1.37 ryo 1373: #define ID_AA64PFR0_EL1_ADV_SIMD_HP 0x1
1.14 skrll 1374: #define ID_AA64PFR0_EL1_ADV_SIMD_NONE 0xf
1.12 christos 1375: #define ID_AA64PFR0_EL1_FP __BITS(19,16) // FP
1.14 skrll 1376: #define ID_AA64PFR0_EL1_FP_IMPL 0x0
1.37 ryo 1377: #define ID_AA64PFR0_EL1_FP_HP 0x1
1.14 skrll 1378: #define ID_AA64PFR0_EL1_FP_NONE 0xf
1.12 christos 1379: #define ID_AA64PFR0_EL1_EL3 __BITS(15,12) // EL3 handling
1.14 skrll 1380: #define ID_AA64PFR0_EL1_EL3_NONE 0
1381: #define ID_AA64PFR0_EL1_EL3_64 1
1382: #define ID_AA64PFR0_EL1_EL3_64_32 2
1.12 christos 1383: #define ID_AA64PFR0_EL1_EL2 __BITS(11,8) // EL2 handling
1.14 skrll 1384: #define ID_AA64PFR0_EL1_EL2_NONE 0
1385: #define ID_AA64PFR0_EL1_EL2_64 1
1386: #define ID_AA64PFR0_EL1_EL2_64_32 2
1.12 christos 1387: #define ID_AA64PFR0_EL1_EL1 __BITS(7,4) // EL1 handling
1.14 skrll 1388: #define ID_AA64PFR0_EL1_EL1_64 1
1389: #define ID_AA64PFR0_EL1_EL1_64_32 2
1.12 christos 1390: #define ID_AA64PFR0_EL1_EL0 __BITS(3,0) // EL0 handling
1.14 skrll 1391: #define ID_AA64PFR0_EL1_EL0_64 1
1392: #define ID_AA64PFR0_EL1_EL0_64_32 2
1.9 ryo 1393:
1.15 jmcneill 1394: /*
1395: * GICv3 system registers
1396: */
1397: AARCH64REG_READWRITE_INLINE2(icc_sre_el1, s3_0_c12_c12_5)
1398: AARCH64REG_READWRITE_INLINE2(icc_ctlr_el1, s3_0_c12_c12_4)
1399: AARCH64REG_READWRITE_INLINE2(icc_pmr_el1, s3_0_c4_c6_0)
1400: AARCH64REG_READWRITE_INLINE2(icc_bpr0_el1, s3_0_c12_c8_3)
1401: AARCH64REG_READWRITE_INLINE2(icc_bpr1_el1, s3_0_c12_c12_3)
1402: AARCH64REG_READWRITE_INLINE2(icc_igrpen0_el1, s3_0_c12_c12_6)
1403: AARCH64REG_READWRITE_INLINE2(icc_igrpen1_el1, s3_0_c12_c12_7)
1404: AARCH64REG_READWRITE_INLINE2(icc_eoir0_el1, s3_0_c12_c8_1)
1405: AARCH64REG_READWRITE_INLINE2(icc_eoir1_el1, s3_0_c12_c12_1)
1406: AARCH64REG_READWRITE_INLINE2(icc_sgi1r_el1, s3_0_c12_c11_5)
1407: AARCH64REG_READ_INLINE2(icc_iar1_el1, s3_0_c12_c12_0)
1408:
1.9 ryo 1409: // ICC_SRE_EL1: Interrupt Controller System Register Enable register
1.15 jmcneill 1410: #define ICC_SRE_EL1_DIB __BIT(2)
1411: #define ICC_SRE_EL1_DFB __BIT(1)
1412: #define ICC_SRE_EL1_SRE __BIT(0)
1413:
1.16 jmcneill 1414: // ICC_SRE_EL2: Interrupt Controller System Register Enable register
1415: #define ICC_SRE_EL2_EN __BIT(3)
1416: #define ICC_SRE_EL2_DIB __BIT(2)
1417: #define ICC_SRE_EL2_DFB __BIT(1)
1418: #define ICC_SRE_EL2_SRE __BIT(0)
1419:
1.15 jmcneill 1420: // ICC_BPR[01]_EL1: Interrupt Controller Binary Point Register 0/1
1421: #define ICC_BPR_EL1_BinaryPoint __BITS(2,0)
1422:
1423: // ICC_CTLR_EL1: Interrupt Controller Control Register
1424: #define ICC_CTLR_EL1_A3V __BIT(15)
1425: #define ICC_CTLR_EL1_SEIS __BIT(14)
1426: #define ICC_CTLR_EL1_IDbits __BITS(13,11)
1427: #define ICC_CTLR_EL1_PRIbits __BITS(10,8)
1428: #define ICC_CTLR_EL1_PMHE __BIT(6)
1429: #define ICC_CTLR_EL1_EOImode __BIT(1)
1430: #define ICC_CTLR_EL1_CBPR __BIT(0)
1431:
1432: // ICC_IGRPEN[01]_EL1: Interrupt Controller Interrupt Group 0/1 Enable register
1433: #define ICC_IGRPEN_EL1_Enable __BIT(0)
1434:
1435: // ICC_SGI[01]R_EL1: Interrupt Controller Software Generated Interrupt Group 0/1 Register
1436: #define ICC_SGIR_EL1_Aff3 __BITS(55,48)
1437: #define ICC_SGIR_EL1_IRM __BIT(40)
1438: #define ICC_SGIR_EL1_Aff2 __BITS(39,32)
1439: #define ICC_SGIR_EL1_INTID __BITS(27,24)
1440: #define ICC_SGIR_EL1_Aff1 __BITS(23,16)
1441: #define ICC_SGIR_EL1_TargetList __BITS(15,0)
1442: #define ICC_SGIR_EL1_Aff (ICC_SGIR_EL1_Aff3|ICC_SGIR_EL1_Aff2|ICC_SGIR_EL1_Aff1)
1443:
1444: // ICC_IAR[01]_EL1: Interrupt Controller Interrupt Acknowledge Register 0/1
1445: #define ICC_IAR_INTID __BITS(23,0)
1446: #define ICC_IAR_INTID_SPURIOUS 1023
1447:
1448: /*
1449: * GICv3 REGISTER ACCESS
1450: */
1.9 ryo 1451:
1.15 jmcneill 1452: #define icc_sre_read reg_icc_sre_el1_read
1453: #define icc_sre_write reg_icc_sre_el1_write
1.25 skrll 1454: #define icc_pmr_read reg_icc_pmr_el1_read
1.15 jmcneill 1455: #define icc_pmr_write reg_icc_pmr_el1_write
1456: #define icc_bpr0_write reg_icc_bpr0_el1_write
1457: #define icc_bpr1_write reg_icc_bpr1_el1_write
1458: #define icc_ctlr_read reg_icc_ctlr_el1_read
1459: #define icc_ctlr_write reg_icc_ctlr_el1_write
1460: #define icc_igrpen1_write reg_icc_igrpen1_el1_write
1461: #define icc_sgi1r_write reg_icc_sgi1r_el1_write
1462: #define icc_iar1_read reg_icc_iar1_el1_read
1463: #define icc_eoi1r_write reg_icc_eoir1_el1_write
1.9 ryo 1464:
1.18 skrll 1465: #if defined(_KERNEL)
1466:
1467: /*
1468: * CPU REGISTER ACCESS
1469: */
1470: static __inline register_t
1471: cpu_mpidr_aff_read(void)
1472: {
1473:
1474: return reg_mpidr_el1_read() &
1475: (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0);
1476: }
1477:
1.9 ryo 1478: /*
1479: * GENERIC TIMER REGISTER ACCESS
1480: */
1.12 christos 1481: static __inline uint32_t
1.9 ryo 1482: gtmr_cntfrq_read(void)
1483: {
1484:
1485: return reg_cntfrq_el0_read();
1486: }
1487:
1.12 christos 1488: static __inline uint32_t
1.9 ryo 1489: gtmr_cntk_ctl_read(void)
1490: {
1.1 matt 1491:
1.9 ryo 1492: return reg_cntkctl_el1_read();
1493: }
1494:
1.12 christos 1495: static __inline void
1.9 ryo 1496: gtmr_cntk_ctl_write(uint32_t val)
1497: {
1498:
1499: reg_cntkctl_el1_write(val);
1500: }
1501:
1502: /*
1503: * Counter-timer Virtual Count timer
1504: */
1.12 christos 1505: static __inline uint64_t
1.9 ryo 1506: gtmr_cntpct_read(void)
1507: {
1508:
1509: return reg_cntpct_el0_read();
1510: }
1511:
1.12 christos 1512: static __inline uint64_t
1.9 ryo 1513: gtmr_cntvct_read(void)
1514: {
1515:
1516: return reg_cntvct_el0_read();
1517: }
1518:
1519: /*
1520: * Counter-timer Virtual Timer Control register
1521: */
1.56 jmcneill 1522: static __inline uint64_t
1.9 ryo 1523: gtmr_cntv_ctl_read(void)
1524: {
1525:
1526: return reg_cntv_ctl_el0_read();
1527: }
1528:
1.12 christos 1529: static __inline void
1.56 jmcneill 1530: gtmr_cntv_ctl_write(uint64_t val)
1.9 ryo 1531: {
1532:
1533: reg_cntv_ctl_el0_write(val);
1534: }
1535:
1.26 jmcneill 1536: /*
1537: * Counter-timer Physical Timer Control register
1538: */
1539: static __inline uint32_t
1540: gtmr_cntp_ctl_read(void)
1541: {
1542:
1543: return reg_cntp_ctl_el0_read();
1544: }
1545:
1.12 christos 1546: static __inline void
1.9 ryo 1547: gtmr_cntp_ctl_write(uint32_t val)
1548: {
1549:
1550: reg_cntp_ctl_el0_write(val);
1551: }
1552:
1553: /*
1.26 jmcneill 1554: * Counter-timer Physical Timer TimerValue register
1555: */
1556: static __inline uint32_t
1557: gtmr_cntp_tval_read(void)
1558: {
1559:
1560: return reg_cntp_tval_el0_read();
1561: }
1562:
1563: static __inline void
1564: gtmr_cntp_tval_write(uint32_t val)
1565: {
1566:
1567: reg_cntp_tval_el0_write(val);
1568: }
1569:
1570: /*
1.9 ryo 1571: * Counter-timer Virtual Timer TimerValue register
1572: */
1.12 christos 1573: static __inline uint32_t
1.10 joerg 1574: gtmr_cntv_tval_read(void)
1575: {
1576:
1577: return reg_cntv_tval_el0_read();
1578: }
1579:
1.12 christos 1580: static __inline void
1.9 ryo 1581: gtmr_cntv_tval_write(uint32_t val)
1582: {
1583:
1584: reg_cntv_tval_el0_write(val);
1585: }
1586:
1.26 jmcneill 1587: /*
1588: * Counter-timer Physical Timer CompareValue register
1589: */
1590: static __inline uint64_t
1591: gtmr_cntp_cval_read(void)
1592: {
1593:
1594: return reg_cntp_cval_el0_read();
1595: }
1596:
1597: static __inline void
1598: gtmr_cntp_cval_write(uint64_t val)
1599: {
1600:
1601: reg_cntp_cval_el0_write(val);
1602: }
1.9 ryo 1603:
1604: /*
1605: * Counter-timer Virtual Timer CompareValue register
1606: */
1.12 christos 1607: static __inline uint64_t
1.9 ryo 1608: gtmr_cntv_cval_read(void)
1609: {
1610:
1611: return reg_cntv_cval_el0_read();
1612: }
1.23 jmcneill 1613:
1614: static __inline void
1615: gtmr_cntv_cval_write(uint64_t val)
1616: {
1617:
1618: reg_cntv_cval_el0_write(val);
1619: }
1.18 skrll 1620: #endif /* _KERNEL */
1.1 matt 1621:
1.21 mrg 1622: /*
1623: * Structure attached to machdep.cpuN.cpu_id sysctl node.
1624: * Always add new members to the end, and avoid arrays.
1625: */
1626: struct aarch64_sysctl_cpu_id {
1627: uint64_t ac_midr; /* Main ID Register */
1628: uint64_t ac_revidr; /* Revision ID Register */
1629: uint64_t ac_mpidr; /* Multiprocessor Affinity Register */
1630:
1631: uint64_t ac_aa64dfr0; /* A64 Debug Feature Register 0 */
1632: uint64_t ac_aa64dfr1; /* A64 Debug Feature Register 1 */
1633:
1634: uint64_t ac_aa64isar0; /* A64 Instruction Set Attribute Register 0 */
1635: uint64_t ac_aa64isar1; /* A64 Instruction Set Attribute Register 1 */
1636:
1.30 rjs 1637: uint64_t ac_aa64mmfr0; /* A64 Memory Model Feature Register 0 */
1638: uint64_t ac_aa64mmfr1; /* A64 Memory Model Feature Register 1 */
1639: uint64_t ac_aa64mmfr2; /* A64 Memory Model Feature Register 2 */
1.21 mrg 1640:
1641: uint64_t ac_aa64pfr0; /* A64 Processor Feature Register 0 */
1642: uint64_t ac_aa64pfr1; /* A64 Processor Feature Register 1 */
1643:
1644: uint64_t ac_aa64zfr0; /* A64 SVE Feature ID Register 0 */
1645:
1646: uint32_t ac_mvfr0; /* Media and VFP Feature Register 0 */
1647: uint32_t ac_mvfr1; /* Media and VFP Feature Register 1 */
1648: uint32_t ac_mvfr2; /* Media and VFP Feature Register 2 */
1.50 ryo 1649: uint32_t ac_pad;
1650:
1.58 skrll 1651: uint64_t ac_clidr; /* Cache Level ID Register */
1.50 ryo 1652: uint64_t ac_ctr; /* Cache Type Register */
1.21 mrg 1653: };
1654:
1.1 matt 1655: #endif /* _AARCH64_ARMREG_H_ */
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