Annotation of src/sys/arch/aarch64/include/armreg.h, Revision 1.32
1.32 ! maxv 1: /* $NetBSD: armreg.h,v 1.31 2020/01/28 17:23:30 maxv Exp $ */
1.1 matt 2:
3: /*-
4: * Copyright (c) 2014 The NetBSD Foundation, Inc.
5: * All rights reserved.
6: *
7: * This code is derived from software contributed to The NetBSD Foundation
8: * by Matt Thomas of 3am Software Foundry.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: *
19: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29: * POSSIBILITY OF SUCH DAMAGE.
30: */
31:
32: #ifndef _AARCH64_ARMREG_H_
33: #define _AARCH64_ARMREG_H_
34:
1.8 ryo 35: #include <arm/cputypes.h>
1.1 matt 36: #include <sys/types.h>
37:
1.7 skrll 38: #define AARCH64REG_READ_INLINE2(regname, regdesc) \
1.12 christos 39: static __inline uint64_t \
1.7 skrll 40: reg_##regname##_read(void) \
41: { \
42: uint64_t __rv; \
43: __asm __volatile("mrs %0, " #regdesc : "=r"(__rv)); \
44: return __rv; \
1.1 matt 45: }
46:
1.7 skrll 47: #define AARCH64REG_WRITE_INLINE2(regname, regdesc) \
1.12 christos 48: static __inline void \
1.7 skrll 49: reg_##regname##_write(uint64_t __val) \
50: { \
51: __asm __volatile("msr " #regdesc ", %0" :: "r"(__val)); \
1.1 matt 52: }
53:
1.7 skrll 54: #define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc) \
1.12 christos 55: static __inline void \
1.7 skrll 56: reg_##regname##_write(uint64_t __val) \
57: { \
58: __asm __volatile("msr " #regdesc ", %0" :: "n"(__val)); \
1.1 matt 59: }
60:
1.7 skrll 61: #define AARCH64REG_READ_INLINE(regname) \
1.1 matt 62: AARCH64REG_READ_INLINE2(regname, regname)
63:
1.7 skrll 64: #define AARCH64REG_WRITE_INLINE(regname) \
1.1 matt 65: AARCH64REG_WRITE_INLINE2(regname, regname)
66:
1.7 skrll 67: #define AARCH64REG_WRITEIMM_INLINE(regname) \
1.1 matt 68: AARCH64REG_WRITEIMM_INLINE2(regname, regname)
1.15 jmcneill 69:
70: #define AARCH64REG_READWRITE_INLINE2(regname, regdesc) \
71: AARCH64REG_READ_INLINE2(regname, regdesc) \
72: AARCH64REG_WRITE_INLINE2(regname, regdesc)
73:
1.24 ryo 74: #define AARCH64REG_ATWRITE_INLINE2(regname, regdesc) \
75: static __inline void \
76: reg_##regname##_write(uint64_t __val) \
77: { \
78: __asm __volatile("at " #regdesc ", %0" :: "r"(__val)); \
79: }
80:
81: #define AARCH64REG_ATWRITE_INLINE(regname) \
82: AARCH64REG_ATWRITE_INLINE2(regname, regname)
83:
1.1 matt 84: /*
85: * System registers available at EL0 (user)
86: */
87: AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register
88:
1.13 skrll 89: #define CTR_EL0_CWG_LINE __BITS(27,24) // Cacheback Writeback Granule
90: #define CTR_EL0_ERG_LINE __BITS(23,20) // Exclusives Reservation Granule
91: #define CTR_EL0_DMIN_LINE __BITS(19,16) // Dcache MIN LINE size (log2 - 2)
1.12 christos 92: #define CTR_EL0_L1IP_MASK __BITS(15,14)
1.13 skrll 93: #define CTR_EL0_L1IP_AIVIVT 1 // ASID-tagged Virtual Index, Virtual Tag
94: #define CTR_EL0_L1IP_VIPT 2 // Virtual Index, Physical Tag
95: #define CTR_EL0_L1IP_PIPT 3 // Physical Index, Physical Tag
96: #define CTR_EL0_IMIN_LINE __BITS(3,0) // Icache MIN LINE size (log2 - 2)
1.1 matt 97:
1.14 skrll 98: AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register
1.1 matt 99:
1.13 skrll 100: #define DCZID_DZP __BIT(4) // Data Zero Prohibited
101: #define DCZID_BS __BITS(3,0) // Block Size (log2 - 2)
1.1 matt 102:
1.14 skrll 103: AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register
1.1 matt 104: AARCH64REG_WRITE_INLINE(fpcr)
105:
1.13 skrll 106: #define FPCR_AHP __BIT(26) // Alternative Half Precision
107: #define FPCR_DN __BIT(25) // Default Nan Control
108: #define FPCR_FZ __BIT(24) // Flush-To-Zero
109: #define FPCR_RMODE __BITS(23,22) // Rounding Mode
110: #define FPCR_RN 0 // Round Nearest
111: #define FPCR_RP 1 // Round towards Plus infinity
112: #define FPCR_RM 2 // Round towards Minus infinity
113: #define FPCR_RZ 3 // Round towards Zero
114: #define FPCR_STRIDE __BITS(21,20)
1.20 riastrad 115: #define FPCR_FZ16 __BIT(19) // Flush-To-Zero for FP16
1.13 skrll 116: #define FPCR_LEN __BITS(18,16)
117: #define FPCR_IDE __BIT(15) // Input Denormal Exception enable
118: #define FPCR_IXE __BIT(12) // IneXact Exception enable
119: #define FPCR_UFE __BIT(11) // UnderFlow Exception enable
120: #define FPCR_OFE __BIT(10) // OverFlow Exception enable
121: #define FPCR_DZE __BIT(9) // Divide by Zero Exception enable
122: #define FPCR_IOE __BIT(8) // Invalid Operation Exception enable
123: #define FPCR_ESUM 0x1F00
1.1 matt 124:
125: AARCH64REG_READ_INLINE(fpsr) // Floating Point Status Register
126: AARCH64REG_WRITE_INLINE(fpsr)
127:
1.13 skrll 128: #define FPSR_N32 __BIT(31) // AARCH32 Negative
129: #define FPSR_Z32 __BIT(30) // AARCH32 Zero
130: #define FPSR_C32 __BIT(29) // AARCH32 Carry
131: #define FPSR_V32 __BIT(28) // AARCH32 Overflow
132: #define FPSR_QC __BIT(27) // SIMD Saturation
133: #define FPSR_IDC __BIT(7) // Input Denormal Cumulative status
134: #define FPSR_IXC __BIT(4) // IneXact Cumulative status
135: #define FPSR_UFC __BIT(3) // UnderFlow Cumulative status
136: #define FPSR_OFC __BIT(2) // OverFlow Cumulative status
137: #define FPSR_DZC __BIT(1) // Divide by Zero Cumulative status
138: #define FPSR_IOC __BIT(0) // Invalid Operation Cumulative status
139: #define FPSR_CSUM 0x1F
1.1 matt 140:
141: AARCH64REG_READ_INLINE(nzcv) // condition codes
142: AARCH64REG_WRITE_INLINE(nzcv)
143:
1.13 skrll 144: #define NZCV_N __BIT(31) // Negative
145: #define NZCV_Z __BIT(30) // Zero
146: #define NZCV_C __BIT(29) // Carry
147: #define NZCV_V __BIT(28) // Overflow
1.1 matt 148:
149: AARCH64REG_READ_INLINE(tpidr_el0) // Thread Pointer ID Register (RW)
150: AARCH64REG_WRITE_INLINE(tpidr_el0)
151:
1.9 ryo 152: AARCH64REG_READ_INLINE(tpidrro_el0) // Thread Pointer ID Register (RO)
153:
1.3 skrll 154: /*
1.1 matt 155: * From here on, these can only be accessed at EL1 (kernel)
156: */
157:
158: /*
159: * These are readonly registers
160: */
1.9 ryo 161: AARCH64REG_READ_INLINE(aidr_el1)
162:
1.14 skrll 163: AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57
1.1 matt 164:
1.13 skrll 165: #define CBAR_PA __BITS(47,18)
1.1 matt 166:
1.9 ryo 167: AARCH64REG_READ_INLINE(ccsidr_el1)
168:
1.13 skrll 169: #define CCSIDR_WT __BIT(31) // Write-through supported
170: #define CCSIDR_WB __BIT(30) // Write-back supported
171: #define CCSIDR_RA __BIT(29) // Read-allocation supported
172: #define CCSIDR_WA __BIT(28) // Write-allocation supported
173: #define CCSIDR_NUMSET __BITS(27,13) // (Number of sets in cache) - 1
174: #define CCSIDR_ASSOC __BITS(12,3) // (Associativity of cache) - 1
175: #define CCSIDR_LINESIZE __BITS(2,0) // Number of bytes in cache line
1.9 ryo 176:
1.1 matt 177: AARCH64REG_READ_INLINE(clidr_el1)
1.9 ryo 178:
1.13 skrll 179: #define CLIDR_LOUU __BITS(29,27) // Level of Unification Uniprocessor
180: #define CLIDR_LOC __BITS(26,24) // Level of Coherency
181: #define CLIDR_LOUIS __BITS(23,21) // Level of Unification InnerShareable*/
182: #define CLIDR_CTYPE7 __BITS(20,18) // Cache Type field for level7
183: #define CLIDR_CTYPE6 __BITS(17,15) // Cache Type field for level6
184: #define CLIDR_CTYPE5 __BITS(14,12) // Cache Type field for level5
185: #define CLIDR_CTYPE4 __BITS(11,9) // Cache Type field for level4
186: #define CLIDR_CTYPE3 __BITS(8,6) // Cache Type field for level3
187: #define CLIDR_CTYPE2 __BITS(5,3) // Cache Type field for level2
188: #define CLIDR_CTYPE1 __BITS(2,0) // Cache Type field for level1
189: #define CLIDR_TYPE_NOCACHE 0 // No cache
190: #define CLIDR_TYPE_ICACHE 1 // Instruction cache only
191: #define CLIDR_TYPE_DCACHE 2 // Data cache only
192: #define CLIDR_TYPE_IDCACHE 3 // Separate inst and data caches
193: #define CLIDR_TYPE_UNIFIEDCACHE 4 // Unified cache
1.9 ryo 194:
195: AARCH64REG_READ_INLINE(currentel)
196: AARCH64REG_READ_INLINE(id_aa64afr0_el1)
197: AARCH64REG_READ_INLINE(id_aa64afr1_el1)
198: AARCH64REG_READ_INLINE(id_aa64dfr0_el1)
199:
1.13 skrll 200: #define ID_AA64DFR0_EL1_CTX_CMPS __BITS(31,28)
201: #define ID_AA64DFR0_EL1_WRPS __BITS(20,23)
202: #define ID_AA64DFR0_EL1_BRPS __BITS(12,15)
203: #define ID_AA64DFR0_EL1_PMUVER __BITS(8,11)
204: #define ID_AA64DFR0_EL1_PMUVER_NONE 0
1.12 christos 205: #define ID_AA64DFR0_EL1_PMUVER_V3 1
1.13 skrll 206: #define ID_AA64DFR0_EL1_PMUVER_NOV3 2
207: #define ID_AA64DFR0_EL1_TRACEVER __BITS(4,7)
208: #define ID_AA64DFR0_EL1_TRACEVER_NONE 0
209: #define ID_AA64DFR0_EL1_TRACEVER_IMPL 1
210: #define ID_AA64DFR0_EL1_DEBUGVER __BITS(0,3)
211: #define ID_AA64DFR0_EL1_DEBUGVER_V8A 6
1.9 ryo 212:
213: AARCH64REG_READ_INLINE(id_aa64dfr1_el1)
214:
215: AARCH64REG_READ_INLINE(id_aa64isar0_el1)
216:
1.13 skrll 217: #define ID_AA64ISAR0_EL1_CRC32 __BITS(19,16)
218: #define ID_AA64ISAR0_EL1_CRC32_NONE 0
219: #define ID_AA64ISAR0_EL1_CRC32_CRC32X 1
220: #define ID_AA64ISAR0_EL1_SHA2 __BITS(15,12)
1.12 christos 221: #define ID_AA64ISAR0_EL1_SHA2_NONE 0
222: #define ID_AA64ISAR0_EL1_SHA2_SHA256HSU 1
1.13 skrll 223: #define ID_AA64ISAR0_EL1_SHA1 __BITS(11,8)
1.12 christos 224: #define ID_AA64ISAR0_EL1_SHA1_NONE 0
225: #define ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU 1
1.13 skrll 226: #define ID_AA64ISAR0_EL1_AES __BITS(7,4)
1.12 christos 227: #define ID_AA64ISAR0_EL1_AES_NONE 0
228: #define ID_AA64ISAR0_EL1_AES_AES 1
229: #define ID_AA64ISAR0_EL1_AES_PMUL 2
1.9 ryo 230:
231: AARCH64REG_READ_INLINE(id_aa64isar1_el1)
1.31 maxv 232:
233: #define ID_AA64ISAR1_EL1_SPECRES __BITS(43,40)
234: #define ID_AA64ISAR1_EL1_SPECRES_NONE 0
235: #define ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
236: #define ID_AA64ISAR1_EL1_SB __BITS(39,36)
237: #define ID_AA64ISAR1_EL1_SB_NONE 0
238: #define ID_AA64ISAR1_EL1_SB_SUPPORTED 1
239: #define ID_AA64ISAR1_EL1_FRINTTS __BITS(35,32)
240: #define ID_AA64ISAR1_EL1_FRINTTS_NONE 0
241: #define ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
242: #define ID_AA64ISAR1_EL1_GPI __BITS(31,28)
243: #define ID_AA64ISAR1_EL1_GPI_NONE 0
244: #define ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
245: #define ID_AA64ISAR1_EL1_GPA __BITS(27,24)
246: #define ID_AA64ISAR1_EL1_GPA_NONE 0
247: #define ID_AA64ISAR1_EL1_GPA_QARMA 1
248: #define ID_AA64ISAR1_EL1_LRCPC __BITS(23,20)
249: #define ID_AA64ISAR1_EL1_LRCPC_NONE 0
250: #define ID_AA64ISAR1_EL1_LRCPC_PR 1
251: #define ID_AA64ISAR1_EL1_LRCPC_PR_UR 2
252: #define ID_AA64ISAR1_EL1_FCMA __BITS(19,16)
253: #define ID_AA64ISAR1_EL1_FCMA_NONE 0
254: #define ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
255: #define ID_AA64ISAR1_EL1_JSCVT __BITS(15,12)
256: #define ID_AA64ISAR1_EL1_JSCVT_NONE 0
257: #define ID_AA64ISAR1_EL1_JSCVT_SUPPORTED 1
258: #define ID_AA64ISAR1_EL1_API __BITS(11,8)
259: #define ID_AA64ISAR1_EL1_API_NONE 0
260: #define ID_AA64ISAR1_EL1_API_SUPPORTED 1
261: #define ID_AA64ISAR1_EL1_API_ENHANCED 2
262: #define ID_AA64ISAR1_EL1_APA __BITS(7,4)
263: #define ID_AA64ISAR1_EL1_APA_NONE 0
264: #define ID_AA64ISAR1_EL1_APA_QARMA 1
265: #define ID_AA64ISAR1_EL1_APA_QARMA_ENH 2
266: #define ID_AA64ISAR1_EL1_DPB __BITS(3,0)
267: #define ID_AA64ISAR1_EL1_DPB_NONE 0
268: #define ID_AA64ISAR1_EL1_DPB_CVAP 1
269: #define ID_AA64ISAR1_EL1_DPB_CVAP_CVADP 2
270:
1.9 ryo 271: AARCH64REG_READ_INLINE(id_aa64mmfr0_el1)
272:
1.13 skrll 273: #define ID_AA64MMFR0_EL1_TGRAN4 __BITS(31,28)
274: #define ID_AA64MMFR0_EL1_TGRAN4_4KB 0
275: #define ID_AA64MMFR0_EL1_TGRAN4_NONE 15
276: #define ID_AA64MMFR0_EL1_TGRAN64 __BITS(24,27)
277: #define ID_AA64MMFR0_EL1_TGRAN64_64KB 0
278: #define ID_AA64MMFR0_EL1_TGRAN64_NONE 15
279: #define ID_AA64MMFR0_EL1_TGRAN16 __BITS(20,23)
280: #define ID_AA64MMFR0_EL1_TGRAN16_NONE 0
281: #define ID_AA64MMFR0_EL1_TGRAN16_16KB 1
282: #define ID_AA64MMFR0_EL1_BIGENDEL0 __BITS(16,19)
1.12 christos 283: #define ID_AA64MMFR0_EL1_BIGENDEL0_NONE 0
1.13 skrll 284: #define ID_AA64MMFR0_EL1_BIGENDEL0_MIX 1
285: #define ID_AA64MMFR0_EL1_SNSMEM __BITS(12,15)
286: #define ID_AA64MMFR0_EL1_SNSMEM_NONE 0
287: #define ID_AA64MMFR0_EL1_SNSMEM_SNSMEM 1
288: #define ID_AA64MMFR0_EL1_BIGEND __BITS(8,11)
289: #define ID_AA64MMFR0_EL1_BIGEND_NONE 0
290: #define ID_AA64MMFR0_EL1_BIGEND_MIX 1
291: #define ID_AA64MMFR0_EL1_ASIDBITS __BITS(4,7)
292: #define ID_AA64MMFR0_EL1_ASIDBITS_8BIT 0
1.12 christos 293: #define ID_AA64MMFR0_EL1_ASIDBITS_16BIT 2
1.13 skrll 294: #define ID_AA64MMFR0_EL1_PARANGE __BITS(0,3)
295: #define ID_AA64MMFR0_EL1_PARANGE_4G 0
296: #define ID_AA64MMFR0_EL1_PARANGE_64G 1
297: #define ID_AA64MMFR0_EL1_PARANGE_1T 2
298: #define ID_AA64MMFR0_EL1_PARANGE_4T 3
299: #define ID_AA64MMFR0_EL1_PARANGE_16T 4
300: #define ID_AA64MMFR0_EL1_PARANGE_256T 5
1.9 ryo 301:
302: AARCH64REG_READ_INLINE(id_aa64mmfr1_el1)
1.31 maxv 303:
304: #define ID_AA64MMFR1_EL1_XNX __BITS(31,28)
305: #define ID_AA64MMFR1_EL1_XNX_NONE 0
306: #define ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
307: #define ID_AA64MMFR1_EL1_SPECSEI __BITS(27,24)
308: #define ID_AA64MMFR1_EL1_SPECSEI_NONE 0
309: #define ID_AA64MMFR1_EL1_SPECSEI_EXTINT 1
310: #define ID_AA64MMFR1_EL1_PAN __BITS(23,20)
311: #define ID_AA64MMFR1_EL1_PAN_NONE 0
312: #define ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
313: #define ID_AA64MMFR1_EL1_PAN_S1E1 2
314: #define ID_AA64MMFR1_EL1_LO __BITS(19,16)
315: #define ID_AA64MMFR1_EL1_LO_NONE 0
316: #define ID_AA64MMFR1_EL1_LO_SUPPORTED 1
317: #define ID_AA64MMFR1_EL1_HPDS __BITS(15,12)
318: #define ID_AA64MMFR1_EL1_HPDS_NONE 0
319: #define ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
320: #define ID_AA64MMFR1_EL1_HPDS_EXTRA_PTD 2
321: #define ID_AA64MMFR1_EL1_VH __BITS(11,8)
322: #define ID_AA64MMFR1_EL1_VH_NONE 0
323: #define ID_AA64MMFR1_EL1_VH_SUPPORTED 1
324: #define ID_AA64MMFR1_EL1_VMIDBITS __BITS(7,4)
325: #define ID_AA64MMFR1_EL1_VMIDBITS_8BIT 0
326: #define ID_AA64MMFR1_EL1_VMIDBITS_16BIT 2
327: #define ID_AA64MMFR1_EL1_HAFDBS __BITS(3,0)
328: #define ID_AA64MMFR1_EL1_HAFDBS_NONE 0
329: #define ID_AA64MMFR1_EL1_HAFDBS_A 1
330: #define ID_AA64MMFR1_EL1_HAFDBS_AD 2
331:
1.21 mrg 332: AARCH64REG_READ_INLINE(id_aa64mmfr2_el1)
1.31 maxv 333:
334: #define ID_AA64MMFR2_EL1_E0PD __BITS(63,60)
335: #define ID_AA64MMFR2_EL1_E0PD_NONE 0
336: #define ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
337: #define ID_AA64MMFR2_EL1_EVT __BITS(59,56)
338: #define ID_AA64MMFR2_EL1_EVT_NONE 0
339: #define ID_AA64MMFR2_EL1_EVT_TO_TI 1
340: #define ID_AA64MMFR2_EL1_EVT_TO_TI_TTL 2
341: #define ID_AA64MMFR2_EL1_BBM __BITS(55,52)
342: #define ID_AA64MMFR2_EL1_BBM_L0 0
343: #define ID_AA64MMFR2_EL1_BBM_L1 1
344: #define ID_AA64MMFR2_EL1_BBM_L2 2
345: #define ID_AA64MMFR2_EL1_TTL __BITS(51,48)
346: #define ID_AA64MMFR2_EL1_TTL_NONE 0
347: #define ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
348: #define ID_AA64MMFR2_EL1_FWB __BITS(43,40)
349: #define ID_AA64MMFR2_EL1_FWB_NONE 0
350: #define ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
351: #define ID_AA64MMFR2_EL1_IDS __BITS(39,36)
352: #define ID_AA64MMFR2_EL1_IDS_0X0 0
353: #define ID_AA64MMFR2_EL1_IDS_0X18 1
354: #define ID_AA64MMFR2_EL1_AT __BITS(35,32)
355: #define ID_AA64MMFR2_EL1_AT_NONE 0
356: #define ID_AA64MMFR2_EL1_AT_16BIT 1
357: #define ID_AA64MMFR2_EL1_ST __BITS(31,28)
358: #define ID_AA64MMFR2_EL1_ST_39 0
359: #define ID_AA64MMFR2_EL1_ST_48 1
360: #define ID_AA64MMFR2_EL1_NV __BITS(27,24)
361: #define ID_AA64MMFR2_EL1_NV_NONE 0
362: #define ID_AA64MMFR2_EL1_NV_HCR 1
363: #define ID_AA64MMFR2_EL1_NV_HCR_VNCR 2
364: #define ID_AA64MMFR2_EL1_CCIDX __BITS(23,20)
365: #define ID_AA64MMFR2_EL1_CCIDX_32BIT 0
366: #define ID_AA64MMFR2_EL1_CCIDX_64BIT 1
367: #define ID_AA64MMFR2_EL1_VARANGE __BITS(19,16)
368: #define ID_AA64MMFR2_EL1_VARANGE_48BIT 0
369: #define ID_AA64MMFR2_EL1_VARANGE_52BIT 1
370: #define ID_AA64MMFR2_EL1_IESB __BITS(15,12)
371: #define ID_AA64MMFR2_EL1_IESB_NONE 0
372: #define ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
373: #define ID_AA64MMFR2_EL1_LSM __BITS(11,8)
374: #define ID_AA64MMFR2_EL1_LSM_NONE 0
375: #define ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
376: #define ID_AA64MMFR2_EL1_UAO __BITS(7,4)
377: #define ID_AA64MMFR2_EL1_UAO_NONE 0
378: #define ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
379: #define ID_AA64MMFR2_EL1_CNP __BITS(3,0)
380: #define ID_AA64MMFR2_EL1_CNP_NONE 0
381: #define ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
382:
383: AARCH64REG_READ_INLINE2(a72_cpuactlr_el1, s3_1_c15_c2_0)
1.9 ryo 384: AARCH64REG_READ_INLINE(id_aa64pfr0_el1)
385: AARCH64REG_READ_INLINE(id_aa64pfr1_el1)
1.31 maxv 386:
387: #define ID_AA64PFR1_EL1_RASFRAC __BITS(15,12)
388: #define ID_AA64PFR1_EL1_RASFRAC_NORMAL 0
389: #define ID_AA64PFR1_EL1_RASFRAC_EXTRA 1
390: #define ID_AA64PFR1_EL1_MTE __BITS(11,8)
391: #define ID_AA64PFR1_EL1_MTE_NONE 0
392: #define ID_AA64PFR1_EL1_MTE_PARTIAL 1
393: #define ID_AA64PFR1_EL1_MTE_SUPPORTED 2
394: #define ID_AA64PFR1_EL1_SSBS __BITS(7,4)
395: #define ID_AA64PFR1_EL1_SSBS_NONE 0
396: #define ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
397: #define ID_AA64PFR1_EL1_SSBS_MSR_MRS 2
398: #define ID_AA64PFR1_EL1_BT __BITS(3,0)
399: #define ID_AA64PFR1_EL1_BT_NONE 0
400: #define ID_AA64PFR1_EL1_BT_SUPPORTED 1
401:
1.21 mrg 402: AARCH64REG_READ_INLINE(id_aa64zfr0_el1)
1.9 ryo 403: AARCH64REG_READ_INLINE(id_pfr1_el1)
1.1 matt 404: AARCH64REG_READ_INLINE(isr_el1)
405: AARCH64REG_READ_INLINE(midr_el1)
406: AARCH64REG_READ_INLINE(mpidr_el1)
1.9 ryo 407:
1.21 mrg 408: #define MIDR_EL1_IMPL __BITS(31,24) // Implementor
409: #define MIDR_EL1_VARIANT __BITS(23,20) // CPU Variant
410: #define MIDR_EL1_ARCH __BITS(19,16) // Architecture
411: #define MIDR_EL1_PARTNUM __BITS(15,4) // PartNum
412: #define MIDR_EL1_REVISION __BITS(3,0) // Revision
413:
1.13 skrll 414: #define MPIDR_AFF3 __BITS(32,39)
415: #define MPIDR_U __BIT(30) // 1 = Uni-Processor System
416: #define MPIDR_MT __BIT(24) // 1 = SMT(AFF0 is logical)
417: #define MPIDR_AFF2 __BITS(16,23)
418: #define MPIDR_AFF1 __BITS(8,15)
419: #define MPIDR_AFF0 __BITS(0,7)
1.9 ryo 420:
1.1 matt 421: AARCH64REG_READ_INLINE(mvfr0_el1)
1.9 ryo 422:
1.14 skrll 423: #define MVFR0_FPROUND __BITS(31,28)
424: #define MVFR0_FPROUND_NEAREST 0
1.12 christos 425: #define MVFR0_FPROUND_ALL 1
1.14 skrll 426: #define MVFR0_FPSHVEC __BITS(27,24)
1.12 christos 427: #define MVFR0_FPSHVEC_NONE 0
1.14 skrll 428: #define MVFR0_FPSHVEC_SHVEC 1
429: #define MVFR0_FPSQRT __BITS(23,20)
1.12 christos 430: #define MVFR0_FPSQRT_NONE 0
431: #define MVFR0_FPSQRT_VSQRT 1
1.14 skrll 432: #define MVFR0_FPDIVIDE __BITS(19,16)
433: #define MVFR0_FPDIVIDE_NONE 0
434: #define MVFR0_FPDIVIDE_VDIV 1
435: #define MVFR0_FPTRAP __BITS(15,12)
1.12 christos 436: #define MVFR0_FPTRAP_NONE 0
437: #define MVFR0_FPTRAP_TRAP 1
1.14 skrll 438: #define MVFR0_FPDP __BITS(11,8)
1.12 christos 439: #define MVFR0_FPDP_NONE 0
440: #define MVFR0_FPDP_VFPV2 1
441: #define MVFR0_FPDP_VFPV3 2
1.14 skrll 442: #define MVFR0_FPSP __BITS(7,4)
1.12 christos 443: #define MVFR0_FPSP_NONE 0
444: #define MVFR0_FPSP_VFPV2 1
445: #define MVFR0_FPSP_VFPV3 2
1.14 skrll 446: #define MVFR0_SIMDREG __BITS(3,0)
1.12 christos 447: #define MVFR0_SIMDREG_NONE 0
1.14 skrll 448: #define MVFR0_SIMDREG_16x64 1
449: #define MVFR0_SIMDREG_32x64 2
1.9 ryo 450:
1.1 matt 451: AARCH64REG_READ_INLINE(mvfr1_el1)
1.9 ryo 452:
1.14 skrll 453: #define MVFR1_SIMDFMAC __BITS(31,28)
454: #define MVFR1_SIMDFMAC_NONE 0
455: #define MVFR1_SIMDFMAC_FMAC 1
456: #define MVFR1_FPHP __BITS(27,24)
1.12 christos 457: #define MVFR1_FPHP_NONE 0
1.14 skrll 458: #define MVFR1_FPHP_HALF_SINGLE 1
459: #define MVFR1_FPHP_HALF_DOUBLE 2
1.20 riastrad 460: #define MVFR1_FPHP_HALF_ARITH 3
1.14 skrll 461: #define MVFR1_SIMDHP __BITS(23,20)
1.12 christos 462: #define MVFR1_SIMDHP_NONE 0
463: #define MVFR1_SIMDHP_HALF 1
1.20 riastrad 464: #define MVFR1_SIMDHP_HALF_ARITH 3
1.14 skrll 465: #define MVFR1_SIMDSP __BITS(19,16)
1.12 christos 466: #define MVFR1_SIMDSP_NONE 0
1.14 skrll 467: #define MVFR1_SIMDSP_SINGLE 1
468: #define MVFR1_SIMDINT __BITS(15,12)
1.12 christos 469: #define MVFR1_SIMDINT_NONE 0
1.14 skrll 470: #define MVFR1_SIMDINT_INTEGER 1
471: #define MVFR1_SIMDLS __BITS(11,8)
1.12 christos 472: #define MVFR1_SIMDLS_NONE 0
1.14 skrll 473: #define MVFR1_SIMDLS_LOADSTORE 1
474: #define MVFR1_FPDNAN __BITS(7,4)
1.12 christos 475: #define MVFR1_FPDNAN_NONE 0
476: #define MVFR1_FPDNAN_NAN 1
1.14 skrll 477: #define MVFR1_FPFTZ __BITS(3,0)
1.12 christos 478: #define MVFR1_FPFTZ_NONE 0
1.14 skrll 479: #define MVFR1_FPFTZ_DENORMAL 1
1.9 ryo 480:
1.1 matt 481: AARCH64REG_READ_INLINE(mvfr2_el1)
1.9 ryo 482:
1.14 skrll 483: #define MVFR2_FPMISC __BITS(7,4)
1.12 christos 484: #define MVFR2_FPMISC_NONE 0
485: #define MVFR2_FPMISC_SEL 1
1.14 skrll 486: #define MVFR2_FPMISC_DROUND 2
487: #define MVFR2_FPMISC_ROUNDINT 3
488: #define MVFR2_FPMISC_MAXMIN 4
489: #define MVFR2_SIMDMISC __BITS(3,0)
490: #define MVFR2_SIMDMISC_NONE 0
491: #define MVFR2_SIMDMISC_DROUND 1
1.12 christos 492: #define MVFR2_SIMDMISC_ROUNDINT 2
1.14 skrll 493: #define MVFR2_SIMDMISC_MAXMIN 3
1.9 ryo 494:
1.1 matt 495: AARCH64REG_READ_INLINE(revidr_el1)
496:
497: /*
498: * These are read/write registers
499: */
500: AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser
501: AARCH64REG_WRITE_INLINE(cpacr_el1)
502:
1.14 skrll 503: #define CPACR_TTA __BIT(28) // System Register Access Traps
504: #define CPACR_FPEN __BITS(21,20)
505: #define CPACR_FPEN_NONE __SHIFTIN(0, CPACR_FPEN)
506: #define CPACR_FPEN_EL1 __SHIFTIN(1, CPACR_FPEN)
507: #define CPACR_FPEN_NONE_2 __SHIFTIN(2, CPACR_FPEN)
508: #define CPACR_FPEN_ALL __SHIFTIN(3, CPACR_FPEN)
1.1 matt 509:
1.9 ryo 510: AARCH64REG_READ_INLINE(csselr_el1) // Cache Size Selection Register
511: AARCH64REG_WRITE_INLINE(csselr_el1)
512:
1.14 skrll 513: #define CSSELR_LEVEL __BITS(3,1) // Cache level of required cache
514: #define CSSELR_IND __BIT(0) // Instruction not Data bit
1.9 ryo 515:
516: AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register
517: AARCH64REG_WRITE_INLINE(daif)
518: AARCH64REG_WRITEIMM_INLINE(daifclr)
519: AARCH64REG_WRITEIMM_INLINE(daifset)
520:
1.14 skrll 521: #define DAIF_D __BIT(9) // Debug Exception Mask
522: #define DAIF_A __BIT(8) // SError Abort Mask
523: #define DAIF_I __BIT(7) // IRQ Mask
524: #define DAIF_F __BIT(6) // FIQ Mask
525: #define DAIF_SETCLR_SHIFT 6 // for daifset/daifclr #imm shift
1.9 ryo 526:
1.1 matt 527: AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register
528: AARCH64REG_WRITE_INLINE(elr_el1)
529:
530: AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register
531: AARCH64REG_WRITE_INLINE(esr_el1)
532:
1.14 skrll 533: #define ESR_EC __BITS(31,26) // Exception Cause
534: #define ESR_EC_UNKNOWN 0x00 // AXX: Unknown Reason
535: #define ESR_EC_WFX 0x01 // AXX: WFI or WFE instruction execution
536: #define ESR_EC_CP15_RT 0x03 // A32: MCR/MRC access to CP15 !EC=0
537: #define ESR_EC_CP15_RRT 0x04 // A32: MCRR/MRRC access to CP15 !EC=0
538: #define ESR_EC_CP14_RT 0x05 // A32: MCR/MRC access to CP14
539: #define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14
540: #define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers
541: #define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7
542: #define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14
543: #define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State
544: #define ESR_EC_SVC_A32 0x11 // A32: SVC Instruction Execution
545: #define ESR_EC_HVC_A32 0x12 // A32: HVC Instruction Execution
546: #define ESR_EC_SMC_A32 0x13 // A32: SMC Instruction Execution
547: #define ESR_EC_SVC_A64 0x15 // A64: SVC Instruction Execution
548: #define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution
549: #define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution
550: #define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7)
551: #define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0)
552: #define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1)
553: #define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC
554: #define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0)
555: #define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1)
556: #define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP
557: #define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception
558: #define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception
559: #define ESR_EC_SERROR 0x2f // AXX: SError Interrupt
560: #define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0)
561: #define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1)
562: #define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0)
563: #define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1)
564: #define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0)
565: #define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1)
566: #define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution
567: #define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception
568: #define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution
569: #define ESR_IL __BIT(25) // Instruction Length (1=32-bit)
570: #define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome
1.12 christos 571: #define ESR_ISS_CV __BIT(24) // common
572: #define ESR_ISS_COND __BITS(23,20) // common
573: #define ESR_ISS_WFX_TRAP_INSN __BIT(0) // for ESR_EC_WFX
574: #define ESR_ISS_MRC_OPC2 __BITS(19,17) // for ESR_EC_CP15_RT
575: #define ESR_ISS_MRC_OPC1 __BITS(16,14) // for ESR_EC_CP15_RT
576: #define ESR_ISS_MRC_CRN __BITS(13,10) // for ESR_EC_CP15_RT
577: #define ESR_ISS_MRC_RT __BITS(9,5) // for ESR_EC_CP15_RT
578: #define ESR_ISS_MRC_CRM __BITS(4,1) // for ESR_EC_CP15_RT
579: #define ESR_ISS_MRC_DIRECTION __BIT(0) // for ESR_EC_CP15_RT
580: #define ESR_ISS_MCRR_OPC1 __BITS(19,16) // for ESR_EC_CP15_RRT
581: #define ESR_ISS_MCRR_RT2 __BITS(14,10) // for ESR_EC_CP15_RRT
582: #define ESR_ISS_MCRR_RT __BITS(9,5) // for ESR_EC_CP15_RRT
583: #define ESR_ISS_MCRR_CRM __BITS(4,1) // for ESR_EC_CP15_RRT
584: #define ESR_ISS_MCRR_DIRECTION __BIT(0) // for ESR_EC_CP15_RRT
585: #define ESR_ISS_HVC_IMM16 __BITS(15,0) // for ESR_EC_{SVC,HVC}
586: // ...
587: #define ESR_ISS_INSNABORT_EA __BIT(9) // for ESC_RC_INSN_ABT_EL[01]
588: #define ESR_ISS_INSNABORT_S1PTW __BIT(7) // for ESC_RC_INSN_ABT_EL[01]
589: #define ESR_ISS_INSNABORT_IFSC __BITS(0,5) // for ESC_RC_INSN_ABT_EL[01]
590: #define ESR_ISS_DATAABORT_ISV __BIT(24) // for ESC_RC_DATA_ABT_EL[01]
591: #define ESR_ISS_DATAABORT_SAS __BITS(23,22) // for ESC_RC_DATA_ABT_EL[01]
592: #define ESR_ISS_DATAABORT_SSE __BIT(21) // for ESC_RC_DATA_ABT_EL[01]
593: #define ESR_ISS_DATAABORT_SRT __BITS(19,16) // for ESC_RC_DATA_ABT_EL[01]
594: #define ESR_ISS_DATAABORT_SF __BIT(15) // for ESC_RC_DATA_ABT_EL[01]
595: #define ESR_ISS_DATAABORT_AR __BIT(14) // for ESC_RC_DATA_ABT_EL[01]
596: #define ESR_ISS_DATAABORT_EA __BIT(9) // for ESC_RC_DATA_ABT_EL[01]
597: #define ESR_ISS_DATAABORT_CM __BIT(8) // for ESC_RC_DATA_ABT_EL[01]
598: #define ESR_ISS_DATAABORT_S1PTW __BIT(7) // for ESC_RC_DATA_ABT_EL[01]
599: #define ESR_ISS_DATAABORT_WnR __BIT(6) // for ESC_RC_DATA_ABT_EL[01]
600: #define ESR_ISS_DATAABORT_DFSC __BITS(0,5) // for ESC_RC_DATA_ABT_EL[01]
601:
1.14 skrll 602: #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_0 0x00
603: #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_1 0x01
604: #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_2 0x02
605: #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_3 0x03
606: #define ESR_ISS_FSC_TRANSLATION_FAULT_0 0x04
607: #define ESR_ISS_FSC_TRANSLATION_FAULT_1 0x05
608: #define ESR_ISS_FSC_TRANSLATION_FAULT_2 0x06
609: #define ESR_ISS_FSC_TRANSLATION_FAULT_3 0x07
610: #define ESR_ISS_FSC_ACCESS_FAULT_0 0x08
611: #define ESR_ISS_FSC_ACCESS_FAULT_1 0x09
612: #define ESR_ISS_FSC_ACCESS_FAULT_2 0x0a
613: #define ESR_ISS_FSC_ACCESS_FAULT_3 0x0b
614: #define ESR_ISS_FSC_PERM_FAULT_0 0x0c
615: #define ESR_ISS_FSC_PERM_FAULT_1 0x0d
616: #define ESR_ISS_FSC_PERM_FAULT_2 0x0e
617: #define ESR_ISS_FSC_PERM_FAULT_3 0x0f
618: #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT 0x10
619: #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_0 0x14
620: #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_1 0x15
621: #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_2 0x16
622: #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_3 0x17
623: #define ESR_ISS_FSC_SYNC_PARITY_ERROR 0x18
624: #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_0 0x1c
625: #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_1 0x1d
626: #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_2 0x1e
627: #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_3 0x1f
628: #define ESR_ISS_FSC_ALIGNMENT_FAULT 0x21
629: #define ESR_ISS_FSC_TLB_CONFLICT_FAULT 0x30
630: #define ESR_ISS_FSC_LOCKDOWN_ABORT 0x34
631: #define ESR_ISS_FSC_UNSUPPORTED_EXCLUSIVE 0x35
632: #define ESR_ISS_FSC_FIRST_LEVEL_DOMAIN_FAULT 0x3d
633: #define ESR_ISS_FSC_SECOND_LEVEL_DOMAIN_FAULT 0x3e
1.1 matt 634:
635:
636: AARCH64REG_READ_INLINE(far_el1) // Fault Address Register
637: AARCH64REG_WRITE_INLINE(far_el1)
638:
1.9 ryo 639: AARCH64REG_READ_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73
640: AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73
641:
1.12 christos 642: #define L2CTLR_NUMOFCORE __BITS(25,24) // Number of cores
643: #define L2CTLR_CPUCACHEPROT __BIT(22) // CPU Cache Protection
644: #define L2CTLR_SCUL2CACHEPROT __BIT(21) // SCU-L2 Cache Protection
645: #define L2CTLR_L2_INPUT_LATENCY __BIT(5) // L2 Data RAM input latency
646: #define L2CTLR_L2_OUTPUT_LATENCY __BIT(0) // L2 Data RAM output latency
1.9 ryo 647:
648: AARCH64REG_READ_INLINE(mair_el1) // Memory Attribute Indirection Register
1.1 matt 649: AARCH64REG_WRITE_INLINE(mair_el1)
650:
1.14 skrll 651: #define MAIR_ATTR0 __BITS(7,0)
652: #define MAIR_ATTR1 __BITS(15,8)
653: #define MAIR_ATTR2 __BITS(23,16)
654: #define MAIR_ATTR3 __BITS(31,24)
655: #define MAIR_ATTR4 __BITS(39,32)
656: #define MAIR_ATTR5 __BITS(47,40)
657: #define MAIR_ATTR6 __BITS(55,48)
658: #define MAIR_ATTR7 __BITS(63,56)
659: #define MAIR_DEVICE_nGnRnE 0x00 // NoGathering,NoReordering,NoEarlyWriteAck.
1.29 jmcneill 660: #define MAIR_DEVICE_nGnRE 0x04 // NoGathering,NoReordering,EarlyWriteAck.
1.14 skrll 661: #define MAIR_NORMAL_NC 0x44
662: #define MAIR_NORMAL_WT 0xbb
663: #define MAIR_NORMAL_WB 0xff
1.9 ryo 664:
1.1 matt 665: AARCH64REG_READ_INLINE(par_el1) // Physical Address Register
666: AARCH64REG_WRITE_INLINE(par_el1)
667:
1.14 skrll 668: #define PAR_ATTR __BITS(63,56) // F=0 memory attributes
669: #define PAR_PA __BITS(47,12) // F=0 physical address
670: #define PAR_NS __BIT(9) // F=0 non-secure
671: #define PAR_S __BIT(9) // F=1 failure stage
672: #define PAR_SHA __BITS(8,7) // F=0 shareability attribute
673: #define PAR_SHA_NONE 0
674: #define PAR_SHA_OUTER 2
675: #define PAR_SHA_INNER 3
676: #define PAR_PTW __BIT(8) // F=1 partial table walk
677: #define PAR_FST __BITS(6,1) // F=1 fault status code
678: #define PAR_F __BIT(0) // translation failed
1.1 matt 679:
680: AARCH64REG_READ_INLINE(rmr_el1) // Reset Management Register
681: AARCH64REG_WRITE_INLINE(rmr_el1)
682:
683: AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register
684: AARCH64REG_WRITE_INLINE(rvbar_el1)
685:
1.24 ryo 686: AARCH64REG_ATWRITE_INLINE(s1e0r); // Address Translate Stages 1
687: AARCH64REG_ATWRITE_INLINE(s1e0w);
688: AARCH64REG_ATWRITE_INLINE(s1e1r);
689: AARCH64REG_ATWRITE_INLINE(s1e1w);
690:
1.2 skrll 691: AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register
692: AARCH64REG_WRITE_INLINE(sctlr_el1)
1.1 matt 693:
1.14 skrll 694: #define SCTLR_RES0 0xc8222400 // Reserved ARMv8.0, write 0
695: #define SCTLR_RES1 0x30d00800 // Reserved ARMv8.0, write 1
696: #define SCTLR_M __BIT(0)
697: #define SCTLR_A __BIT(1)
698: #define SCTLR_C __BIT(2)
699: #define SCTLR_SA __BIT(3)
700: #define SCTLR_SA0 __BIT(4)
701: #define SCTLR_CP15BEN __BIT(5)
1.32 ! maxv 702: #define SCTLR_nAA __BIT(6)
1.14 skrll 703: #define SCTLR_ITD __BIT(7)
704: #define SCTLR_SED __BIT(8)
705: #define SCTLR_UMA __BIT(9)
706: #define SCTLR_I __BIT(12)
707: #define SCTLR_DZE __BIT(14)
708: #define SCTLR_UCT __BIT(15)
709: #define SCTLR_nTWI __BIT(16)
710: #define SCTLR_nTWE __BIT(18)
711: #define SCTLR_WXN __BIT(19)
712: #define SCTLR_IESB __BIT(21)
713: #define SCTLR_SPAN __BIT(23)
714: #define SCTLR_EOE __BIT(24)
715: #define SCTLR_EE __BIT(25)
716: #define SCTLR_UCI __BIT(26)
717: #define SCTLR_nTLSMD __BIT(28)
718: #define SCTLR_LSMAOE __BIT(29)
1.9 ryo 719:
720: // current EL stack pointer
1.12 christos 721: static __inline uint64_t
1.9 ryo 722: reg_sp_read(void)
723: {
724: uint64_t __rv;
725: __asm __volatile ("mov %0, sp" : "=r"(__rv));
726: return __rv;
727: }
728:
729: AARCH64REG_READ_INLINE(sp_el0) // EL0 Stack Pointer
1.1 matt 730: AARCH64REG_WRITE_INLINE(sp_el0)
731:
1.9 ryo 732: AARCH64REG_READ_INLINE(spsel) // Stack Pointer Select
733: AARCH64REG_WRITE_INLINE(spsel)
1.1 matt 734:
1.14 skrll 735: #define SPSEL_SP __BIT(0); // use SP_EL0 at all exception levels
1.1 matt 736:
737: AARCH64REG_READ_INLINE(spsr_el1) // Saved Program Status Register
738: AARCH64REG_WRITE_INLINE(spsr_el1)
739:
1.14 skrll 740: #define SPSR_NZCV __BITS(31,28) // mask of N Z C V
741: #define SPSR_N __BIT(31) // Negative
742: #define SPSR_Z __BIT(30) // Zero
743: #define SPSR_C __BIT(29) // Carry
744: #define SPSR_V __BIT(28) // oVerflow
745: #define SPSR_A32_Q __BIT(27) // A32: Overflow
1.32 ! maxv 746: #define SPSR_A32_IT1 __BIT(26) // A32: IT[1]
! 747: #define SPSR_A32_IT0 __BIT(25) // A32: IT[0]
1.14 skrll 748: #define SPSR_SS __BIT(21) // Software Step
1.22 ryo 749: #define SPSR_SS_SHIFT 21
1.14 skrll 750: #define SPSR_IL __BIT(20) // Instruction Length
751: #define SPSR_GE __BITS(19,16) // A32: SIMD GE
752: #define SPSR_IT7 __BIT(15) // A32: IT[7]
753: #define SPSR_IT6 __BIT(14) // A32: IT[6]
754: #define SPSR_IT5 __BIT(13) // A32: IT[5]
755: #define SPSR_IT4 __BIT(12) // A32: IT[4]
756: #define SPSR_IT3 __BIT(11) // A32: IT[3]
757: #define SPSR_IT2 __BIT(10) // A32: IT[2]
758: #define SPSR_A64_D __BIT(9) // A64: Debug Exception Mask
759: #define SPSR_A32_E __BIT(9) // A32: BE Endian Mode
760: #define SPSR_A __BIT(8) // Async abort (SError) Mask
761: #define SPSR_I __BIT(7) // IRQ Mask
762: #define SPSR_F __BIT(6) // FIQ Mask
763: #define SPSR_A32_T __BIT(5) // A32 Thumb Mode
1.19 ryo 764: #define SPSR_A32 __BIT(4) // A32 Mode (a part of SPSR_M)
1.14 skrll 765: #define SPSR_M __BITS(4,0) // Execution State
766: #define SPSR_M_EL3H 0x0d
767: #define SPSR_M_EL3T 0x0c
768: #define SPSR_M_EL2H 0x09
769: #define SPSR_M_EL2T 0x08
770: #define SPSR_M_EL1H 0x05
771: #define SPSR_M_EL1T 0x04
772: #define SPSR_M_EL0T 0x00
773: #define SPSR_M_SYS32 0x1f
774: #define SPSR_M_UND32 0x1b
775: #define SPSR_M_ABT32 0x17
776: #define SPSR_M_SVC32 0x13
777: #define SPSR_M_IRQ32 0x12
778: #define SPSR_M_FIQ32 0x11
779: #define SPSR_M_USR32 0x10
1.1 matt 780:
781: AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register
782: AARCH64REG_WRITE_INLINE(tcr_el1)
783:
1.27 skrll 784:
785: /* TCR_EL1 - Translation Control Register */
786: #define TCR_TBI1 __BIT(38) /* ignore Top Byte TTBR1_EL1 */
787: #define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */
788: #define TCR_AS64K __BIT(36) /* Use 64K ASIDs */
789: #define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */
790: #define TCR_IPS_4PB __SHIFTIN(6,TCR_IPS) /* 52 bits ( 4 PB) */
791: #define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */
792: #define TCR_IPS_16TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */
793: #define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */
794: #define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */
795: #define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */
796: #define TCR_IPS_4GB __SHIFTIN(0,TCR_IPS) /* 32 bits (4 GB) */
797: #define TCR_TG1 __BITS(31,30) /* TTBR1 Page Granule Size */
798: #define TCR_TG1_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */
799: #define TCR_TG1_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */
800: #define TCR_TG1_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */
801: #define TCR_SH1 __BITS(29,28)
802: #define TCR_SH1_NONE __SHIFTIN(0,TCR_SH1)
803: #define TCR_SH1_OUTER __SHIFTIN(2,TCR_SH1)
804: #define TCR_SH1_INNER __SHIFTIN(3,TCR_SH1)
805: #define TCR_ORGN1 __BITS(27,26) /* TTBR1 Outer cacheability */
806: #define TCR_ORGN1_NC __SHIFTIN(0,TCR_ORGN1) /* Non Cacheable */
807: #define TCR_ORGN1_WB_WA __SHIFTIN(1,TCR_ORGN1) /* WriteBack WriteAllocate */
808: #define TCR_ORGN1_WT __SHIFTIN(2,TCR_ORGN1) /* WriteThrough */
809: #define TCR_ORGN1_WB __SHIFTIN(3,TCR_ORGN1) /* WriteBack */
810: #define TCR_IRGN1 __BITS(25,24) /* TTBR1 Inner cacheability */
811: #define TCR_IRGN1_NC __SHIFTIN(0,TCR_IRGN1) /* Non Cacheable */
812: #define TCR_IRGN1_WB_WA __SHIFTIN(1,TCR_IRGN1) /* WriteBack WriteAllocate */
813: #define TCR_IRGN1_WT __SHIFTIN(2,TCR_IRGN1) /* WriteThrough */
814: #define TCR_IRGN1_WB __SHIFTIN(3,TCR_IRGN1) /* WriteBack */
815: #define TCR_EPD1 __BIT(23) /* Walk Disable for TTBR1_EL1 */
816: #define TCR_A1 __BIT(22) /* ASID is in TTBR1_EL1 */
817: #define TCR_T1SZ __BITS(21,16) /* Size offset for TTBR1_EL1 */
818: #define TCR_TG0 __BITS(15,14) /* TTBR0 Page Granule Size */
819: #define TCR_TG0_4KB __SHIFTIN(0,TCR_TG0) /* 4KB page size */
820: #define TCR_TG0_64KB __SHIFTIN(1,TCR_TG0) /* 64KB page size */
821: #define TCR_TG0_16KB __SHIFTIN(2,TCR_TG0) /* 16KB page size */
822: #define TCR_SH0 __BITS(13,12)
823: #define TCR_SH0_NONE __SHIFTIN(0,TCR_SH0)
824: #define TCR_SH0_OUTER __SHIFTIN(2,TCR_SH0)
825: #define TCR_SH0_INNER __SHIFTIN(3,TCR_SH0)
826: #define TCR_ORGN0 __BITS(11,10) /* TTBR0 Outer cacheability */
827: #define TCR_ORGN0_NC __SHIFTIN(0,TCR_ORGN0) /* Non Cacheable */
828: #define TCR_ORGN0_WB_WA __SHIFTIN(1,TCR_ORGN0) /* WriteBack WriteAllocate */
829: #define TCR_ORGN0_WT __SHIFTIN(2,TCR_ORGN0) /* WriteThrough */
830: #define TCR_ORGN0_WB __SHIFTIN(3,TCR_ORGN0) /* WriteBack */
831: #define TCR_IRGN0 __BITS(9,8) /* TTBR0 Inner cacheability */
832: #define TCR_IRGN0_NC __SHIFTIN(0,TCR_IRGN0) /* Non Cacheable */
833: #define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */
834: #define TCR_IRGN0_WT __SHIFTIN(2,TCR_IRGN0) /* WriteThrough */
835: #define TCR_IRGN0_WB __SHIFTIN(3,TCR_IRGN0) /* WriteBack */
836: #define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */
837: #define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */
1.1 matt 838:
839: AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1)
840: AARCH64REG_WRITE_INLINE(tpidr_el1)
841:
842: AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0)
843:
1.9 ryo 844: AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL1
1.1 matt 845: AARCH64REG_WRITE_INLINE(ttbr0_el1)
846:
1.9 ryo 847: AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1
1.1 matt 848: AARCH64REG_WRITE_INLINE(ttbr1_el1)
849:
1.27 skrll 850: #define TTBR_ASID __BITS(63,48)
851: #define TTBR_BADDR __BITS(47,0)
852:
1.1 matt 853: AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register
854: AARCH64REG_WRITE_INLINE(vbar_el1)
855:
1.9 ryo 856: /*
857: * From here on, these are DEBUG registers
858: */
859: AARCH64REG_READ_INLINE(dbgbcr0_el1) // Debug Breakpoint Control Register 0
860: AARCH64REG_WRITE_INLINE(dbgbcr0_el1)
861: AARCH64REG_READ_INLINE(dbgbcr1_el1) // Debug Breakpoint Control Register 1
862: AARCH64REG_WRITE_INLINE(dbgbcr1_el1)
863: AARCH64REG_READ_INLINE(dbgbcr2_el1) // Debug Breakpoint Control Register 2
864: AARCH64REG_WRITE_INLINE(dbgbcr2_el1)
865: AARCH64REG_READ_INLINE(dbgbcr3_el1) // Debug Breakpoint Control Register 3
866: AARCH64REG_WRITE_INLINE(dbgbcr3_el1)
867: AARCH64REG_READ_INLINE(dbgbcr4_el1) // Debug Breakpoint Control Register 4
868: AARCH64REG_WRITE_INLINE(dbgbcr4_el1)
869: AARCH64REG_READ_INLINE(dbgbcr5_el1) // Debug Breakpoint Control Register 5
870: AARCH64REG_WRITE_INLINE(dbgbcr5_el1)
871: AARCH64REG_READ_INLINE(dbgbcr6_el1) // Debug Breakpoint Control Register 6
872: AARCH64REG_WRITE_INLINE(dbgbcr6_el1)
873: AARCH64REG_READ_INLINE(dbgbcr7_el1) // Debug Breakpoint Control Register 7
874: AARCH64REG_WRITE_INLINE(dbgbcr7_el1)
875: AARCH64REG_READ_INLINE(dbgbcr8_el1) // Debug Breakpoint Control Register 8
876: AARCH64REG_WRITE_INLINE(dbgbcr8_el1)
877: AARCH64REG_READ_INLINE(dbgbcr9_el1) // Debug Breakpoint Control Register 9
878: AARCH64REG_WRITE_INLINE(dbgbcr9_el1)
879: AARCH64REG_READ_INLINE(dbgbcr10_el1) // Debug Breakpoint Control Register 10
880: AARCH64REG_WRITE_INLINE(dbgbcr10_el1)
881: AARCH64REG_READ_INLINE(dbgbcr11_el1) // Debug Breakpoint Control Register 11
882: AARCH64REG_WRITE_INLINE(dbgbcr11_el1)
883: AARCH64REG_READ_INLINE(dbgbcr12_el1) // Debug Breakpoint Control Register 12
884: AARCH64REG_WRITE_INLINE(dbgbcr12_el1)
885: AARCH64REG_READ_INLINE(dbgbcr13_el1) // Debug Breakpoint Control Register 13
886: AARCH64REG_WRITE_INLINE(dbgbcr13_el1)
887: AARCH64REG_READ_INLINE(dbgbcr14_el1) // Debug Breakpoint Control Register 14
888: AARCH64REG_WRITE_INLINE(dbgbcr14_el1)
889: AARCH64REG_READ_INLINE(dbgbcr15_el1) // Debug Breakpoint Control Register 15
890: AARCH64REG_WRITE_INLINE(dbgbcr15_el1)
891:
1.14 skrll 892: #define DBGBCR_BT __BITS(23,20)
893: #define DBGBCR_LBN __BITS(19,16)
894: #define DBGBCR_SSC __BITS(15,14)
895: #define DBGBCR_HMC __BIT(13)
896: #define DBGBCR_BAS __BITS(8,5)
897: #define DBGBCR_PMC __BITS(2,1)
898: #define DBGBCR_E __BIT(0)
1.9 ryo 899:
900: AARCH64REG_READ_INLINE(dbgbvr0_el1) // Debug Breakpoint Value Register 0
901: AARCH64REG_WRITE_INLINE(dbgbvr0_el1)
902: AARCH64REG_READ_INLINE(dbgbvr1_el1) // Debug Breakpoint Value Register 1
903: AARCH64REG_WRITE_INLINE(dbgbvr1_el1)
904: AARCH64REG_READ_INLINE(dbgbvr2_el1) // Debug Breakpoint Value Register 2
905: AARCH64REG_WRITE_INLINE(dbgbvr2_el1)
906: AARCH64REG_READ_INLINE(dbgbvr3_el1) // Debug Breakpoint Value Register 3
907: AARCH64REG_WRITE_INLINE(dbgbvr3_el1)
908: AARCH64REG_READ_INLINE(dbgbvr4_el1) // Debug Breakpoint Value Register 4
909: AARCH64REG_WRITE_INLINE(dbgbvr4_el1)
910: AARCH64REG_READ_INLINE(dbgbvr5_el1) // Debug Breakpoint Value Register 5
911: AARCH64REG_WRITE_INLINE(dbgbvr5_el1)
912: AARCH64REG_READ_INLINE(dbgbvr6_el1) // Debug Breakpoint Value Register 6
913: AARCH64REG_WRITE_INLINE(dbgbvr6_el1)
914: AARCH64REG_READ_INLINE(dbgbvr7_el1) // Debug Breakpoint Value Register 7
915: AARCH64REG_WRITE_INLINE(dbgbvr7_el1)
916: AARCH64REG_READ_INLINE(dbgbvr8_el1) // Debug Breakpoint Value Register 8
917: AARCH64REG_WRITE_INLINE(dbgbvr8_el1)
918: AARCH64REG_READ_INLINE(dbgbvr9_el1) // Debug Breakpoint Value Register 9
919: AARCH64REG_WRITE_INLINE(dbgbvr9_el1)
920: AARCH64REG_READ_INLINE(dbgbvr10_el1) // Debug Breakpoint Value Register 10
921: AARCH64REG_WRITE_INLINE(dbgbvr10_el1)
922: AARCH64REG_READ_INLINE(dbgbvr11_el1) // Debug Breakpoint Value Register 11
923: AARCH64REG_WRITE_INLINE(dbgbvr11_el1)
924: AARCH64REG_READ_INLINE(dbgbvr12_el1) // Debug Breakpoint Value Register 12
925: AARCH64REG_WRITE_INLINE(dbgbvr12_el1)
926: AARCH64REG_READ_INLINE(dbgbvr13_el1) // Debug Breakpoint Value Register 13
927: AARCH64REG_WRITE_INLINE(dbgbvr13_el1)
928: AARCH64REG_READ_INLINE(dbgbvr14_el1) // Debug Breakpoint Value Register 14
929: AARCH64REG_WRITE_INLINE(dbgbvr14_el1)
930: AARCH64REG_READ_INLINE(dbgbvr15_el1) // Debug Breakpoint Value Register 15
931: AARCH64REG_WRITE_INLINE(dbgbvr15_el1)
932:
933: AARCH64REG_READ_INLINE(dbgwcr0_el1) // Debug Watchpoint Control Register 0
934: AARCH64REG_WRITE_INLINE(dbgwcr0_el1)
935: AARCH64REG_READ_INLINE(dbgwcr1_el1) // Debug Watchpoint Control Register 1
936: AARCH64REG_WRITE_INLINE(dbgwcr1_el1)
937: AARCH64REG_READ_INLINE(dbgwcr2_el1) // Debug Watchpoint Control Register 2
938: AARCH64REG_WRITE_INLINE(dbgwcr2_el1)
939: AARCH64REG_READ_INLINE(dbgwcr3_el1) // Debug Watchpoint Control Register 3
940: AARCH64REG_WRITE_INLINE(dbgwcr3_el1)
941: AARCH64REG_READ_INLINE(dbgwcr4_el1) // Debug Watchpoint Control Register 4
942: AARCH64REG_WRITE_INLINE(dbgwcr4_el1)
943: AARCH64REG_READ_INLINE(dbgwcr5_el1) // Debug Watchpoint Control Register 5
944: AARCH64REG_WRITE_INLINE(dbgwcr5_el1)
945: AARCH64REG_READ_INLINE(dbgwcr6_el1) // Debug Watchpoint Control Register 6
946: AARCH64REG_WRITE_INLINE(dbgwcr6_el1)
947: AARCH64REG_READ_INLINE(dbgwcr7_el1) // Debug Watchpoint Control Register 7
948: AARCH64REG_WRITE_INLINE(dbgwcr7_el1)
949: AARCH64REG_READ_INLINE(dbgwcr8_el1) // Debug Watchpoint Control Register 8
950: AARCH64REG_WRITE_INLINE(dbgwcr8_el1)
951: AARCH64REG_READ_INLINE(dbgwcr9_el1) // Debug Watchpoint Control Register 9
952: AARCH64REG_WRITE_INLINE(dbgwcr9_el1)
953: AARCH64REG_READ_INLINE(dbgwcr10_el1) // Debug Watchpoint Control Register 10
954: AARCH64REG_WRITE_INLINE(dbgwcr10_el1)
955: AARCH64REG_READ_INLINE(dbgwcr11_el1) // Debug Watchpoint Control Register 11
956: AARCH64REG_WRITE_INLINE(dbgwcr11_el1)
957: AARCH64REG_READ_INLINE(dbgwcr12_el1) // Debug Watchpoint Control Register 12
958: AARCH64REG_WRITE_INLINE(dbgwcr12_el1)
959: AARCH64REG_READ_INLINE(dbgwcr13_el1) // Debug Watchpoint Control Register 13
960: AARCH64REG_WRITE_INLINE(dbgwcr13_el1)
961: AARCH64REG_READ_INLINE(dbgwcr14_el1) // Debug Watchpoint Control Register 14
962: AARCH64REG_WRITE_INLINE(dbgwcr14_el1)
963: AARCH64REG_READ_INLINE(dbgwcr15_el1) // Debug Watchpoint Control Register 15
964: AARCH64REG_WRITE_INLINE(dbgwcr15_el1)
965:
1.14 skrll 966: #define DBGWCR_MASK __BITS(28,24)
967: #define DBGWCR_WT __BIT(20)
968: #define DBGWCR_LBN __BITS(19,16)
969: #define DBGWCR_SSC __BITS(15,14)
970: #define DBGWCR_HMC __BIT(13)
971: #define DBGWCR_BAS __BITS(12,5)
972: #define DBGWCR_LSC __BITS(4,3)
973: #define DBGWCR_PAC __BITS(2,1)
974: #define DBGWCR_E __BIT(0)
1.9 ryo 975:
976: AARCH64REG_READ_INLINE(dbgwvr0_el1) // Debug Watchpoint Value Register 0
977: AARCH64REG_WRITE_INLINE(dbgwvr0_el1)
978: AARCH64REG_READ_INLINE(dbgwvr1_el1) // Debug Watchpoint Value Register 1
979: AARCH64REG_WRITE_INLINE(dbgwvr1_el1)
980: AARCH64REG_READ_INLINE(dbgwvr2_el1) // Debug Watchpoint Value Register 2
981: AARCH64REG_WRITE_INLINE(dbgwvr2_el1)
982: AARCH64REG_READ_INLINE(dbgwvr3_el1) // Debug Watchpoint Value Register 3
983: AARCH64REG_WRITE_INLINE(dbgwvr3_el1)
984: AARCH64REG_READ_INLINE(dbgwvr4_el1) // Debug Watchpoint Value Register 4
985: AARCH64REG_WRITE_INLINE(dbgwvr4_el1)
986: AARCH64REG_READ_INLINE(dbgwvr5_el1) // Debug Watchpoint Value Register 5
987: AARCH64REG_WRITE_INLINE(dbgwvr5_el1)
988: AARCH64REG_READ_INLINE(dbgwvr6_el1) // Debug Watchpoint Value Register 6
989: AARCH64REG_WRITE_INLINE(dbgwvr6_el1)
990: AARCH64REG_READ_INLINE(dbgwvr7_el1) // Debug Watchpoint Value Register 7
991: AARCH64REG_WRITE_INLINE(dbgwvr7_el1)
992: AARCH64REG_READ_INLINE(dbgwvr8_el1) // Debug Watchpoint Value Register 8
993: AARCH64REG_WRITE_INLINE(dbgwvr8_el1)
994: AARCH64REG_READ_INLINE(dbgwvr9_el1) // Debug Watchpoint Value Register 9
995: AARCH64REG_WRITE_INLINE(dbgwvr9_el1)
996: AARCH64REG_READ_INLINE(dbgwvr10_el1) // Debug Watchpoint Value Register 10
997: AARCH64REG_WRITE_INLINE(dbgwvr10_el1)
998: AARCH64REG_READ_INLINE(dbgwvr11_el1) // Debug Watchpoint Value Register 11
999: AARCH64REG_WRITE_INLINE(dbgwvr11_el1)
1000: AARCH64REG_READ_INLINE(dbgwvr12_el1) // Debug Watchpoint Value Register 12
1001: AARCH64REG_WRITE_INLINE(dbgwvr12_el1)
1002: AARCH64REG_READ_INLINE(dbgwvr13_el1) // Debug Watchpoint Value Register 13
1003: AARCH64REG_WRITE_INLINE(dbgwvr13_el1)
1004: AARCH64REG_READ_INLINE(dbgwvr14_el1) // Debug Watchpoint Value Register 14
1005: AARCH64REG_WRITE_INLINE(dbgwvr14_el1)
1006: AARCH64REG_READ_INLINE(dbgwvr15_el1) // Debug Watchpoint Value Register 15
1007: AARCH64REG_WRITE_INLINE(dbgwvr15_el1)
1008:
1.14 skrll 1009: #define DBGWVR_MASK __BITS(64,3)
1.9 ryo 1010:
1011:
1012: AARCH64REG_READ_INLINE(mdscr_el1) // Monitor Debug System Control Register
1013: AARCH64REG_WRITE_INLINE(mdscr_el1)
1014:
1.22 ryo 1015: #define MDSCR_RXFULL __BIT(30) // for EDSCR.RXfull
1016: #define MDSCR_TXFULL __BIT(29) // for EDSCR.TXfull
1017: #define MDSCR_RXO __BIT(27) // for EDSCR.RXO
1018: #define MDSCR_TXU __BIT(26) // for EDSCR.TXU
1019: #define MDSCR_INTDIS __BITS(32,22) // for EDSCR.INTdis
1020: #define MDSCR_TDA __BIT(21) // for EDSCR.TDA
1021: #define MDSCR_MDE __BIT(15) // Monitor debug events
1022: #define MDSCR_HDE __BIT(14) // for EDSCR.HDE
1023: #define MDSCR_KDE __BIT(13) // Local debug enable
1024: #define MDSCR_TDCC __BIT(12) // Trap Debug CommCh access
1025: #define MDSCR_ERR __BIT(6) // for EDSCR.ERR
1026: #define MDSCR_SS __BIT(0) // Software step
1027:
1.9 ryo 1028: AARCH64REG_WRITE_INLINE(oslar_el1) // OS Lock Access Register
1029:
1030: AARCH64REG_READ_INLINE(oslsr_el1) // OS Lock Status Register
1031:
1032: /*
1033: * From here on, these are PMC registers
1034: */
1035:
1.1 matt 1036: AARCH64REG_READ_INLINE(pmccfiltr_el0)
1037: AARCH64REG_WRITE_INLINE(pmccfiltr_el0)
1038:
1.14 skrll 1039: #define PMCCFILTR_P __BIT(31) // Don't count cycles in EL1
1040: #define PMCCFILTR_U __BIT(30) // Don't count cycles in EL0
1041: #define PMCCFILTR_NSK __BIT(29) // Don't count cycles in NS EL1
1042: #define PMCCFILTR_NSU __BIT(28) // Don't count cycles in NS EL0
1043: #define PMCCFILTR_NSH __BIT(27) // Don't count cycles in NS EL2
1044: #define PMCCFILTR_M __BIT(26) // Don't count cycles in EL3
1.1 matt 1045:
1046: AARCH64REG_READ_INLINE(pmccntr_el0)
1047:
1.12 christos 1048: AARCH64REG_READ_INLINE(pmceid0_el0)
1049: AARCH64REG_READ_INLINE(pmceid1_el0)
1.11 jmcneill 1050:
1.12 christos 1051: AARCH64REG_WRITE_INLINE(pmcntenclr_el0)
1052: AARCH64REG_WRITE_INLINE(pmcntenset_el0)
1.11 jmcneill 1053:
1054: AARCH64REG_READ_INLINE(pmcr_el0)
1055: AARCH64REG_WRITE_INLINE(pmcr_el0)
1056:
1.14 skrll 1057: #define PMCR_IMP __BITS(31,24) // Implementor code
1058: #define PMCR_IDCODE __BITS(23,16) // Identification code
1059: #define PMCR_N __BITS(15,11) // Number of event counters
1060: #define PMCR_LC __BIT(6) // Long cycle counter enable
1061: #define PMCR_DP __BIT(5) // Disable cycle counter when event
1062: // counting is prohibited
1063: #define PMCR_X __BIT(4) // Enable export of events
1064: #define PMCR_D __BIT(3) // Clock divider
1065: #define PMCR_C __BIT(2) // Cycle counter reset
1066: #define PMCR_P __BIT(1) // Event counter reset
1067: #define PMCR_E __BIT(0) // Enable
1.11 jmcneill 1068:
1069:
1.12 christos 1070: AARCH64REG_READ_INLINE(pmevcntr1_el0)
1071: AARCH64REG_WRITE_INLINE(pmevcntr1_el0)
1.11 jmcneill 1072:
1073: AARCH64REG_READ_INLINE(pmevtyper1_el0)
1074: AARCH64REG_WRITE_INLINE(pmevtyper1_el0)
1075:
1.14 skrll 1076: #define PMEVTYPER_P __BIT(31) // Don't count events in EL1
1077: #define PMEVTYPER_U __BIT(30) // Don't count events in EL0
1078: #define PMEVTYPER_NSK __BIT(29) // Don't count events in NS EL1
1079: #define PMEVTYPER_NSU __BIT(28) // Don't count events in NS EL0
1080: #define PMEVTYPER_NSH __BIT(27) // Count events in NS EL2
1081: #define PMEVTYPER_M __BIT(26) // Don't count events in EL3
1082: #define PMEVTYPER_MT __BIT(25) // Count events on all CPUs with same
1083: // aff1 level
1084: #define PMEVTYPER_EVTCOUNT __BITS(15,0) // Event to count
1.11 jmcneill 1085:
1.12 christos 1086: AARCH64REG_WRITE_INLINE(pmintenclr_el1)
1087: AARCH64REG_WRITE_INLINE(pmintenset_el1)
1.11 jmcneill 1088:
1.12 christos 1089: AARCH64REG_WRITE_INLINE(pmovsclr_el0)
1090: AARCH64REG_READ_INLINE(pmovsset_el0)
1091: AARCH64REG_WRITE_INLINE(pmovsset_el0)
1.11 jmcneill 1092:
1.12 christos 1093: AARCH64REG_WRITE_INLINE(pmselr_el0)
1.11 jmcneill 1094:
1.12 christos 1095: AARCH64REG_WRITE_INLINE(pmswinc_el0)
1.11 jmcneill 1096:
1.12 christos 1097: AARCH64REG_READ_INLINE(pmuserenr_el0)
1098: AARCH64REG_WRITE_INLINE(pmuserenr_el0)
1.11 jmcneill 1099:
1.12 christos 1100: AARCH64REG_READ_INLINE(pmxevcntr_el0)
1101: AARCH64REG_WRITE_INLINE(pmxevcntr_el0)
1.11 jmcneill 1102:
1.12 christos 1103: AARCH64REG_READ_INLINE(pmxevtyper_el0)
1104: AARCH64REG_WRITE_INLINE(pmxevtyper_el0)
1.11 jmcneill 1105:
1106: /*
1107: * Generic timer registers
1108: */
1109:
1.1 matt 1110: AARCH64REG_READ_INLINE(cntfrq_el0)
1111:
1.9 ryo 1112: AARCH64REG_READ_INLINE(cnthctl_el2)
1113: AARCH64REG_WRITE_INLINE(cnthctl_el2)
1114:
1.14 skrll 1115: #define CNTHCTL_EVNTDIR __BIT(3)
1116: #define CNTHCTL_EVNTEN __BIT(2)
1117: #define CNTHCTL_EL1PCEN __BIT(1)
1118: #define CNTHCTL_EL1PCTEN __BIT(0)
1.9 ryo 1119:
1.1 matt 1120: AARCH64REG_READ_INLINE(cntkctl_el1)
1121: AARCH64REG_WRITE_INLINE(cntkctl_el1)
1122:
1.14 skrll 1123: #define CNTKCTL_EL0PTEN __BIT(9) // EL0 access for CNTP CVAL/TVAL/CTL
1124: #define CNTKCTL_PL0PTEN CNTKCTL_EL0PTEN
1125: #define CNTKCTL_EL0VTEN __BIT(8) // EL0 access for CNTV CVAL/TVAL/CTL
1126: #define CNTKCTL_PL0VTEN CNTKCTL_EL0VTEN
1127: #define CNTKCTL_ELNTI __BITS(7,4)
1128: #define CNTKCTL_EVNTDIR __BIT(3)
1129: #define CNTKCTL_EVNTEN __BIT(2)
1130: #define CNTKCTL_EL0VCTEN __BIT(1) // EL0 access for CNTVCT and CNTFRQ
1131: #define CNTKCTL_PL0VCTEN CNTKCTL_EL0VCTEN
1132: #define CNTKCTL_EL0PCTEN __BIT(0) // EL0 access for CNTPCT and CNTFRQ
1133: #define CNTKCTL_PL0PCTEN CNTKCTL_EL0PCTEN
1.1 matt 1134:
1135: AARCH64REG_READ_INLINE(cntp_ctl_el0)
1136: AARCH64REG_WRITE_INLINE(cntp_ctl_el0)
1137: AARCH64REG_READ_INLINE(cntp_cval_el0)
1138: AARCH64REG_WRITE_INLINE(cntp_cval_el0)
1139: AARCH64REG_READ_INLINE(cntp_tval_el0)
1140: AARCH64REG_WRITE_INLINE(cntp_tval_el0)
1141: AARCH64REG_READ_INLINE(cntpct_el0)
1142: AARCH64REG_WRITE_INLINE(cntpct_el0)
1143:
1144: AARCH64REG_READ_INLINE(cntps_ctl_el1)
1145: AARCH64REG_WRITE_INLINE(cntps_ctl_el1)
1146: AARCH64REG_READ_INLINE(cntps_cval_el1)
1147: AARCH64REG_WRITE_INLINE(cntps_cval_el1)
1148: AARCH64REG_READ_INLINE(cntps_tval_el1)
1149: AARCH64REG_WRITE_INLINE(cntps_tval_el1)
1150:
1151: AARCH64REG_READ_INLINE(cntv_ctl_el0)
1152: AARCH64REG_WRITE_INLINE(cntv_ctl_el0)
1153: AARCH64REG_READ_INLINE(cntv_cval_el0)
1154: AARCH64REG_WRITE_INLINE(cntv_cval_el0)
1155: AARCH64REG_READ_INLINE(cntv_tval_el0)
1156: AARCH64REG_WRITE_INLINE(cntv_tval_el0)
1157: AARCH64REG_READ_INLINE(cntvct_el0)
1158: AARCH64REG_WRITE_INLINE(cntvct_el0)
1159:
1.14 skrll 1160: #define CNTCTL_ISTATUS __BIT(2) // Interrupt Asserted
1161: #define CNTCTL_IMASK __BIT(1) // Timer Interrupt is Masked
1162: #define CNTCTL_ENABLE __BIT(0) // Timer Enabled
1.1 matt 1163:
1.9 ryo 1164: // ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0
1.12 christos 1165: #define ID_AA64PFR0_EL1_GIC __BITS(24,27) // GIC CPU IF
1166: #define ID_AA64PFR0_EL1_GIC_SHIFT 24
1.14 skrll 1167: #define ID_AA64PFR0_EL1_GIC_CPUIF_EN 1
1168: #define ID_AA64PFR0_EL1_GIC_CPUIF_NONE 0
1.12 christos 1169: #define ID_AA64PFR0_EL1_ADVSIMD __BITS(23,20) // SIMD
1.14 skrll 1170: #define ID_AA64PFR0_EL1_ADV_SIMD_IMPL 0x0
1171: #define ID_AA64PFR0_EL1_ADV_SIMD_NONE 0xf
1.12 christos 1172: #define ID_AA64PFR0_EL1_FP __BITS(19,16) // FP
1.14 skrll 1173: #define ID_AA64PFR0_EL1_FP_IMPL 0x0
1174: #define ID_AA64PFR0_EL1_FP_NONE 0xf
1.12 christos 1175: #define ID_AA64PFR0_EL1_EL3 __BITS(15,12) // EL3 handling
1.14 skrll 1176: #define ID_AA64PFR0_EL1_EL3_NONE 0
1177: #define ID_AA64PFR0_EL1_EL3_64 1
1178: #define ID_AA64PFR0_EL1_EL3_64_32 2
1.12 christos 1179: #define ID_AA64PFR0_EL1_EL2 __BITS(11,8) // EL2 handling
1.14 skrll 1180: #define ID_AA64PFR0_EL1_EL2_NONE 0
1181: #define ID_AA64PFR0_EL1_EL2_64 1
1182: #define ID_AA64PFR0_EL1_EL2_64_32 2
1.12 christos 1183: #define ID_AA64PFR0_EL1_EL1 __BITS(7,4) // EL1 handling
1.14 skrll 1184: #define ID_AA64PFR0_EL1_EL1_64 1
1185: #define ID_AA64PFR0_EL1_EL1_64_32 2
1.12 christos 1186: #define ID_AA64PFR0_EL1_EL0 __BITS(3,0) // EL0 handling
1.14 skrll 1187: #define ID_AA64PFR0_EL1_EL0_64 1
1188: #define ID_AA64PFR0_EL1_EL0_64_32 2
1.9 ryo 1189:
1.15 jmcneill 1190: /*
1191: * GICv3 system registers
1192: */
1193: AARCH64REG_READWRITE_INLINE2(icc_sre_el1, s3_0_c12_c12_5)
1194: AARCH64REG_READWRITE_INLINE2(icc_ctlr_el1, s3_0_c12_c12_4)
1195: AARCH64REG_READWRITE_INLINE2(icc_pmr_el1, s3_0_c4_c6_0)
1196: AARCH64REG_READWRITE_INLINE2(icc_bpr0_el1, s3_0_c12_c8_3)
1197: AARCH64REG_READWRITE_INLINE2(icc_bpr1_el1, s3_0_c12_c12_3)
1198: AARCH64REG_READWRITE_INLINE2(icc_igrpen0_el1, s3_0_c12_c12_6)
1199: AARCH64REG_READWRITE_INLINE2(icc_igrpen1_el1, s3_0_c12_c12_7)
1200: AARCH64REG_READWRITE_INLINE2(icc_eoir0_el1, s3_0_c12_c8_1)
1201: AARCH64REG_READWRITE_INLINE2(icc_eoir1_el1, s3_0_c12_c12_1)
1202: AARCH64REG_READWRITE_INLINE2(icc_sgi1r_el1, s3_0_c12_c11_5)
1203: AARCH64REG_READ_INLINE2(icc_iar1_el1, s3_0_c12_c12_0)
1204:
1.9 ryo 1205: // ICC_SRE_EL1: Interrupt Controller System Register Enable register
1.15 jmcneill 1206: #define ICC_SRE_EL1_DIB __BIT(2)
1207: #define ICC_SRE_EL1_DFB __BIT(1)
1208: #define ICC_SRE_EL1_SRE __BIT(0)
1209:
1.16 jmcneill 1210: // ICC_SRE_EL2: Interrupt Controller System Register Enable register
1211: #define ICC_SRE_EL2_EN __BIT(3)
1212: #define ICC_SRE_EL2_DIB __BIT(2)
1213: #define ICC_SRE_EL2_DFB __BIT(1)
1214: #define ICC_SRE_EL2_SRE __BIT(0)
1215:
1.15 jmcneill 1216: // ICC_BPR[01]_EL1: Interrupt Controller Binary Point Register 0/1
1217: #define ICC_BPR_EL1_BinaryPoint __BITS(2,0)
1218:
1219: // ICC_CTLR_EL1: Interrupt Controller Control Register
1220: #define ICC_CTLR_EL1_A3V __BIT(15)
1221: #define ICC_CTLR_EL1_SEIS __BIT(14)
1222: #define ICC_CTLR_EL1_IDbits __BITS(13,11)
1223: #define ICC_CTLR_EL1_PRIbits __BITS(10,8)
1224: #define ICC_CTLR_EL1_PMHE __BIT(6)
1225: #define ICC_CTLR_EL1_EOImode __BIT(1)
1226: #define ICC_CTLR_EL1_CBPR __BIT(0)
1227:
1228: // ICC_IGRPEN[01]_EL1: Interrupt Controller Interrupt Group 0/1 Enable register
1229: #define ICC_IGRPEN_EL1_Enable __BIT(0)
1230:
1231: // ICC_SGI[01]R_EL1: Interrupt Controller Software Generated Interrupt Group 0/1 Register
1232: #define ICC_SGIR_EL1_Aff3 __BITS(55,48)
1233: #define ICC_SGIR_EL1_IRM __BIT(40)
1234: #define ICC_SGIR_EL1_Aff2 __BITS(39,32)
1235: #define ICC_SGIR_EL1_INTID __BITS(27,24)
1236: #define ICC_SGIR_EL1_Aff1 __BITS(23,16)
1237: #define ICC_SGIR_EL1_TargetList __BITS(15,0)
1238: #define ICC_SGIR_EL1_Aff (ICC_SGIR_EL1_Aff3|ICC_SGIR_EL1_Aff2|ICC_SGIR_EL1_Aff1)
1239:
1240: // ICC_IAR[01]_EL1: Interrupt Controller Interrupt Acknowledge Register 0/1
1241: #define ICC_IAR_INTID __BITS(23,0)
1242: #define ICC_IAR_INTID_SPURIOUS 1023
1243:
1244: /*
1245: * GICv3 REGISTER ACCESS
1246: */
1.9 ryo 1247:
1.15 jmcneill 1248: #define icc_sre_read reg_icc_sre_el1_read
1249: #define icc_sre_write reg_icc_sre_el1_write
1.25 skrll 1250: #define icc_pmr_read reg_icc_pmr_el1_read
1.15 jmcneill 1251: #define icc_pmr_write reg_icc_pmr_el1_write
1252: #define icc_bpr0_write reg_icc_bpr0_el1_write
1253: #define icc_bpr1_write reg_icc_bpr1_el1_write
1254: #define icc_ctlr_read reg_icc_ctlr_el1_read
1255: #define icc_ctlr_write reg_icc_ctlr_el1_write
1256: #define icc_igrpen1_write reg_icc_igrpen1_el1_write
1257: #define icc_sgi1r_write reg_icc_sgi1r_el1_write
1258: #define icc_iar1_read reg_icc_iar1_el1_read
1259: #define icc_eoi1r_write reg_icc_eoir1_el1_write
1.9 ryo 1260:
1.18 skrll 1261: #if defined(_KERNEL)
1262:
1263: /*
1264: * CPU REGISTER ACCESS
1265: */
1266: static __inline register_t
1267: cpu_mpidr_aff_read(void)
1268: {
1269:
1270: return reg_mpidr_el1_read() &
1271: (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0);
1272: }
1273:
1.9 ryo 1274: /*
1275: * GENERIC TIMER REGISTER ACCESS
1276: */
1.12 christos 1277: static __inline uint32_t
1.9 ryo 1278: gtmr_cntfrq_read(void)
1279: {
1280:
1281: return reg_cntfrq_el0_read();
1282: }
1283:
1.12 christos 1284: static __inline uint32_t
1.9 ryo 1285: gtmr_cntk_ctl_read(void)
1286: {
1.1 matt 1287:
1.9 ryo 1288: return reg_cntkctl_el1_read();
1289: }
1290:
1.12 christos 1291: static __inline void
1.9 ryo 1292: gtmr_cntk_ctl_write(uint32_t val)
1293: {
1294:
1295: reg_cntkctl_el1_write(val);
1296: }
1297:
1298: /*
1299: * Counter-timer Virtual Count timer
1300: */
1.12 christos 1301: static __inline uint64_t
1.9 ryo 1302: gtmr_cntpct_read(void)
1303: {
1304:
1305: return reg_cntpct_el0_read();
1306: }
1307:
1.12 christos 1308: static __inline uint64_t
1.9 ryo 1309: gtmr_cntvct_read(void)
1310: {
1311:
1312: return reg_cntvct_el0_read();
1313: }
1314:
1315: /*
1316: * Counter-timer Virtual Timer Control register
1317: */
1.12 christos 1318: static __inline uint32_t
1.9 ryo 1319: gtmr_cntv_ctl_read(void)
1320: {
1321:
1322: return reg_cntv_ctl_el0_read();
1323: }
1324:
1.12 christos 1325: static __inline void
1.9 ryo 1326: gtmr_cntv_ctl_write(uint32_t val)
1327: {
1328:
1329: reg_cntv_ctl_el0_write(val);
1330: }
1331:
1.26 jmcneill 1332: /*
1333: * Counter-timer Physical Timer Control register
1334: */
1335: static __inline uint32_t
1336: gtmr_cntp_ctl_read(void)
1337: {
1338:
1339: return reg_cntp_ctl_el0_read();
1340: }
1341:
1.12 christos 1342: static __inline void
1.9 ryo 1343: gtmr_cntp_ctl_write(uint32_t val)
1344: {
1345:
1346: reg_cntp_ctl_el0_write(val);
1347: }
1348:
1349: /*
1.26 jmcneill 1350: * Counter-timer Physical Timer TimerValue register
1351: */
1352: static __inline uint32_t
1353: gtmr_cntp_tval_read(void)
1354: {
1355:
1356: return reg_cntp_tval_el0_read();
1357: }
1358:
1359: static __inline void
1360: gtmr_cntp_tval_write(uint32_t val)
1361: {
1362:
1363: reg_cntp_tval_el0_write(val);
1364: }
1365:
1366: /*
1.9 ryo 1367: * Counter-timer Virtual Timer TimerValue register
1368: */
1.12 christos 1369: static __inline uint32_t
1.10 joerg 1370: gtmr_cntv_tval_read(void)
1371: {
1372:
1373: return reg_cntv_tval_el0_read();
1374: }
1375:
1.12 christos 1376: static __inline void
1.9 ryo 1377: gtmr_cntv_tval_write(uint32_t val)
1378: {
1379:
1380: reg_cntv_tval_el0_write(val);
1381: }
1382:
1.26 jmcneill 1383: /*
1384: * Counter-timer Physical Timer CompareValue register
1385: */
1386: static __inline uint64_t
1387: gtmr_cntp_cval_read(void)
1388: {
1389:
1390: return reg_cntp_cval_el0_read();
1391: }
1392:
1393: static __inline void
1394: gtmr_cntp_cval_write(uint64_t val)
1395: {
1396:
1397: reg_cntp_cval_el0_write(val);
1398: }
1.9 ryo 1399:
1400: /*
1401: * Counter-timer Virtual Timer CompareValue register
1402: */
1.12 christos 1403: static __inline uint64_t
1.9 ryo 1404: gtmr_cntv_cval_read(void)
1405: {
1406:
1407: return reg_cntv_cval_el0_read();
1408: }
1.23 jmcneill 1409:
1410: static __inline void
1411: gtmr_cntv_cval_write(uint64_t val)
1412: {
1413:
1414: reg_cntv_cval_el0_write(val);
1415: }
1.18 skrll 1416: #endif /* _KERNEL */
1.1 matt 1417:
1.21 mrg 1418: /*
1419: * Structure attached to machdep.cpuN.cpu_id sysctl node.
1420: * Always add new members to the end, and avoid arrays.
1421: */
1422: struct aarch64_sysctl_cpu_id {
1423: uint64_t ac_midr; /* Main ID Register */
1424: uint64_t ac_revidr; /* Revision ID Register */
1425: uint64_t ac_mpidr; /* Multiprocessor Affinity Register */
1426:
1427: uint64_t ac_aa64dfr0; /* A64 Debug Feature Register 0 */
1428: uint64_t ac_aa64dfr1; /* A64 Debug Feature Register 1 */
1429:
1430: uint64_t ac_aa64isar0; /* A64 Instruction Set Attribute Register 0 */
1431: uint64_t ac_aa64isar1; /* A64 Instruction Set Attribute Register 1 */
1432:
1.30 rjs 1433: uint64_t ac_aa64mmfr0; /* A64 Memory Model Feature Register 0 */
1434: uint64_t ac_aa64mmfr1; /* A64 Memory Model Feature Register 1 */
1435: uint64_t ac_aa64mmfr2; /* A64 Memory Model Feature Register 2 */
1.21 mrg 1436:
1437: uint64_t ac_aa64pfr0; /* A64 Processor Feature Register 0 */
1438: uint64_t ac_aa64pfr1; /* A64 Processor Feature Register 1 */
1439:
1440: uint64_t ac_aa64zfr0; /* A64 SVE Feature ID Register 0 */
1441:
1442: uint32_t ac_mvfr0; /* Media and VFP Feature Register 0 */
1443: uint32_t ac_mvfr1; /* Media and VFP Feature Register 1 */
1444: uint32_t ac_mvfr2; /* Media and VFP Feature Register 2 */
1445: };
1446:
1.1 matt 1447: #endif /* _AARCH64_ARMREG_H_ */
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