version 1.17, 2018/08/12 17:16:18 |
version 1.18, 2018/08/12 17:21:35 |
Line 1025 AARCH64REG_READ_INLINE2(icc_iar1_el1, s3 |
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Line 1025 AARCH64REG_READ_INLINE2(icc_iar1_el1, s3 |
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#define icc_iar1_read reg_icc_iar1_el1_read |
#define icc_iar1_read reg_icc_iar1_el1_read |
#define icc_eoi1r_write reg_icc_eoir1_el1_write |
#define icc_eoi1r_write reg_icc_eoir1_el1_write |
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#if defined(_KERNEL) |
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/* |
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* CPU REGISTER ACCESS |
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*/ |
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static __inline register_t |
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cpu_mpidr_aff_read(void) |
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{ |
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return reg_mpidr_el1_read() & |
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(MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0); |
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} |
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/* |
/* |
* GENERIC TIMER REGISTER ACCESS |
* GENERIC TIMER REGISTER ACCESS |
*/ |
*/ |
Line 1117 gtmr_cntv_cval_read(void) |
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Line 1130 gtmr_cntv_cval_read(void) |
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return reg_cntv_cval_el0_read(); |
return reg_cntv_cval_el0_read(); |
} |
} |
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#endif /* _KERNEL */ |
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#endif /* _AARCH64_ARMREG_H_ */ |
#endif /* _AARCH64_ARMREG_H_ */ |