CVS log for src/sys/arch/aarch64/include/armreg.h

Up to [cvs.NetBSD.org] / src / sys / arch / aarch64 / include

Request diff between arbitrary revisions

Default branch: MAIN

Revision 1.63 / (download) - annotate - [select for diffs], Thu Dec 1 00:32:52 2022 UTC (3 months, 3 weeks ago) by ryo
Branch: MAIN
CVS Tags: netbsd-10-base, netbsd-10, HEAD
Changes since 1.62: +6 -1 lines
Diff to previous 1.62 (colored)

Improve tprof(4)

- Multiple events can now be handled simultaneously.
- Counters should be configured with TPROF_IOC_CONFIGURE_EVENT in advance,
  instead of being configured at TPROF_IOC_START.
- The configured counters can be started and stopped repeatedly by
  PROF_IOC_START/TPROF_IOC_STOP.
- The value of the performance counter can be obtained at any timing as a 64bit
  value with TPROF_IOC_GETCOUNTS.
- Backend common parts are handled in tprof.c as much as possible, and functions
  on the tprof_backend side have been reimplemented to be more primitive.
- The reset value of counter overflows for profiling can now be adjusted.
  It is calculated by default from the CPU clock (speed of cycle counter) and
  TPROF_HZ, but for some events the value may be too large to be sufficient for
  profiling. The event counter can be specified as a ratio to the default or as
  an absolute value when configuring the event counter.
- Due to overall changes, API and ABI have been changed. TPROF_VERSION and
  TPROF_BACKEND_VERSION were updated.

Revision 1.62 / (download) - annotate - [select for diffs], Thu Dec 1 00:29:10 2022 UTC (3 months, 3 weeks ago) by ryo
Branch: MAIN
Changes since 1.61: +7 -1 lines
Diff to previous 1.61 (colored)

PMCR.E should not be disabled from tprof.

PMCR.E controls not only performance event counters but also the cycle
counter operation, and the cycle counter may be used for cpu_counter.
Similarly, the 31st bit in PMINTENCLR and PMCNTENCLR controls the cycle
counter, not performance event counters, and should not be modified.

Revision 1.61 / (download) - annotate - [select for diffs], Mon May 2 10:13:15 2022 UTC (10 months, 3 weeks ago) by skrll
Branch: MAIN
CVS Tags: bouyer-sunxi-drm-base, bouyer-sunxi-drm
Changes since 1.60: +6 -5 lines
Diff to previous 1.60 (colored)

Only print the appropriate PAR fields for PAR.F={0,1}

Group the fields in the header.

Revision 1.60 / (download) - annotate - [select for diffs], Wed Jan 5 19:53:32 2022 UTC (14 months, 2 weeks ago) by ryo
Branch: MAIN
Changes since 1.59: +2 -2 lines
Diff to previous 1.59 (colored)

fix ID_AA64ISAR0_EL1.ATOMIC field definition

Revision 1.59 / (download) - annotate - [select for diffs], Tue Oct 26 16:58:46 2021 UTC (16 months, 4 weeks ago) by ryo
Branch: MAIN
Changes since 1.58: +3 -3 lines
Diff to previous 1.58 (colored)

fix build with COPTS=-O0

Revision 1.58 / (download) - annotate - [select for diffs], Sat Oct 23 05:31:53 2021 UTC (17 months ago) by skrll
Branch: MAIN
Changes since 1.57: +2 -2 lines
Diff to previous 1.57 (colored)

Typo in comment

Revision 1.55.4.1 / (download) - annotate - [select for diffs], Sun Aug 1 22:42:00 2021 UTC (19 months, 3 weeks ago) by thorpej
Branch: thorpej-i2c-spi-conf
Changes since 1.55: +4 -3 lines
Diff to previous 1.55 (colored) next main 1.56 (colored)

Sync with HEAD.

Revision 1.57 / (download) - annotate - [select for diffs], Sat Jun 19 13:40:00 2021 UTC (21 months, 1 week ago) by jmcneill
Branch: MAIN
CVS Tags: thorpej-i2c-spi-conf2-base, thorpej-i2c-spi-conf2, thorpej-i2c-spi-conf-base, thorpej-futex2-base, thorpej-futex2, thorpej-cfargs2-base, thorpej-cfargs2
Changes since 1.56: +2 -1 lines
Diff to previous 1.56 (colored)

Do not try to initialize PMU if ID_AA64DFR0_EL1 reports a non-standard
PMU implementation.

Revision 1.56 / (download) - annotate - [select for diffs], Sat Jun 19 13:38:21 2021 UTC (21 months, 1 week ago) by jmcneill
Branch: MAIN
Changes since 1.55: +3 -3 lines
Diff to previous 1.55 (colored)

CNTV_CTL_EL0 is a 64-bit register

Revision 1.54.2.1 / (download) - annotate - [select for diffs], Sat Apr 3 22:28:13 2021 UTC (23 months, 3 weeks ago) by thorpej
Branch: thorpej-futex
Changes since 1.54: +4 -2 lines
Diff to previous 1.54 (colored) next main 1.55 (colored)

Sync with HEAD.

Revision 1.55 / (download) - annotate - [select for diffs], Tue Mar 9 16:41:43 2021 UTC (2 years ago) by ryo
Branch: MAIN
CVS Tags: thorpej-futex-base, thorpej-cfargs-base, thorpej-cfargs, cjep_sun2x-base1, cjep_sun2x-base, cjep_sun2x, cjep_staticlib_x-base1, cjep_staticlib_x-base, cjep_staticlib_x
Branch point for: thorpej-i2c-spi-conf
Changes since 1.54: +4 -2 lines
Diff to previous 1.54 (colored)

fixed mask width of DBGWVR_MASK, and added definition of DBGBVR_MASK

Revision 1.54 / (download) - annotate - [select for diffs], Wed Sep 30 08:40:49 2020 UTC (2 years, 5 months ago) by ryo
Branch: MAIN
Branch point for: thorpej-futex
Changes since 1.53: +10 -1 lines
Diff to previous 1.53 (colored)

add some fields of ID_AA64ISAR1_EL1 definition (ARMv8.6)

Revision 1.53 / (download) - annotate - [select for diffs], Tue Sep 15 09:28:21 2020 UTC (2 years, 6 months ago) by ryo
Branch: MAIN
Changes since 1.52: +2 -2 lines
Diff to previous 1.52 (colored)

fix typo

Revision 1.52 / (download) - annotate - [select for diffs], Sun Aug 2 06:58:16 2020 UTC (2 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.51: +5 -1 lines
Diff to previous 1.51 (colored)

Add support for Privileged Access Never (ARMv8.1-PAN).

PAN provides the same functionality as SMAP on x86: it forbids kernel
access to userland pages when PSTATE.PAN=1, and allows such accesses when
PSTATE.PAN=0.

We clear SCTLR_SPAN, to guarantee that PAN=1 each time the kernel is
entered. We catch PAN faults and panic right away without further
processing. In copyin, copyout, etc, we temporarily authorize access to
userland pages.

PAN is a very useful exploit mitigation. Reviewed by ryo@, thanks. Tested
on Qemu. Enabled by default.

Revision 1.51 / (download) - annotate - [select for diffs], Sat Aug 1 08:47:05 2020 UTC (2 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.50: +8 -4 lines
Diff to previous 1.50 (colored)

The system registers we modify can have an impact on memory accesses, and
we don't want the compiler to randomly re-order the instructions, so add
barriers. Same as WRMSR on x86.

Revision 1.50 / (download) - annotate - [select for diffs], Wed Jul 1 08:01:07 2020 UTC (2 years, 8 months ago) by ryo
Branch: MAIN
Changes since 1.49: +5 -1 lines
Diff to previous 1.49 (colored)

- On some systems with a different cache line size (and DIC,IDC) per CPU, trap "mrs Xt,ctr_el0" instruction
  to return the minimum cache line size of the system to userland.
- add CLIDR_EL1 and CTR_EL0 to struct aarch64_sysctl_cpu_id.

On most systems, cache line size is the same for all CPUs, so this mechanism won't be required.
Rather, this is primarily for errata support, which will be committed later.

Revision 1.49 / (download) - annotate - [select for diffs], Sun Jun 14 16:10:18 2020 UTC (2 years, 9 months ago) by riastradh
Branch: MAIN
Changes since 1.48: +21 -1 lines
Diff to previous 1.48 (colored)

Add some more id_aa64pfr0_el1 bits.

Revision 1.48 / (download) - annotate - [select for diffs], Thu May 28 12:41:15 2020 UTC (2 years, 9 months ago) by skrll
Branch: MAIN
Changes since 1.47: +4 -1 lines
Diff to previous 1.47 (colored)

Add some new CTR_EL0 bits

Revision 1.47 / (download) - annotate - [select for diffs], Mon May 25 05:17:05 2020 UTC (2 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.46: +21 -1 lines
Diff to previous 1.46 (colored)

add ARMv8.1-8.5 definitions of TCR_EL1

Revision 1.46 / (download) - annotate - [select for diffs], Mon May 25 05:13:16 2020 UTC (2 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.45: +7 -1 lines
Diff to previous 1.45 (colored)

cache information can be detected correctly on newer CPUs

- add VPIPT cache type
- adapt to 64-bit CCSIDR (ARMv8.3-CCIDX)
- CCSIDR:[WT,WB,PA,WA] are deprecated
- show number of cache lines when attaching cpu

Revision 1.45 / (download) - annotate - [select for diffs], Sat May 23 18:08:59 2020 UTC (2 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.44: +21 -1 lines
Diff to previous 1.44 (colored)

Not only the kernel thread, but also the userland PAC keys
(APIA,APIB,APDA,APDB,APGA) are now randomly initialized at exec, and switched
when context switch.
userland programs are able to perform pointer authentication on ARMv8.3+PAC cpu.

reviewd by maxv@, thanks.

Revision 1.44 / (download) - annotate - [select for diffs], Thu May 21 05:04:13 2020 UTC (2 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.43: +2 -2 lines
Diff to previous 1.43 (colored)

fix typo

Revision 1.43 / (download) - annotate - [select for diffs], Wed May 13 06:08:51 2020 UTC (2 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.42: +1 -12 lines
Diff to previous 1.42 (colored)

- move aarch64 addressspace macros from pmap.h to cpufunc.h
- rename ptr_strip_pac() to aarch64_strip_pac()

Revision 1.42 / (download) - annotate - [select for diffs], Mon May 11 03:00:57 2020 UTC (2 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.41: +29 -22 lines
Diff to previous 1.41 (colored)

"options ARMV83_PAC" is now supported for gcc as well.

- add "-msign-return-address=all" to CFLAGS for gcc when specified options ARMV83_PAC
- AARCH64REG_{READ,WRITE}_INLINE3 macro can now use the APIAKey registers in both gcc and llvm.
  llvm requires asm(".arch armv8.3-a"), whereas gcc requires __attribute__((target("arch=armv8.3-a"))).
- use ".arch armv8.3-a" rather than ".arch armv8.3-a+pac" in *.S for llvm.

Revision 1.41 / (download) - annotate - [select for diffs], Sun May 10 21:40:38 2020 UTC (2 years, 10 months ago) by riastradh
Branch: MAIN
Changes since 1.40: +2 -2 lines
Diff to previous 1.40 (colored)

Fix ID_AA64ISAR0_EL1_RNDR field definition for RNDR support.

ARMv8.5 ARM, p. D13-3232

Revision 1.10.2.3 / (download) - annotate - [select for diffs], Tue Apr 21 18:42:02 2020 UTC (2 years, 11 months ago) by martin
Branch: phil-wifi
Changes since 1.10.2.2: +25 -0 lines
Diff to previous 1.10.2.2 (colored) to branchpoint 1.10 (colored) next main 1.11 (colored)

Sync with HEAD

Revision 1.39.2.1 / (download) - annotate - [select for diffs], Mon Apr 20 11:28:51 2020 UTC (2 years, 11 months ago) by bouyer
Branch: bouyer-xenpvh
Changes since 1.39: +26 -1 lines
Diff to previous 1.39 (colored) next main 1.40 (colored)

Sync with HEAD

Revision 1.10.2.2 / (download) - annotate - [select for diffs], Mon Apr 13 08:03:27 2020 UTC (2 years, 11 months ago) by martin
Branch: phil-wifi
Changes since 1.10.2.1: +336 -19 lines
Diff to previous 1.10.2.1 (colored) to branchpoint 1.10 (colored)

Mostly merge changes from HEAD upto 20200411

Revision 1.40 / (download) - annotate - [select for diffs], Sun Apr 12 07:49:58 2020 UTC (2 years, 11 months ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20200421, bouyer-xenpvh-base2, bouyer-xenpvh-base1
Changes since 1.39: +26 -1 lines
Diff to previous 1.39 (colored)

Add support for Pointer Authentication (PAC).

We use the "pac-ret" option, to sign the return instruction pointer on
function entry, and authenticate it on function exit. This acts as a
mitigation against ROP.

The authentication uses a per-lwp (secret) I-A key stored in the 128bit
APIAKey register and part of the lwp context. During lwp creation, the
kernel generates a random key, and during context switches, it installs
the key of the target lwp on the CPU.

Userland cannot read the APIAKey register directly. However, it can sign
its pointers with it, because the register is architecturally shared
between userland and the kernel. Although part of the CPU design, it is
a bit of an undesired behavior, because it allows to forge valid kernel
pointers from userland. To avoid that, we don't share the key with
userland, and rather switch it in EL0<->EL1 transitions. This means that
when userland executes, a different key is loaded in APIAKey than the one
the kernel uses. For now the userland key is a fixed 128bit zero value.

The DDB stack unwinder is changed to strip the authentication code from
the pointers in lr.

Two problems are known:

 * Currently the idlelwps' keys are not really secret. This is because
   the RNG is not yet available when we spawn these lwps. Not overly
   important, but would be nice to fix with UEFI RNG.
 * The key switching in EL0<->EL1 transitions is not the most optimized
   code on the planet. Instead of checking aarch64_pac_enabled, it would
   be better to hot-patch the code at boot time, but there currently is
   no hot-patch support on aarch64.

Tested on Qemu.

Revision 1.39 / (download) - annotate - [select for diffs], Mon Mar 30 11:38:29 2020 UTC (2 years, 11 months ago) by jmcneill
Branch: MAIN
CVS Tags: phil-wifi-20200411, phil-wifi-20200406, bouyer-xenpvh-base
Branch point for: bouyer-xenpvh
Changes since 1.38: +4 -1 lines
Diff to previous 1.38 (colored)

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

Revision 1.38 / (download) - annotate - [select for diffs], Fri Mar 6 20:28:26 2020 UTC (3 years ago) by ryo
Branch: MAIN
Changes since 1.37: +2 -2 lines
Diff to previous 1.37 (colored)

fix missing paren

Revision 1.37 / (download) - annotate - [select for diffs], Fri Mar 6 20:13:24 2020 UTC (3 years ago) by ryo
Branch: MAIN
Changes since 1.36: +58 -5 lines
Diff to previous 1.36 (colored)

add more definitions for ARMv8.1-ARMv8.4

Revision 1.36 / (download) - annotate - [select for diffs], Sat Feb 29 21:29:23 2020 UTC (3 years ago) by ryo
Branch: MAIN
CVS Tags: is-mlppp-base, is-mlppp
Changes since 1.35: +3 -2 lines
Diff to previous 1.35 (colored)

widen bit PAR_EL1.PAR_PA from [47:12] to [51:12] for ARMv8.2 (and later).

PAR_EL1:[51:48] is RES0 in ARMv8.1 and ARMv8.0.

Revision 1.30.2.1 / (download) - annotate - [select for diffs], Sat Feb 29 20:18:15 2020 UTC (3 years ago) by ad
Branch: ad-namecache
Changes since 1.30: +169 -11 lines
Diff to previous 1.30 (colored) next main 1.31 (colored)

Sync with head.

Revision 1.35 / (download) - annotate - [select for diffs], Fri Jan 31 09:23:58 2020 UTC (3 years, 1 month ago) by maxv
Branch: MAIN
CVS Tags: ad-namecache-base3
Changes since 1.34: +3 -1 lines
Diff to previous 1.34 (colored)

BTI definitions.

Revision 1.34 / (download) - annotate - [select for diffs], Tue Jan 28 18:02:30 2020 UTC (3 years, 1 month ago) by maxv
Branch: MAIN
Changes since 1.33: +17 -1 lines
Diff to previous 1.33 (colored)

More SCTLR.

Revision 1.33 / (download) - annotate - [select for diffs], Tue Jan 28 17:47:51 2020 UTC (3 years, 1 month ago) by maxv
Branch: MAIN
Changes since 1.32: +13 -6 lines
Diff to previous 1.32 (colored)

Fetch ID_AA64MMFR2_EL1. Okayed by Nick the other day.

Revision 1.32 / (download) - annotate - [select for diffs], Tue Jan 28 17:33:07 2020 UTC (3 years, 1 month ago) by maxv
Branch: MAIN
Changes since 1.31: +4 -5 lines
Diff to previous 1.31 (colored)

Jazelle and T32EE are not part of ARMv8, fix the bits to their real
meanings. No functional change.

Revision 1.31 / (download) - annotate - [select for diffs], Tue Jan 28 17:23:30 2020 UTC (3 years, 1 month ago) by maxv
Branch: MAIN
Changes since 1.30: +136 -2 lines
Diff to previous 1.30 (colored)

More definitions.

Revision 1.25.2.2 / (download) - annotate - [select for diffs], Sun Dec 29 09:27:09 2019 UTC (3 years, 2 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-3-RELEASE, netbsd-9-2-RELEASE, netbsd-9-1-RELEASE, netbsd-9-0-RELEASE, netbsd-9-0-RC2
Changes since 1.25.2.1: +2 -1 lines
Diff to previous 1.25.2.1 (colored) to branchpoint 1.25 (colored) next main 1.26 (colored)

Pull up following revision(s) (requested by jmcneill in ticket #586):

	sys/arch/arm/nvidia/tegra_pcie.c: revision 1.27
	sys/arch/aarch64/aarch64/pmap.c: revision 1.57
	sys/arch/aarch64/aarch64/locore.S: revision 1.48
	sys/arch/aarch64/include/armreg.h: revision 1.29
	sys/arch/aarch64/aarch64/pmap.c: revision 1.58
	sys/arch/aarch64/aarch64/locore.S: revision 1.49
	sys/arch/arm/acpi/acpipchb.c: revision 1.14
	sys/arch/aarch64/aarch64/genassym.cf: revision 1.16
	sys/arch/arm/acpi/acpi_machdep.c: revision 1.13
	sys/arch/aarch64/include/pmap.h: revision 1.27
	sys/arch/aarch64/aarch64/genassym.cf: revision 1.17
	sys/arch/aarch64/include/pmap.h: revision 1.28
	sys/arch/arm/fdt/pcihost_fdtvar.h: revision 1.3
	sys/arch/arm/include/bus_defs.h: revision 1.14
	sys/arch/aarch64/aarch64/bus_space.c: revision 1.9
	sys/arch/arm/fdt/pcihost_fdt.c: revision 1.12
	sys/arch/aarch64/conf/files.aarch64: revision 1.15
	sys/arch/aarch64/conf/files.aarch64: revision 1.16
	sys/arch/arm/rockchip/rk3399_pcie.c: revision 1.9

Enable early write acknowledge for device memory mappings.

Do not use Early Write Acknowledge for PCIe I/O and config space.

Revision 1.30 / (download) - annotate - [select for diffs], Sat Dec 28 00:22:08 2019 UTC (3 years, 2 months ago) by rjs
Branch: MAIN
CVS Tags: ad-namecache-base2, ad-namecache-base1, ad-namecache-base
Branch point for: ad-namecache
Changes since 1.29: +4 -4 lines
Diff to previous 1.29 (colored)

s/Memroy/Memory/ in comment.

Revision 1.29 / (download) - annotate - [select for diffs], Fri Dec 27 18:56:47 2019 UTC (3 years, 2 months ago) by jmcneill
Branch: MAIN
Changes since 1.28: +2 -1 lines
Diff to previous 1.28 (colored)

Enable early write acknowledge for device memory mappings.

Revision 1.28 / (download) - annotate - [select for diffs], Sun Sep 15 15:16:30 2019 UTC (3 years, 6 months ago) by tnn
Branch: MAIN
CVS Tags: phil-wifi-20191119
Changes since 1.27: +2 -1 lines
Diff to previous 1.27 (colored)

report A72 errata #859971 workaround status during boot

Revision 1.27 / (download) - annotate - [select for diffs], Wed Sep 11 18:19:35 2019 UTC (3 years, 6 months ago) by skrll
Branch: MAIN
Changes since 1.26: +58 -2 lines
Diff to previous 1.26 (colored)

Move the TCR and TTBR defines into armreg.h where they below.  NFCI.

Revision 1.25.2.1 / (download) - annotate - [select for diffs], Tue Aug 13 14:57:49 2019 UTC (3 years, 7 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-0-RC1
Changes since 1.25: +44 -1 lines
Diff to previous 1.25 (colored)

Pull up following revision(s) (requested by jmcneill in ticket #54):

	sys/arch/aarch64/include/armreg.h: revision 1.26
	sys/arch/arm/cortex/gtmr.c: revision 1.41
	sys/arch/arm/include/armreg.h: revision 1.128
	sys/arch/arm/cortex/gtmr_var.h: revision 1.12

Add support for physical timers and sprinkle isb where needed.

Revision 1.26 / (download) - annotate - [select for diffs], Mon Aug 12 23:31:48 2019 UTC (3 years, 7 months ago) by jmcneill
Branch: MAIN
Changes since 1.25: +44 -1 lines
Diff to previous 1.25 (colored)

Add support for physical timers and sprinkle isb where needed.

Revision 1.25 / (download) - annotate - [select for diffs], Sun Jun 16 15:16:15 2019 UTC (3 years, 9 months ago) by skrll
Branch: MAIN
CVS Tags: netbsd-9-base
Branch point for: netbsd-9
Changes since 1.24: +2 -1 lines
Diff to previous 1.24 (colored)

Provide icc_pmr_read

Revision 1.10.2.1 / (download) - annotate - [select for diffs], Mon Jun 10 22:05:43 2019 UTC (3 years, 9 months ago) by christos
Branch: phil-wifi
Changes since 1.10: +700 -521 lines
Diff to previous 1.10 (colored)

Sync with HEAD

Revision 1.24 / (download) - annotate - [select for diffs], Wed Mar 20 07:16:07 2019 UTC (4 years ago) by ryo
Branch: MAIN
CVS Tags: phil-wifi-20190609, isaki-audio2-base, isaki-audio2
Changes since 1.23: +16 -1 lines
Diff to previous 1.23 (colored)

- add reg_{s1e0r,s1e0w,s1e1r,s1e1w}_write() macro.
- show the result of AT insn at ddb "machine pte" command.

Revision 1.23 / (download) - annotate - [select for diffs], Wed Jan 30 02:02:23 2019 UTC (4 years, 1 month ago) by jmcneill
Branch: MAIN
Changes since 1.22: +8 -1 lines
Diff to previous 1.22 (colored)

add gtmr_cntv_cval_write

Revision 1.3.2.9 / (download) - annotate - [select for diffs], Wed Dec 26 14:01:30 2018 UTC (4 years, 3 months ago) by pgoyette
Branch: pgoyette-compat
CVS Tags: pgoyette-compat-merge-20190127
Changes since 1.3.2.8: +15 -1 lines
Diff to previous 1.3.2.8 (colored) to branchpoint 1.3 (colored) next main 1.4 (colored)

Sync with HEAD, resolve a few conflicts

Revision 1.22 / (download) - annotate - [select for diffs], Thu Dec 13 10:44:25 2018 UTC (4 years, 3 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-20190127, pgoyette-compat-20190118, pgoyette-compat-1226
Changes since 1.21: +15 -1 lines
Diff to previous 1.21 (colored)

add support PT_STEP

Revision 1.3.2.8 / (download) - annotate - [select for diffs], Mon Nov 26 01:52:16 2018 UTC (4 years, 4 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.3.2.7: +41 -1 lines
Diff to previous 1.3.2.7 (colored) to branchpoint 1.3 (colored)

Sync with HEAD, resolve a couple of conflicts

Revision 1.21 / (download) - annotate - [select for diffs], Tue Nov 20 01:59:51 2018 UTC (4 years, 4 months ago) by mrg
Branch: MAIN
CVS Tags: pgoyette-compat-1126
Changes since 1.20: +38 -1 lines
Diff to previous 1.20 (colored)

rewrite the CPU identification on arm64:

- publish per-cpu data
- publish a whole bunch of info in struct aarch64_sysctl_cpu_id
  instead of various individual nodes (there are 16 total.)
- add MIDR extractor bits
- define ARMv8.2-A id_aa64mmfr2_el1 and id_aa64zfr0_el1 regs,
  but avoid using them until we make sure they exist.  (these
  members are added to aarch64_sysctl_cpu_id to avoid future
  compat issues.)

the arm32 and aarch32 version of these need to be adjusted as
well (and aarch32 data published at all.)  still trying to
work out how to make the same userland binary running on a
real arm32 or an aarch32 system can work sanely here.

ok ryo@.

Revision 1.20 / (download) - annotate - [select for diffs], Wed Nov 7 06:47:38 2018 UTC (4 years, 4 months ago) by riastradh
Branch: MAIN
Changes since 1.19: +4 -1 lines
Diff to previous 1.19 (colored)

When hardware subnormal support is available, disable flush-to-zero.

Similarly, when hardware NaN propagation is available, disable
default-NaN substitution.

This enables IEEE 754 semantics on any hardware that supports it by
default.  Programs that want flush-to-zero or default-NaN substitution
can enable them explicitly.

ok ryo@

Revision 1.3.2.7 / (download) - annotate - [select for diffs], Sat Oct 20 06:58:24 2018 UTC (4 years, 5 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.3.2.6: +2 -1 lines
Diff to previous 1.3.2.6 (colored) to branchpoint 1.3 (colored)

Sync with head

Revision 1.19 / (download) - annotate - [select for diffs], Fri Oct 12 01:28:58 2018 UTC (4 years, 5 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-1020
Changes since 1.18: +2 -1 lines
Diff to previous 1.18 (colored)

add initial support of COMPAT_NETBSD32 on AArch64.
arm ELF32 EABI binaries could be execute in AArch32 state on AArch64. A32 THUMB mode is not supported yet.

Revision 1.3.2.6 / (download) - annotate - [select for diffs], Thu Sep 6 06:55:23 2018 UTC (4 years, 6 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.3.2.5: +486 -411 lines
Diff to previous 1.3.2.5 (colored) to branchpoint 1.3 (colored)

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

Revision 1.18 / (download) - annotate - [select for diffs], Sun Aug 12 17:21:35 2018 UTC (4 years, 7 months ago) by skrll
Branch: MAIN
CVS Tags: pgoyette-compat-0930, pgoyette-compat-0906
Changes since 1.17: +15 -1 lines
Diff to previous 1.17 (colored)

Provide and use cpu_mpidr_aff_read in psci_fdt_bootstrap

Revision 1.17 / (download) - annotate - [select for diffs], Sun Aug 12 17:16:18 2018 UTC (4 years, 7 months ago) by skrll
Branch: MAIN
Changes since 1.16: +1 -3 lines
Diff to previous 1.16 (colored)

Whitespace

Revision 1.16 / (download) - annotate - [select for diffs], Thu Aug 9 10:27:17 2018 UTC (4 years, 7 months ago) by jmcneill
Branch: MAIN
Changes since 1.15: +7 -1 lines
Diff to previous 1.15 (colored)

Restore ICC_SRE_EL2 registers lost in previous commit

Revision 1.15 / (download) - annotate - [select for diffs], Wed Aug 8 19:00:53 2018 UTC (4 years, 7 months ago) by jmcneill
Branch: MAIN
Changes since 1.14: +67 -10 lines
Diff to previous 1.14 (colored)

Add GICv3 system registers

Revision 1.14 / (download) - annotate - [select for diffs], Sun Aug 5 07:49:02 2018 UTC (4 years, 7 months ago) by skrll
Branch: MAIN
Changes since 1.13: +290 -290 lines
Diff to previous 1.13 (colored)

More whitespace

Revision 1.13 / (download) - annotate - [select for diffs], Wed Aug 1 13:42:58 2018 UTC (4 years, 7 months ago) by skrll
Branch: MAIN
Changes since 1.12: +117 -117 lines
Diff to previous 1.12 (colored)

Some whitespace improvements.  NFC.

Revision 1.3.2.5 / (download) - annotate - [select for diffs], Sat Jul 28 04:37:26 2018 UTC (4 years, 8 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.3.2.4: +545 -518 lines
Diff to previous 1.3.2.4 (colored) to branchpoint 1.3 (colored)

Sync with HEAD

Revision 1.12 / (download) - annotate - [select for diffs], Tue Jul 17 00:35:03 2018 UTC (4 years, 8 months ago) by christos
Branch: MAIN
CVS Tags: pgoyette-compat-0728
Changes since 1.11: +520 -557 lines
Diff to previous 1.11 (colored)

- use #define to define constants instead of static const variables so that
  gcc can compile the code.
- fix position of inline, and use __inline

Revision 1.11 / (download) - annotate - [select for diffs], Sun Jul 15 16:08:30 2018 UTC (4 years, 8 months ago) by jmcneill
Branch: MAIN
Changes since 1.10: +65 -1 lines
Diff to previous 1.10 (colored)

Add more PMC registers

Revision 1.3.2.4 / (download) - annotate - [select for diffs], Mon May 21 04:35:57 2018 UTC (4 years, 10 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.3.2.3: +8 -1 lines
Diff to previous 1.3.2.3 (colored) to branchpoint 1.3 (colored)

Sync with HEAD

Revision 1.10 / (download) - annotate - [select for diffs], Mon May 14 17:15:54 2018 UTC (4 years, 10 months ago) by joerg
Branch: MAIN
CVS Tags: phil-wifi-base, pgoyette-compat-0625, pgoyette-compat-0521
Branch point for: phil-wifi
Changes since 1.9: +8 -1 lines
Diff to previous 1.9 (colored)

Workaround A-008585 errata in GTMR.

Register reads and writes may provide unstable results if the counter
hardware is active at the same time. This results in non-monotonic
counters seen by both the gtmr interrupt and time counter.

The loops are currently applied unconditionally, restricting them to
appropiate FDT markers can be applied later.

Revision 1.3.2.3 / (download) - annotate - [select for diffs], Sat Apr 7 04:12:11 2018 UTC (4 years, 11 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.3.2.2: +658 -89 lines
Diff to previous 1.3.2.2 (colored) to branchpoint 1.3 (colored)

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Revision 1.9 / (download) - annotate - [select for diffs], Sun Apr 1 04:35:03 2018 UTC (4 years, 11 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-0502, pgoyette-compat-0422, pgoyette-compat-0415, pgoyette-compat-0407
Changes since 1.8: +658 -89 lines
Diff to previous 1.8 (colored)

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

Revision 1.3.2.2 / (download) - annotate - [select for diffs], Thu Mar 22 01:44:41 2018 UTC (5 years ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.3.2.1: +2 -1 lines
Diff to previous 1.3.2.1 (colored) to branchpoint 1.3 (colored)

Synch with HEAD, resolve conflicts

Revision 1.8 / (download) - annotate - [select for diffs], Tue Mar 20 10:14:29 2018 UTC (5 years ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-0330, pgoyette-compat-0322
Changes since 1.7: +2 -1 lines
Diff to previous 1.7 (colored)

separate cputypes.h for CPU_ID_* from armreg.h,
and add some implementor IDs, CortexA55,73,75 IDs.

(preliminary changes for merging aarch64)

Revision 1.3.2.1 / (download) - annotate - [select for diffs], Thu Mar 15 09:12:02 2018 UTC (5 years ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.3: +56 -56 lines
Diff to previous 1.3 (colored)

Synch with HEAD

Revision 1.7 / (download) - annotate - [select for diffs], Tue Mar 6 08:20:22 2018 UTC (5 years ago) by skrll
Branch: MAIN
CVS Tags: pgoyette-compat-0315
Changes since 1.6: +21 -21 lines
Diff to previous 1.6 (colored)

Sprinkle __volatile on asm instructions

Revision 1.6 / (download) - annotate - [select for diffs], Tue Mar 6 08:14:17 2018 UTC (5 years ago) by skrll
Branch: MAIN
Changes since 1.5: +36 -36 lines
Diff to previous 1.5 (colored)

Convert decimal to hex to make comparison to arm arm (slightly) easier.

Revision 1.5 / (download) - annotate - [select for diffs], Tue Mar 6 07:36:09 2018 UTC (5 years ago) by skrll
Branch: MAIN
Changes since 1.4: +2 -2 lines
Diff to previous 1.4 (colored)

Another harmless typo

Revision 1.4 / (download) - annotate - [select for diffs], Tue Mar 6 07:31:57 2018 UTC (5 years ago) by skrll
Branch: MAIN
Changes since 1.3: +2 -2 lines
Diff to previous 1.3 (colored)

Fix harmless typo

Revision 1.3 / (download) - annotate - [select for diffs], Wed Dec 20 14:58:08 2017 UTC (5 years, 3 months ago) by skrll
Branch: MAIN
CVS Tags: pgoyette-compat-base
Branch point for: pgoyette-compat
Changes since 1.2: +4 -4 lines
Diff to previous 1.2 (colored)

Trailing whitespace

Revision 1.1.4.3 / (download) - annotate - [select for diffs], Sun Dec 3 11:35:44 2017 UTC (5 years, 3 months ago) by jdolecek
Branch: tls-maxphys
Changes since 1.1.4.2: +2 -2 lines
Diff to previous 1.1.4.2 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored)

update from HEAD

Revision 1.1.6.1 / (download) - annotate - [select for diffs], Sat Jun 6 14:39:53 2015 UTC (7 years, 9 months ago) by skrll
Branch: nick-nhusb
Changes since 1.1: +3 -3 lines
Diff to previous 1.1 (colored) next main 1.2 (colored)

Sync with HEAD

ARM spells the System Control Register SCTLR

Revision 1.1.4.2 / (download) - annotate - [select for diffs], Wed Aug 20 00:02:39 2014 UTC (8 years, 7 months ago) by tls
Branch: tls-maxphys
Changes since 1.1.4.1: +456 -0 lines
Diff to previous 1.1.4.1 (colored) to branchpoint 1.1 (colored)

Rebase to HEAD as of a few days ago.

Revision 1.1.4.1, Sun Aug 10 05:47:37 2014 UTC (8 years, 7 months ago) by tls
Branch: tls-maxphys
Changes since 1.1: +0 -456 lines
FILE REMOVED

file armreg.h was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000

Revision 1.1 / (download) - annotate - [select for diffs], Sun Aug 10 05:47:37 2014 UTC (8 years, 7 months ago) by matt
Branch: MAIN
CVS Tags: tls-maxphys-base, nick-nhusb-base-20150406, nick-nhusb-base, netbsd-7-nhusb-base-20170116, netbsd-7-nhusb-base, netbsd-7-nhusb, netbsd-7-base, netbsd-7-2-RELEASE, netbsd-7-1-RELEASE, netbsd-7-1-RC2, netbsd-7-1-RC1, netbsd-7-1-2-RELEASE, netbsd-7-1-1-RELEASE, netbsd-7-1, netbsd-7-0-RELEASE, netbsd-7-0-RC3, netbsd-7-0-RC2, netbsd-7-0-RC1, netbsd-7-0-2-RELEASE, netbsd-7-0-1-RELEASE, netbsd-7-0, netbsd-7
Branch point for: tls-maxphys, nick-nhusb

Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.

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