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CVS log for src/sys/arch/aarch64/aarch64/vectors.S

[BACK] Up to [cvs.NetBSD.org] / src / sys / arch / aarch64 / aarch64

Request diff between arbitrary revisions

Default branch: MAIN

Revision 1.29 / (download) - annotate - [select for diffs], Sun Jun 26 11:14:36 2022 UTC (11 months, 1 week ago) by jmcneill
Branch: MAIN
CVS Tags: netbsd-10-base, netbsd-10, bouyer-sunxi-drm-base, bouyer-sunxi-drm, HEAD
Changes since 1.28: +2 -3 lines
Diff to previous 1.28 (colored) 

build fix: remove includes of opt_gic.h

Revision 1.28 / (download) - annotate - [select for diffs], Sat Jun 25 13:24:34 2022 UTC (11 months, 1 week ago) by jmcneill
Branch: MAIN
Changes since 1.27: +3 -19 lines
Diff to previous 1.27 (colored) 

Remove GIC_SPLFUNCS.

Revision 1.27 / (download) - annotate - [select for diffs], Sun May 29 23:39:59 2022 UTC (12 months ago) by ryo
Branch: MAIN
Changes since 1.26: +27 -22 lines
Diff to previous 1.26 (colored) 

ESR_EL1 and FAR_EL1 are not required in interrupt trapframe and their values are meaningless.
To identify it as an interrupt trap frame, store -1 and 0.

Revision 1.26 / (download) - annotate - [select for diffs], Fri May 6 06:09:50 2022 UTC (12 months, 4 weeks ago) by ryo
Branch: MAIN
Changes since 1.25: +4 -2 lines
Diff to previous 1.25 (colored) 

Sprinkle isb after modifying system regs of pointer auth.
With options ARMV83_PAC, it now works on native Mac M1.

TODO: Multiple ISBs should be combined in one place.

Revision 1.25 / (download) - annotate - [select for diffs], Fri May 6 05:14:38 2022 UTC (12 months, 4 weeks ago) by ryo
Branch: MAIN
Changes since 1.24: +3 -3 lines
Diff to previous 1.24 (colored) 

md_astpending is uint32_t

Revision 1.24 / (download) - annotate - [select for diffs], Sat Sep 18 12:25:06 2021 UTC (20 months, 2 weeks ago) by jmcneill
Branch: MAIN
Changes since 1.23: +20 -3 lines
Diff to previous 1.23 (colored) 

gic_splx: performance optimizations

Avoid any kind of register access (DAIF, PMR, etc), barriers, and atomic
operations in the common case where no interrupt fires between spl being
raised and lowered.

This introduces a per-CPU return address (ci_splx_restart) used by the
vector handler to restart a sequence in splx that compares the new ipl
with the per-CPU hardware priority state stored in ci_hwpl.

Revision 1.23 / (download) - annotate - [select for diffs], Mon Aug 30 23:20:00 2021 UTC (21 months ago) by jmcneill
Branch: MAIN
Changes since 1.22: +8 -8 lines
Diff to previous 1.22 (colored) 

Add FIQ support.

Revision 1.21.2.1 / (download) - annotate - [select for diffs], Sat Apr 3 22:28:13 2021 UTC (2 years, 2 months ago) by thorpej
Branch: thorpej-futex
Changes since 1.21: +5 -2 lines
Diff to previous 1.21 (colored) next main 1.22 (colored) 

Sync with HEAD.

Revision 1.22 / (download) - annotate - [select for diffs], Tue Mar 9 16:44:27 2021 UTC (2 years, 2 months ago) by ryo
Branch: MAIN
CVS Tags: thorpej-i2c-spi-conf2-base, thorpej-i2c-spi-conf2, thorpej-i2c-spi-conf-base, thorpej-i2c-spi-conf, thorpej-futex2-base, thorpej-futex2, thorpej-futex-base, thorpej-cfargs2-base, thorpej-cfargs2, thorpej-cfargs-base, thorpej-cfargs, cjep_sun2x-base1, cjep_sun2x-base, cjep_sun2x, cjep_staticlib_x-base1, cjep_staticlib_x-base, cjep_staticlib_x
Changes since 1.21: +5 -2 lines
Diff to previous 1.21 (colored) 

Add support hardware breakpoint and watchpoint again.

Limited support for hardware watchpoint has been available for some time, but it
has not been working properly. In addition, it stopped working at the time of
the PTRACE support commit on 2018-12-13. This has been fixed to work correctly,
and also fixed to be practical by sharing hardware watchpoints and breakpoints
between CPUs on MULTIPROCESSOR.

Also fixed a bug that causes a malfunction when switching CPUs with
"machine cpu N" when entering ddb mode from other than cpu_Debugger().

I have confirmed that the CPU can be switched by "machine cpu N" and return from
ddb properly in each case where ddb is called triggered by ddb break/watchpoint,
hardware break/watchpoint, and cpu_Debugger().

Revision 1.21 / (download) - annotate - [select for diffs], Thu Oct 15 08:37:20 2020 UTC (2 years, 7 months ago) by ryo
Branch: MAIN
Branch point for: thorpej-futex
Changes since 1.20: +11 -11 lines
Diff to previous 1.20 (colored) 

slightly optimized loop for trap_doast() calls

Revision 1.20 / (download) - annotate - [select for diffs], Tue Oct 6 06:26:46 2020 UTC (2 years, 7 months ago) by skrll
Branch: MAIN
Changes since 1.19: +3 -2 lines
Diff to previous 1.19 (colored) 

move #include "opt_compat_netbsd32.h" to where it's required

Revision 1.19 / (download) - annotate - [select for diffs], Wed Sep 30 16:35:49 2020 UTC (2 years, 8 months ago) by skrll
Branch: MAIN
Changes since 1.18: +144 -1 lines
Diff to previous 1.18 (colored) 

Move el[01]_trap_exit into vectors.S where the callers exist

Revision 1.18 / (download) - annotate - [select for diffs], Wed Aug 12 13:19:35 2020 UTC (2 years, 9 months ago) by skrll
Branch: MAIN
Changes since 1.17: +2 -3 lines
Diff to previous 1.17 (colored) 

Part II of ad's aarch64 performance improvements (cpu_switch.S bugs are
all mine)

- Use tpidr_el1 to hold curlwp and not curcpu, because curlwp is accessed
  much more often by MI code.  It also makes curlwp preemption safe and
  allows aarch64_curlwp() to be a const function (curcpu must be volatile).

- Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs
  can see spurious ASTs (which doesn't cause a problem, it just means some
  time may be wasted).

- Use plain stores to set/clear ASTs.  Make sure ASTs are always set on the
  same CPU as the target LWP, and delivered via IPI if posted from a remote
  CPU so that they are resolved quickly.

- Add some cache line padding to struct cpu_info, to match x86.

- Add a memory barrier in a couple of places where ci_curlwp is set.  This
  is needed whenever an LWP that is resuming on the CPU could hold an
  adaptive mutex.  The barrier needs to drain the CPU's store buffer, so
  that the update to ci_curlwp becomes globally visible before the LWP can
  resume and call mutex_exit().  By my reading of the ARM docs it looks like
  the instruction I used will do the right thing, but I'm not 100% sure.

Revision 1.17 / (download) - annotate - [select for diffs], Sat May 23 18:08:59 2020 UTC (3 years ago) by ryo
Branch: MAIN
Changes since 1.16: +2 -7 lines
Diff to previous 1.16 (colored) 

Not only the kernel thread, but also the userland PAC keys
(APIA,APIB,APDA,APDB,APGA) are now randomly initialized at exec, and switched
when context switch.
userland programs are able to perform pointer authentication on ARMv8.3+PAC cpu.

reviewd by maxv@, thanks.

Revision 1.16 / (download) - annotate - [select for diffs], Fri May 15 09:08:10 2020 UTC (3 years ago) by ryo
Branch: MAIN
Changes since 1.15: +5 -1 lines
Diff to previous 1.15 (colored) 

use ldp if possible

Revision 1.5.2.4 / (download) - annotate - [select for diffs], Tue Apr 21 18:42:02 2020 UTC (3 years, 1 month ago) by martin
Branch: phil-wifi
Changes since 1.5.2.3: +18 -2 lines
Diff to previous 1.5.2.3 (colored) to branchpoint 1.5 (colored) next main 1.6 (colored) 

Sync with HEAD

Revision 1.11.4.1 / (download) - annotate - [select for diffs], Mon Apr 20 11:28:50 2020 UTC (3 years, 1 month ago) by bouyer
Branch: bouyer-xenpvh
Changes since 1.11: +88 -36 lines
Diff to previous 1.11 (colored) next main 1.12 (colored) 

Sync with HEAD

Revision 1.15 / (download) - annotate - [select for diffs], Thu Apr 16 08:59:16 2020 UTC (3 years, 1 month ago) by skrll
Branch: MAIN
CVS Tags: phil-wifi-20200421, bouyer-xenpvh-base2, bouyer-xenpvh-base1
Changes since 1.14: +3 -2 lines
Diff to previous 1.14 (colored) 

Shave off 3 instructions per trap

Revision 1.5.2.3 / (download) - annotate - [select for diffs], Mon Apr 13 08:03:27 2020 UTC (3 years, 1 month ago) by martin
Branch: phil-wifi
Changes since 1.5.2.2: +71 -35 lines
Diff to previous 1.5.2.2 (colored) to branchpoint 1.5 (colored) 

Mostly merge changes from HEAD upto 20200411

Revision 1.14 / (download) - annotate - [select for diffs], Mon Apr 13 05:40:25 2020 UTC (3 years, 1 month ago) by maxv
Branch: MAIN
Changes since 1.13: +3 -3 lines
Diff to previous 1.13 (colored) 

Add support for Branch Target Identification (BTI).

On the executable pages that have the GP (Guarded Page) bit, the semantic
of the "br" and "blr" instructions is changed: the CPU expects the first
instruction of the jump/call target to be "bti", and faults if it isn't.

We add the GP bit on the kernel .text pages (and incidentally the .rodata
pages, but we don't care). The compiler adds a "bti c" instruction at the
beginning of each C function. We modify the ENTRY() macros to manually add
"bti c" in the asm functions.

cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j",
which is bad because the functions begin with "bti c"; switch to "br x16",
for the CPU to accept "bti c".

BTI helps defend against JOP/COP. Tested on Qemu.

Revision 1.13 / (download) - annotate - [select for diffs], Sun Apr 12 07:49:58 2020 UTC (3 years, 1 month ago) by maxv
Branch: MAIN
Changes since 1.12: +16 -1 lines
Diff to previous 1.12 (colored) 

Add support for Pointer Authentication (PAC).

We use the "pac-ret" option, to sign the return instruction pointer on
function entry, and authenticate it on function exit. This acts as a
mitigation against ROP.

The authentication uses a per-lwp (secret) I-A key stored in the 128bit
APIAKey register and part of the lwp context. During lwp creation, the
kernel generates a random key, and during context switches, it installs
the key of the target lwp on the CPU.

Userland cannot read the APIAKey register directly. However, it can sign
its pointers with it, because the register is architecturally shared
between userland and the kernel. Although part of the CPU design, it is
a bit of an undesired behavior, because it allows to forge valid kernel
pointers from userland. To avoid that, we don't share the key with
userland, and rather switch it in EL0<->EL1 transitions. This means that
when userland executes, a different key is loaded in APIAKey than the one
the kernel uses. For now the userland key is a fixed 128bit zero value.

The DDB stack unwinder is changed to strip the authentication code from
the pointers in lr.

Two problems are known:

 * Currently the idlelwps' keys are not really secret. This is because
   the RNG is not yet available when we spawn these lwps. Not overly
   important, but would be nice to fix with UEFI RNG.
 * The key switching in EL0<->EL1 transitions is not the most optimized
   code on the planet. Instead of checking aarch64_pac_enabled, it would
   be better to hot-patch the code at boot time, but there currently is
   no hot-patch support on aarch64.

Tested on Qemu.

Revision 1.12 / (download) - annotate - [select for diffs], Sat Apr 11 09:02:04 2020 UTC (3 years, 1 month ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20200411
Changes since 1.11: +72 -36 lines
Diff to previous 1.11 (colored) 

The vectors allow for up to 0x80 bytes of instructions, but we've reached
this limit already, so implement the handler functions outside, and jump
to them. This allows to add instructions in the future.

Sent to ryo@ and skrll@.

Revision 1.5.2.2 / (download) - annotate - [select for diffs], Wed Apr 8 14:07:23 2020 UTC (3 years, 1 month ago) by martin
Branch: phil-wifi
Changes since 1.5.2.1: +17 -3 lines
Diff to previous 1.5.2.1 (colored) to branchpoint 1.5 (colored) 

Merge changes from current as of 20200406

Revision 1.9.6.1 / (download) - annotate - [select for diffs], Sat Feb 29 20:18:15 2020 UTC (3 years, 3 months ago) by ad
Branch: ad-namecache
Changes since 1.9: +17 -3 lines
Diff to previous 1.9 (colored) next main 1.10 (colored) 

Sync with head.

Revision 1.9.4.1 / (download) - annotate - [select for diffs], Wed Feb 12 19:55:57 2020 UTC (3 years, 3 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-3-RELEASE, netbsd-9-2-RELEASE, netbsd-9-1-RELEASE, netbsd-9-0-RELEASE
Changes since 1.9: +15 -3 lines
Diff to previous 1.9 (colored) next main 1.10 (colored) 

Pull up following revision(s) (requested by riastradh in ticket #701):

	external/cddl/osnet/dev/dtrace/aarch64/dtrace_isa.c: revision 1.2
	external/cddl/osnet/dist/lib/libdtrace/common/dt_open.c: revision 1.17
	external/cddl/osnet/dist/lib/libdtrace/common/dt_module.c: revision 1.18
	sys/modules/cyclic/Makefile: revision 1.5
	external/cddl/osnet/dev/dtrace/aarch64/dtrace_subr.c: revision 1.2
	external/cddl/osnet/dev/dtrace/aarch64/dtrace_subr.c: revision 1.3
	sys/arch/aarch64/aarch64/vectors.S: revision 1.10
	external/cddl/osnet/dev/fbt/aarch64/fbt_isa.c: revision 1.2
	external/cddl/osnet/dev/fbt/aarch64/fbt_isa.c: revision 1.3
	external/cddl/osnet/dev/fbt/aarch64/fbt_isa.c: revision 1.4
	external/cddl/osnet/dev/fbt/aarch64/fbt_isa.c: revision 1.5
	external/cddl/osnet/dev/fbt/aarch64/fbt_isa.c: revision 1.6
	sys/arch/aarch64/include/cpu.h: revision 1.20
	external/cddl/osnet/dist/lib/libdtrace/common/dt_impl.h: revision 1.9

Create a buffer space of 512 bytes before the trapframe.

dtrace fbt needs enough space to emulate an

        stp     x29, x30, [sp,#-FRAMESIZE]!

instruction in a function prologue.  In the aarch64 instruction
encoding, FRAMESIZE can be as large as 512 bytes, so reserve this
much space when KDTRACE_HOOKS is enabled.

Use db_write_bytes to overwrite kernel text.

Tidy up a bit.  No functional change intended.

aarch64 fbt_invop doesn't actually use the argument, but it would
make more sense for it to be the return value and/or first argument
register.  Certainly it's not `eax'!

Tidy up a bit: don't set things we won't use; assert nonzeroness.

Use /dev/ksyms, not /netbsd, for the running kernel's symbols.

Teach dtrace about el1_trap_exit frames on aarch64.

Implement dtrace_getarg and dtrace_getreg while here.

Count the number of artificial frames in aarch64 fbt probe correctly.

Change the address ranges that aarch64 considers toxic for dtrace.
`Toxic' means dtrace forbids D scripts from even attempting to read
or write at them.

Previously we considered [0, VM_MIN_KERNEL_ADDRESS) toxic, but
VM_MIN_KERNEL_ADDRESS is only the minimum address of the kernel map;
the direct-mapped region lies below it, and with PMAP_MAP_POOLPAGE we
allocate virtual pages for pool backing directly from physical pages
through the direct-mapped region.  Also, this did not consider I/O
mappings to be toxic, which they probably should be.

Instead, treat:

[0, AARCH64_KSEG_START)
and
[VM_KERNEL_IO_ADDRESS, 0xfff...ff)

as toxic.  (The upper bound for 0xfff...ff ought to be inclusive, not
exclusive, but I think we'll need another mechanism for expressing
that to dtrace!)

Switch from db_write_bytes to using direct-mapping.

This way there's no dependency on ddb.

Define the MULTIPROCESSOR cpu_number() for modules too.
Modules should work whether the main kernel is multiprocessor or not.
In particular, dtrace should not think cpu_number() is 0 while
cpu_index(curcpu()) and curcpu()->ci_index are nonzero, leading to
rather spectacularly bogus results...

cyclic.kmod needs -Wno-sign-compare for aarch64 CPU_INFO_FOREACH.
Provisional workaround; feel free to fix.

Revision 1.11 / (download) - annotate - [select for diffs], Wed Feb 12 07:02:08 2020 UTC (3 years, 3 months ago) by skrll
Branch: MAIN
CVS Tags: phil-wifi-20200406, is-mlppp-base, is-mlppp, bouyer-xenpvh-base, ad-namecache-base3
Branch point for: bouyer-xenpvh
Changes since 1.10: +5 -3 lines
Diff to previous 1.10 (colored) 

Adjust comments

Revision 1.10 / (download) - annotate - [select for diffs], Wed Feb 12 01:09:17 2020 UTC (3 years, 3 months ago) by riastradh
Branch: MAIN
Changes since 1.9: +15 -3 lines
Diff to previous 1.9 (colored) 

Create a buffer space of 512 bytes before the trapframe.

dtrace fbt needs enough space to emulate an

	stp	x29, x30, [sp,#-FRAMESIZE]!

instruction in a function prologue.  In the aarch64 instruction
encoding, FRAMESIZE can be as large as 512 bytes, so reserve this
much space when KDTRACE_HOOKS is enabled.

Revision 1.5.2.1 / (download) - annotate - [select for diffs], Mon Jun 10 22:05:43 2019 UTC (3 years, 11 months ago) by christos
Branch: phil-wifi
Changes since 1.5: +16 -12 lines
Diff to previous 1.5 (colored) 

Sync with HEAD

Revision 1.4.2.5 / (download) - annotate - [select for diffs], Sat Oct 20 06:58:23 2018 UTC (4 years, 7 months ago) by pgoyette
Branch: pgoyette-compat
CVS Tags: pgoyette-compat-merge-20190127
Changes since 1.4.2.4: +10 -10 lines
Diff to previous 1.4.2.4 (colored) to branchpoint 1.4 (colored) next main 1.5 (colored) 

Sync with head

Revision 1.9 / (download) - annotate - [select for diffs], Fri Oct 12 01:28:57 2018 UTC (4 years, 7 months ago) by ryo
Branch: MAIN
CVS Tags: phil-wifi-20191119, phil-wifi-20190609, pgoyette-compat-20190127, pgoyette-compat-20190118, pgoyette-compat-1226, pgoyette-compat-1126, pgoyette-compat-1020, netbsd-9-base, netbsd-9-0-RC2, netbsd-9-0-RC1, isaki-audio2-base, isaki-audio2, ad-namecache-base2, ad-namecache-base1, ad-namecache-base
Branch point for: netbsd-9, ad-namecache
Changes since 1.8: +10 -10 lines
Diff to previous 1.8 (colored) 

add initial support of COMPAT_NETBSD32 on AArch64.
arm ELF32 EABI binaries could be execute in AArch32 state on AArch64. A32 THUMB mode is not supported yet.

Revision 1.4.2.4 / (download) - annotate - [select for diffs], Sun Sep 30 01:45:35 2018 UTC (4 years, 8 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.4.2.3: +2 -2 lines
Diff to previous 1.4.2.3 (colored) to branchpoint 1.4 (colored) 

Ssync with HEAD

Revision 1.8 / (download) - annotate - [select for diffs], Fri Sep 14 05:33:50 2018 UTC (4 years, 8 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-0930
Changes since 1.7: +2 -2 lines
Diff to previous 1.7 (colored) 

use ENTRY_NP to avoid added _PROF_PROLOGUE.

Revision 1.4.2.3 / (download) - annotate - [select for diffs], Thu Sep 6 06:55:22 2018 UTC (4 years, 8 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.4.2.2: +5 -1 lines
Diff to previous 1.4.2.2 (colored) to branchpoint 1.4 (colored) 

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

Revision 1.7 / (download) - annotate - [select for diffs], Mon Jul 30 15:59:44 2018 UTC (4 years, 10 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-0906
Changes since 1.6: +5 -1 lines
Diff to previous 1.6 (colored) 

don't depend on clang code to backtrace. keep trapframe as framepointer if DDB.

Revision 1.4.2.2 / (download) - annotate - [select for diffs], Sat Jul 28 04:37:25 2018 UTC (4 years, 10 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.4.2.1: +2 -2 lines
Diff to previous 1.4.2.1 (colored) to branchpoint 1.4 (colored) 

Sync with HEAD

Revision 1.6 / (download) - annotate - [select for diffs], Tue Jul 17 10:01:59 2018 UTC (4 years, 10 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-0728
Changes since 1.5: +2 -2 lines
Diff to previous 1.5 (colored) 

fix build with aarch64 gcc/gas

Revision 1.4.2.1 / (download) - annotate - [select for diffs], Sat Apr 7 04:12:10 2018 UTC (5 years, 1 month ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.4: +59 -127 lines
Diff to previous 1.4 (colored) 

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Revision 1.5 / (download) - annotate - [select for diffs], Sun Apr 1 04:35:03 2018 UTC (5 years, 2 months ago) by ryo
Branch: MAIN
CVS Tags: phil-wifi-base, pgoyette-compat-0625, pgoyette-compat-0521, pgoyette-compat-0502, pgoyette-compat-0422, pgoyette-compat-0415, pgoyette-compat-0407
Branch point for: phil-wifi
Changes since 1.4: +59 -127 lines
Diff to previous 1.4 (colored) 

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

Revision 1.1.4.3 / (download) - annotate - [select for diffs], Sun Dec 3 11:35:43 2017 UTC (5 years, 6 months ago) by jdolecek
Branch: tls-maxphys
Changes since 1.1.4.2: +165 -52 lines
Diff to previous 1.1.4.2 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored) 

update from HEAD

Revision 1.1.6.1 / (download) - annotate - [select for diffs], Mon Aug 28 17:51:26 2017 UTC (5 years, 9 months ago) by skrll
Branch: nick-nhusb
Changes since 1.1: +165 -52 lines
Diff to previous 1.1 (colored) next main 1.2 (colored) 

Sync with HEAD

Revision 1.4 / (download) - annotate - [select for diffs], Wed Aug 23 13:02:14 2017 UTC (5 years, 9 months ago) by nisimura
Branch: MAIN
CVS Tags: tls-maxphys-base-20171202, pgoyette-compat-base, pgoyette-compat-0330, pgoyette-compat-0322, pgoyette-compat-0315, nick-nhusb-base-20170825
Branch point for: pgoyette-compat
Changes since 1.3: +31 -24 lines
Diff to previous 1.3 (colored) 


- don't use ENTRY() for exception entries.
- correct section definition.
- designate long pointer ldr.

Revision 1.3 / (download) - annotate - [select for diffs], Tue Aug 22 18:35:09 2017 UTC (5 years, 9 months ago) by nisimura
Branch: MAIN
Changes since 1.2: +13 -13 lines
Diff to previous 1.2 (colored) 

use lr for current x30. some comment snip

Revision 1.2 / (download) - annotate - [select for diffs], Tue Aug 22 17:08:03 2017 UTC (5 years, 9 months ago) by nisimura
Branch: MAIN
Changes since 1.1: +158 -52 lines
Diff to previous 1.1 (colored) 

fill EL1 exception entry vector

Revision 1.1.4.2 / (download) - annotate - [select for diffs], Wed Aug 20 00:02:39 2014 UTC (8 years, 9 months ago) by tls
Branch: tls-maxphys
Changes since 1.1.4.1: +68 -0 lines
Diff to previous 1.1.4.1 (colored) to branchpoint 1.1 (colored) 

Rebase to HEAD as of a few days ago.

Revision 1.1.4.1, Sun Aug 10 05:47:37 2014 UTC (8 years, 9 months ago) by tls
Branch: tls-maxphys
Changes since 1.1: +0 -68 lines
FILE REMOVED 

file vectors.S was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000

Revision 1.1 / (download) - annotate - [select for diffs], Sun Aug 10 05:47:37 2014 UTC (8 years, 9 months ago) by matt
Branch: MAIN
CVS Tags: tls-maxphys-base, prg-localcount2-base3, prg-localcount2-base2, prg-localcount2-base1, prg-localcount2-base, prg-localcount2, pgoyette-localcount-base, pgoyette-localcount-20170426, pgoyette-localcount-20170320, pgoyette-localcount-20170107, pgoyette-localcount-20161104, pgoyette-localcount-20160806, pgoyette-localcount-20160726, pgoyette-localcount, perseant-stdc-iso10646-base, perseant-stdc-iso10646, nick-nhusb-base-20170204, nick-nhusb-base-20161204, nick-nhusb-base-20161004, nick-nhusb-base-20160907, nick-nhusb-base-20160529, nick-nhusb-base-20160422, nick-nhusb-base-20160319, nick-nhusb-base-20151226, nick-nhusb-base-20150921, nick-nhusb-base-20150606, nick-nhusb-base-20150406, nick-nhusb-base, netbsd-8-base, netbsd-8-2-RELEASE, netbsd-8-1-RELEASE, netbsd-8-1-RC1, netbsd-8-0-RELEASE, netbsd-8-0-RC2, netbsd-8-0-RC1, netbsd-8, netbsd-7-nhusb-base-20170116, netbsd-7-nhusb-base, netbsd-7-nhusb, netbsd-7-base, netbsd-7-2-RELEASE, netbsd-7-1-RELEASE, netbsd-7-1-RC2, netbsd-7-1-RC1, netbsd-7-1-2-RELEASE, netbsd-7-1-1-RELEASE, netbsd-7-1, netbsd-7-0-RELEASE, netbsd-7-0-RC3, netbsd-7-0-RC2, netbsd-7-0-RC1, netbsd-7-0-2-RELEASE, netbsd-7-0-1-RELEASE, netbsd-7-0, netbsd-7, matt-nb8-mediatek-base, matt-nb8-mediatek, localcount-20160914, jdolecek-ncq-base, jdolecek-ncq, bouyer-socketcan-base1, bouyer-socketcan-base, bouyer-socketcan
Branch point for: tls-maxphys, nick-nhusb 

Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.

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