CVS log for src/sys/arch/aarch64/aarch64/pmapboot.c

Up to [cvs.NetBSD.org] / src / sys / arch / aarch64 / aarch64

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

Remove ryo@'s mail addresses.

fix build with options PMAPBOOT_DEBUG and options DDB

Sync with HEAD.

Make the ddb for pmap / pte information pmap agnostic

Sync with HEAD.

Sync with HEAD.

Make pmapboot_enter panic if anything goes wrong and any mappings overlap
rather than only doing it in locore.S

Fix a potential issue in pmapboot_enter_range and pmapboot_enter where
if the va and size are not page aligned, there is a possibility of the
last page not being taken into consideration.

Sync w/ HEAD.

s:aarch64/cpufunc.h:arm/cpufunc.h:

a baby step in the grand arm header unification challenge

Ensure translation table updates are visible to the hardware walker(s)
in pmapboot_enter.

AA64 is not MIPS.

Change all KSEG references to directmap

Pull up following revision(s) (requested by skrll in ticket #1128):

	sys/arch/aarch64/aarch64/pmapboot.c: revision 1.11

Fix the use of the contiguous bit by checking the output address as well.

Fix the use of the contiguous bit by checking the output address as well.

KNF. 80 cols, use tab.

Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter().
Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.

pmapboot_enter simplication
- bootpage_alloc in asm becomes pmapboot_pagealloc in C
- PMAPBOOT_ENTER_NOBLOCK is removed as it's not used
- PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on
- physpage_allocator argument is removed as it's always
  pmapboot_pagealloc
- Support for EARLYCONS without CONSADDR is removed so that the identity
  map for CONSADDR is always known.

For the assembly files:
 2 files changed, 40 insertions(+), 89 deletions(-)

LGTM ryo

Sync with HEAD

Sync with HEAD

Mostly merge changes from HEAD upto 20200411

Add support for Branch Target Identification (BTI).

On the executable pages that have the GP (Guarded Page) bit, the semantic
of the "br" and "blr" instructions is changed: the CPU expects the first
instruction of the jump/call target to be "bti", and faults if it isn't.

We add the GP bit on the kernel .text pages (and incidentally the .rodata
pages, but we don't care). The compiler adds a "bti c" instruction at the
beginning of each C function. We modify the ENTRY() macros to manually add
"bti c" in the asm functions.

cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j",
which is bad because the functions begin with "bti c"; switch to "br x16",
for the CPU to accept "bti c".

BTI helps defend against JOP/COP. Tested on Qemu.

Merge changes from current as of 20200406

Fix pmap to work correctly with tagged addresses

- when fault, untag from address before passing to uvm/pmap functions
- pmap_extract() checks more strictly and consider the address tag

replace KSEG pages mapping code with generic function pmapboot_enter_range()

Simplify conditionals when clearing the CONTIG flag in pmapboot_enter and
update the comments to be a little clearer.

Sync with HEAD

Synch with HEAD

file pmapboot.c was added on branch phil-wifi on 2019-06-10 22:05:43 +0000

pmapboot_pte_print() is only used when VERBOSE_INIT_ARM is defined.

Sync with head

file pmapboot.c was added on branch pgoyette-compat on 2018-10-20 06:58:23 +0000

fix build error without DDB

cleanup locore, and changed the way to map memories during boot.
- add functions bootpage_enter() and bootpage_alloc() to adapt various layout
  of physical memory map. especially for 64bit physical memory layout.
  pmapboot_alloc() allocates pagetable pages from _end[].
- changed to map only the required amount for PA=VA identity mapping
  (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte).
- changing page permission for kernel image, and making KSEG mapping are done
  at cpu_kernel_vm_init() instead of at locore.
- optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.

reviewed by skrll@, thanks.