CVS log for src/sys/arch/aarch64/aarch64/locore.S

Up to [cvs.NetBSD.org] / src / sys / arch / aarch64 / aarch64

Request diff between arbitrary revisions

Default branch: MAIN
Current tag: MAIN

Revision 1.93 / (download) - annotate - [select for diffs], Wed Feb 7 04:20:26 2024 UTC (2 months, 1 week ago) by msaitoh
Branch: MAIN
CVS Tags: HEAD
Changes since 1.92: +3 -3 lines
Diff to previous 1.92 (colored)

Remove ryo@'s mail addresses.

Revision 1.92 / (download) - annotate - [select for diffs], Sun Apr 16 14:01:51 2023 UTC (12 months ago) by skrll
Branch: MAIN
CVS Tags: thorpej-ifq-base, thorpej-ifq, thorpej-altq-separation-base, thorpej-altq-separation
Changes since 1.91: +3 -3 lines
Diff to previous 1.91 (colored)

Rename VM_KERNEL_IO_ADDRESS to VM_KERNEL_IO_BASE to match RISC-V

It's less letters, matches other similar variables and will help with
sharing code between the two architectures.

NFCI.

Revision 1.91 / (download) - annotate - [select for diffs], Thu Feb 23 14:54:57 2023 UTC (13 months, 3 weeks ago) by riastradh
Branch: MAIN
Changes since 1.90: +7 -2 lines
Diff to previous 1.90 (colored)

aarch64: Add missing barriers in cpu_switchto.

Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

XXX pullup-9
XXX pullup-10

Revision 1.90 / (download) - annotate - [select for diffs], Fri Feb 17 06:24:26 2023 UTC (14 months ago) by skrll
Branch: MAIN
Changes since 1.89: +3 -3 lines
Diff to previous 1.89 (colored)

Improve an error message

Revision 1.89 / (download) - annotate - [select for diffs], Sat Oct 29 07:32:54 2022 UTC (17 months, 3 weeks ago) by skrll
Branch: MAIN
CVS Tags: netbsd-10-base
Branch point for: netbsd-10
Changes since 1.88: +3 -3 lines
Diff to previous 1.88 (colored)

Slightly better English in a comment.

Revision 1.88 / (download) - annotate - [select for diffs], Sat Oct 15 11:07:38 2022 UTC (18 months ago) by jmcneill
Branch: MAIN
Changes since 1.87: +5 -5 lines
Diff to previous 1.87 (colored)

Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
 - _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
 - PMAP_DEV_SO to PMAP_DEV_NP
 - LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
 - AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED

Revision 1.87 / (download) - annotate - [select for diffs], Tue Aug 23 05:31:12 2022 UTC (19 months, 3 weeks ago) by ryo
Branch: MAIN
CVS Tags: bouyer-sunxi-drm-base, bouyer-sunxi-drm
Changes since 1.86: +2 -16 lines
Diff to previous 1.86 (colored)

Bss clearing is now done at the beginning of start.S.

Some `__attribute__((__section__(".data")))' hack will no longer be needed.

Revision 1.86 / (download) - annotate - [select for diffs], Fri May 6 06:09:50 2022 UTC (23 months, 2 weeks ago) by ryo
Branch: MAIN
Changes since 1.85: +4 -2 lines
Diff to previous 1.85 (colored)

Sprinkle isb after modifying system regs of pointer auth.
With options ARMV83_PAC, it now works on native Mac M1.

TODO: Multiple ISBs should be combined in one place.

Revision 1.85 / (download) - annotate - [select for diffs], Mon Jan 31 09:16:09 2022 UTC (2 years, 2 months ago) by ryo
Branch: MAIN
Changes since 1.84: +10 -2 lines
Diff to previous 1.84 (colored)

add support Hardware updates to Access flag and Dirty state (FEAT_HAFDBS)

- The DBM bit of the PTE is now used to determine if it is writable, and
  the AF bit is treated entirely as a reference bit. A valid PTE is always
  treated as readable. There can be no valid PTE that is not readable.
- LX_BLKPAG_OS_{READ,WRITE} are used only for debugging purposes,
  and has been superseded by LX_BLKPAG_AF and LX_BLKPAG_DBM.
- Improve comment

The need for reference/modify emulation has been eliminated,
and access/permission faults have been reduced, however,
there has been little change in overall performance.

Revision 1.84 / (download) - annotate - [select for diffs], Fri Dec 10 20:36:02 2021 UTC (2 years, 4 months ago) by andvar
Branch: MAIN
Changes since 1.83: +3 -3 lines
Diff to previous 1.83 (colored)

s/occured/occurred/ in comments, log messages and man pages.

Revision 1.83 / (download) - annotate - [select for diffs], Sun Nov 14 16:56:32 2021 UTC (2 years, 5 months ago) by riastradh
Branch: MAIN
Changes since 1.82: +3 -4 lines
Diff to previous 1.82 (colored)

arm: Fix CPU startup synchronization.

- Use load-acquire instead of (wrong) membar_consumer then load in
  cpu_boot_secondary_processors and cpu_hatched_p.

  => (Could use load then membar_consumer instead but load-acquire is
     shorter.)

- Issue  dmb ish  before setting or clearing the bit in
  cpu_set_hatched and cpu_clr_mbox to effect a store-release.

  => (Could use membar_exit, which is semantically weaker than  dmb ish
     but on arm is just implemented as  dmb ish.)

  => (Could use stlr except we don't have atomic_ops(9) to do that.)

This way, everything before cpu_set_hatched or cpu_clr_mbox is
guaranteed to happen before everything after
cpu_boot_secondary_processors, which was previously not guaranteed.

Revision 1.82 / (download) - annotate - [select for diffs], Sun Oct 31 16:23:47 2021 UTC (2 years, 5 months ago) by skrll
Branch: MAIN
Changes since 1.81: +19 -41 lines
Diff to previous 1.81 (colored)

Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
   diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3

Revision 1.81 / (download) - annotate - [select for diffs], Thu Oct 21 06:06:16 2021 UTC (2 years, 5 months ago) by skrll
Branch: MAIN
Changes since 1.80: +3 -3 lines
Diff to previous 1.80 (colored)

fix gimplish

Revision 1.80 / (download) - annotate - [select for diffs], Thu Sep 30 21:19:16 2021 UTC (2 years, 6 months ago) by skrll
Branch: MAIN
Changes since 1.79: +22 -2 lines
Diff to previous 1.79 (colored)

Ensure TCR_EPD0 is set on entry to pmap_activate and ensure it is set as
early as possible for APs.

Revision 1.79 / (download) - annotate - [select for diffs], Mon Aug 30 22:24:39 2021 UTC (2 years, 7 months ago) by jmcneill
Branch: MAIN
Changes since 1.78: +3 -3 lines
Diff to previous 1.78 (colored)

Add instruction barrier after write to mair_el1

Revision 1.78 / (download) - annotate - [select for diffs], Sun Mar 21 09:08:40 2021 UTC (3 years, 1 month ago) by skrll
Branch: MAIN
CVS Tags: thorpej-i2c-spi-conf2-base, thorpej-i2c-spi-conf2, thorpej-i2c-spi-conf-base, thorpej-i2c-spi-conf, thorpej-futex2-base, thorpej-futex2, thorpej-futex-base, thorpej-cfargs2-base, thorpej-cfargs2, thorpej-cfargs-base, cjep_sun2x-base1, cjep_sun2x-base, cjep_sun2x, cjep_staticlib_x-base1, cjep_staticlib_x-base, cjep_staticlib_x
Changes since 1.77: +3 -3 lines
Diff to previous 1.77 (colored)

Fix a comment

Revision 1.77 / (download) - annotate - [select for diffs], Sat Mar 20 14:30:50 2021 UTC (3 years, 1 month ago) by skrll
Branch: MAIN
Changes since 1.76: +3 -7 lines
Diff to previous 1.76 (colored)

Make pmapboot_enter panic if anything goes wrong and any mappings overlap
rather than only doing it in locore.S

Revision 1.76 / (download) - annotate - [select for diffs], Sat Jan 9 15:07:42 2021 UTC (3 years, 3 months ago) by jmcneill
Branch: MAIN
Branch point for: thorpej-cfargs
Changes since 1.75: +5 -4 lines
Diff to previous 1.75 (colored)

Avoid mismatched memory attributes for kernel and page table memory.

The initial page table code enters mappings first through an identity
mapped normal-NC mapping. Then later on, additional mappings are added
through a KVA-mapped normal-WB mapping. There is a warning about this
in the Armv8 ARM:

  Bytes written without the Write-Back cacheable attribute within the
  same Write-Back granule as bytes written with the Write-Back cacheable
  attribute might have their values reverted to the old values as a result
  of cache Write-Back.

Change the identity mapping attributes to match the KVA-mapping. This
fixes an issue where the kernel often doesn't start under ESXi-Arm Fling.

Revision 1.75 / (download) - annotate - [select for diffs], Sat Dec 26 00:55:26 2020 UTC (3 years, 3 months ago) by jmcneill
Branch: MAIN
Changes since 1.74: +3 -2 lines
Diff to previous 1.74 (colored)

Always issue isb after cpacr_el1 writes since it is a context-changing
operation.

Revision 1.74 / (download) - annotate - [select for diffs], Thu Oct 22 07:16:06 2020 UTC (3 years, 5 months ago) by ryo
Branch: MAIN
Branch point for: thorpej-futex
Changes since 1.73: +4 -10 lines
Diff to previous 1.73 (colored)

Don't trap EL0 accesses to the DCC registers.
VMWare use "mrs xzr, mdccsr_el0" for guest side backdoor.

Revision 1.73 / (download) - annotate - [select for diffs], Tue Sep 15 09:28:20 2020 UTC (3 years, 7 months ago) by ryo
Branch: MAIN
Changes since 1.72: +4 -4 lines
Diff to previous 1.72 (colored)

fix typo

Revision 1.72 / (download) - annotate - [select for diffs], Tue Sep 15 09:23:15 2020 UTC (3 years, 7 months ago) by ryo
Branch: MAIN
Changes since 1.71: +26 -10 lines
Diff to previous 1.71 (colored)

fix aarch64eb MULTIPROCESSOR boot

- set endian of EL2,EL1 and EL0 at the beginning of start() and cpu_mpstart()
- drop_to_el1() keeps the endian setting

Revision 1.71 / (download) - annotate - [select for diffs], Sun Aug 16 10:08:42 2020 UTC (3 years, 8 months ago) by skrll
Branch: MAIN
Changes since 1.70: +10 -5 lines
Diff to previous 1.70 (colored)

Improve comments

Revision 1.70 / (download) - annotate - [select for diffs], Wed Aug 12 13:19:35 2020 UTC (3 years, 8 months ago) by skrll
Branch: MAIN
Changes since 1.69: +13 -12 lines
Diff to previous 1.69 (colored)

Part II of ad's aarch64 performance improvements (cpu_switch.S bugs are
all mine)

- Use tpidr_el1 to hold curlwp and not curcpu, because curlwp is accessed
  much more often by MI code.  It also makes curlwp preemption safe and
  allows aarch64_curlwp() to be a const function (curcpu must be volatile).

- Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs
  can see spurious ASTs (which doesn't cause a problem, it just means some
  time may be wasted).

- Use plain stores to set/clear ASTs.  Make sure ASTs are always set on the
  same CPU as the target LWP, and delivered via IPI if posted from a remote
  CPU so that they are resolved quickly.

- Add some cache line padding to struct cpu_info, to match x86.

- Add a memory barrier in a couple of places where ci_curlwp is set.  This
  is needed whenever an LWP that is resuming on the CPU could hold an
  adaptive mutex.  The barrier needs to drain the CPU's store buffer, so
  that the update to ci_curlwp becomes globally visible before the LWP can
  resume and call mutex_exit().  By my reading of the ARM docs it looks like
  the instruction I used will do the right thing, but I'm not 100% sure.

Revision 1.69 / (download) - annotate - [select for diffs], Sun Aug 2 06:58:16 2020 UTC (3 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.68: +10 -2 lines
Diff to previous 1.68 (colored)

Add support for Privileged Access Never (ARMv8.1-PAN).

PAN provides the same functionality as SMAP on x86: it forbids kernel
access to userland pages when PSTATE.PAN=1, and allows such accesses when
PSTATE.PAN=0.

We clear SCTLR_SPAN, to guarantee that PAN=1 each time the kernel is
entered. We catch PAN faults and panic right away without further
processing. In copyin, copyout, etc, we temporarily authorize access to
userland pages.

PAN is a very useful exploit mitigation. Reviewed by ryo@, thanks. Tested
on Qemu. Enabled by default.

Revision 1.68 / (download) - annotate - [select for diffs], Fri Jul 17 07:16:10 2020 UTC (3 years, 9 months ago) by ryo
Branch: MAIN
Changes since 1.67: +5 -6 lines
Diff to previous 1.67 (colored)

Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter().
Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.

Revision 1.67 / (download) - annotate - [select for diffs], Thu Jul 16 11:36:35 2020 UTC (3 years, 9 months ago) by skrll
Branch: MAIN
Changes since 1.66: +37 -91 lines
Diff to previous 1.66 (colored)

pmapboot_enter simplication
- bootpage_alloc in asm becomes pmapboot_pagealloc in C
- PMAPBOOT_ENTER_NOBLOCK is removed as it's not used
- PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on
- physpage_allocator argument is removed as it's always
  pmapboot_pagealloc
- Support for EARLYCONS without CONSADDR is removed so that the identity
  map for CONSADDR is always known.

For the assembly files:
 2 files changed, 40 insertions(+), 89 deletions(-)

LGTM ryo

Revision 1.66 / (download) - annotate - [select for diffs], Sun Jul 12 06:37:39 2020 UTC (3 years, 9 months ago) by skrll
Branch: MAIN
Changes since 1.65: +5 -2 lines
Diff to previous 1.65 (colored)

More DEBUG

Revision 1.65 / (download) - annotate - [select for diffs], Sun Jul 12 06:35:58 2020 UTC (3 years, 9 months ago) by skrll
Branch: MAIN
Changes since 1.64: +11 -11 lines
Diff to previous 1.64 (colored)

KNF (whitespace)

Revision 1.64 / (download) - annotate - [select for diffs], Thu May 28 04:51:44 2020 UTC (3 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.63: +15 -4 lines
Diff to previous 1.63 (colored)

- make AP{IB,DA,DB}Key are also enabled when ARMV83_PAC.
- If no ARMV83_PAC, clearly disable SCTLR_En{IA,IB,DA,DB}

Revision 1.63 / (download) - annotate - [select for diffs], Wed May 27 19:49:37 2020 UTC (3 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.62: +3 -3 lines
Diff to previous 1.62 (colored)

don't use x8 (caller-saved register) across functions

fix llvm+EARLYCONS kernel doesn't boot. it was working luckily with gcc.

Revision 1.62 / (download) - annotate - [select for diffs], Tue May 26 09:16:33 2020 UTC (3 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.61: +4 -4 lines
Diff to previous 1.61 (colored)

clang assembler evaluates #'\r' as #0x72. Grrr

Revision 1.61 / (download) - annotate - [select for diffs], Tue May 26 07:23:57 2020 UTC (3 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.60: +3 -2 lines
Diff to previous 1.60 (colored)

fixed that BTI trap will be occured when AP jumps to mp_vstart on ARMV85_BTI+SMP evironment.

Revision 1.60 / (download) - annotate - [select for diffs], Fri May 15 04:55:40 2020 UTC (3 years, 11 months ago) by ryo
Branch: MAIN
Changes since 1.59: +12 -2 lines
Diff to previous 1.59 (colored)

SCTLR_EnIA should be enabled in the caller(locore).

For some reason, gcc make aarch64_pac_init() function non-leaf, and it uses paciasp/autiasp.

Revision 1.59 / (download) - annotate - [select for diffs], Sun Apr 12 07:49:58 2020 UTC (4 years ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20200421, bouyer-xenpvh-base2, bouyer-xenpvh-base1
Changes since 1.58: +10 -2 lines
Diff to previous 1.58 (colored)

Add support for Pointer Authentication (PAC).

We use the "pac-ret" option, to sign the return instruction pointer on
function entry, and authenticate it on function exit. This acts as a
mitigation against ROP.

The authentication uses a per-lwp (secret) I-A key stored in the 128bit
APIAKey register and part of the lwp context. During lwp creation, the
kernel generates a random key, and during context switches, it installs
the key of the target lwp on the CPU.

Userland cannot read the APIAKey register directly. However, it can sign
its pointers with it, because the register is architecturally shared
between userland and the kernel. Although part of the CPU design, it is
a bit of an undesired behavior, because it allows to forge valid kernel
pointers from userland. To avoid that, we don't share the key with
userland, and rather switch it in EL0<->EL1 transitions. This means that
when userland executes, a different key is loaded in APIAKey than the one
the kernel uses. For now the userland key is a fixed 128bit zero value.

The DDB stack unwinder is changed to strip the authentication code from
the pointers in lr.

Two problems are known:

 * Currently the idlelwps' keys are not really secret. This is because
   the RNG is not yet available when we spawn these lwps. Not overly
   important, but would be nice to fix with UEFI RNG.
 * The key switching in EL0<->EL1 transitions is not the most optimized
   code on the planet. Instead of checking aarch64_pac_enabled, it would
   be better to hot-patch the code at boot time, but there currently is
   no hot-patch support on aarch64.

Tested on Qemu.

Revision 1.58 / (download) - annotate - [select for diffs], Thu Feb 20 07:52:55 2020 UTC (4 years, 1 month ago) by skrll
Branch: MAIN
CVS Tags: phil-wifi-20200411, phil-wifi-20200406, is-mlppp-base, is-mlppp, bouyer-xenpvh-base, ad-namecache-base3
Branch point for: bouyer-xenpvh
Changes since 1.57: +6 -4 lines
Diff to previous 1.57 (colored)

Use orr instead of mov (an alias for orr) to appease clang... *shrug*

Revision 1.57 / (download) - annotate - [select for diffs], Sat Feb 15 13:51:33 2020 UTC (4 years, 2 months ago) by tnn
Branch: MAIN
Changes since 1.56: +5 -5 lines
Diff to previous 1.56 (colored)

avoid nesting /*'s (-Wcomment)

Revision 1.56 / (download) - annotate - [select for diffs], Sat Feb 15 08:16:10 2020 UTC (4 years, 2 months ago) by skrll
Branch: MAIN
Changes since 1.55: +24 -18 lines
Diff to previous 1.55 (colored)

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
  drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
  - a static cpu_info_store array
  - the same arm_cpu_{hatched,mbox}

Revision 1.55 / (download) - annotate - [select for diffs], Sun Feb 9 08:09:58 2020 UTC (4 years, 2 months ago) by skrll
Branch: MAIN
Changes since 1.54: +5 -3 lines
Diff to previous 1.54 (colored)

Improve comments

Revision 1.54 / (download) - annotate - [select for diffs], Tue Jan 28 17:33:07 2020 UTC (4 years, 2 months ago) by maxv
Branch: MAIN
Changes since 1.53: +3 -3 lines
Diff to previous 1.53 (colored)

Jazelle and T32EE are not part of ARMv8, fix the bits to their real
meanings. No functional change.

Revision 1.53 / (download) - annotate - [select for diffs], Sun Jan 19 16:12:56 2020 UTC (4 years, 3 months ago) by skrll
Branch: MAIN
CVS Tags: ad-namecache-base2
Changes since 1.52: +24 -30 lines
Diff to previous 1.52 (colored)

Replace the two copies of the ADDR macro with a centralised adrl macro.
The adrl name matches the one used by armasm.

Revision 1.52 / (download) - annotate - [select for diffs], Wed Jan 15 08:34:04 2020 UTC (4 years, 3 months ago) by mrg
Branch: MAIN
CVS Tags: ad-namecache-base1
Changes since 1.51: +3 -3 lines
Diff to previous 1.51 (colored)

port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system.  tested
on rockpro64 and pinebook pro.

Revision 1.51 / (download) - annotate - [select for diffs], Sun Jan 12 09:29:18 2020 UTC (4 years, 3 months ago) by mrg
Branch: MAIN
Changes since 1.50: +4 -3 lines
Diff to previous 1.50 (colored)

provide some semblance of valid cpu topology for big.little systems.

while attaching cpus, if the FDT provides "capacity-dmips-mhz" track
the fastest set, and call cpu_topology_set() with slow=true for any
cpus that are not the fastest.

bug fix for cpu_topology_set(): actually set ci_is_slow for slow cpus.

with this change, and -current's recent scheduler changes, this means
that long running processes run on the faster cores.  on RK3399 based
systems, i am seeing 20-50% speed ups for many tasks.


XXX: all this can be made common with armv7 big.little.

Revision 1.50 / (download) - annotate - [select for diffs], Wed Jan 8 05:41:07 2020 UTC (4 years, 3 months ago) by ryo
Branch: MAIN
CVS Tags: ad-namecache-base
Branch point for: ad-namecache
Changes since 1.49: +2 -3 lines
Diff to previous 1.49 (colored)

fix panic when modload.

>panic: kernel diagnostic assertion "!pmap_extract(pmap_kernel(), loopva, NULL)" failed: file "../../../../uvm/uvm_km.c", line 674 loopva=0xffffffc001000000'

The space allocated by bootpage_alloc() is only used as a physical page
for pagetable pages, so there is no need to map it with KVA.
And kernend_extra should not have consumed any KVA space.

Revision 1.49 / (download) - annotate - [select for diffs], Sat Dec 28 17:19:43 2019 UTC (4 years, 3 months ago) by jmcneill
Branch: MAIN
Changes since 1.48: +6 -4 lines
Diff to previous 1.48 (colored)

Do not use Early Write Acknowledge for PCIe I/O and config space.

Revision 1.48 / (download) - annotate - [select for diffs], Fri Dec 27 18:56:47 2019 UTC (4 years, 3 months ago) by jmcneill
Branch: MAIN
Changes since 1.47: +8 -3 lines
Diff to previous 1.47 (colored)

Enable early write acknowledge for device memory mappings.

Revision 1.47 / (download) - annotate - [select for diffs], Thu Dec 26 08:48:53 2019 UTC (4 years, 3 months ago) by skrll
Branch: MAIN
Changes since 1.46: +2 -5 lines
Diff to previous 1.46 (colored)

Whitespace

Revision 1.46 / (download) - annotate - [select for diffs], Sun Dec 8 10:37:19 2019 UTC (4 years, 4 months ago) by skrll
Branch: MAIN
Changes since 1.45: +4 -2 lines
Diff to previous 1.45 (colored)

Mark FDT as non-exec and create KVA=VA mapping of same size as identity
mapping, i.e. include BOOTPAGE_ALLOC_MAX

Revision 1.45 / (download) - annotate - [select for diffs], Fri Nov 22 05:21:19 2019 UTC (4 years, 4 months ago) by mlelstv
Branch: MAIN
Changes since 1.44: +9 -2 lines
Diff to previous 1.44 (colored)

Make cache operations available early.

Revision 1.44 / (download) - annotate - [select for diffs], Sun Oct 20 14:03:51 2019 UTC (4 years, 6 months ago) by jmcneill
Branch: MAIN
CVS Tags: phil-wifi-20191119
Changes since 1.43: +21 -10 lines
Diff to previous 1.43 (colored)

Use separate cacheline aligned arrays for mbox and hatched as before.

Revision 1.43 / (download) - annotate - [select for diffs], Sun Oct 20 12:25:43 2019 UTC (4 years, 6 months ago) by skrll
Branch: MAIN
Changes since 1.42: +4 -6 lines
Diff to previous 1.42 (colored)

Avoid overlap between BP and last AP stack. AP stacks are now in order of
increasing address order.

Spotted by and idea from mlelstv.

Revision 1.42 / (download) - annotate - [select for diffs], Sat Oct 19 18:04:26 2019 UTC (4 years, 6 months ago) by jmcneill
Branch: MAIN
Changes since 1.41: +13 -17 lines
Diff to previous 1.41 (colored)

Increase aarch64 MAXCPUS to 256.

Revision 1.41 / (download) - annotate - [select for diffs], Sun Sep 29 08:33:20 2019 UTC (4 years, 6 months ago) by skrll
Branch: MAIN
Changes since 1.40: +3 -3 lines
Diff to previous 1.40 (colored)

Typo in comment

Revision 1.40 / (download) - annotate - [select for diffs], Sun Sep 8 12:17:23 2019 UTC (4 years, 7 months ago) by jmcneill
Branch: MAIN
Changes since 1.39: +4 -2 lines
Diff to previous 1.39 (colored)

Map device memory for early console XN

Revision 1.39 / (download) - annotate - [select for diffs], Wed Jul 17 08:39:03 2019 UTC (4 years, 9 months ago) by skrll
Branch: MAIN
CVS Tags: netbsd-9-base
Branch point for: netbsd-9
Changes since 1.38: +3 -3 lines
Diff to previous 1.38 (colored)

Spell endianness correctly in comments

Revision 1.38 / (download) - annotate - [select for diffs], Mon Jul 15 11:46:53 2019 UTC (4 years, 9 months ago) by skrll
Branch: MAIN
Changes since 1.37: +3 -3 lines
Diff to previous 1.37 (colored)

Fix a comment

Revision 1.37 / (download) - annotate - [select for diffs], Mon Jul 15 11:45:54 2019 UTC (4 years, 9 months ago) by skrll
Branch: MAIN
Changes since 1.36: +3 -3 lines
Diff to previous 1.36 (colored)

Restore the comment against the line changed in the last commit

Revision 1.36 / (download) - annotate - [select for diffs], Mon Jul 15 11:27:19 2019 UTC (4 years, 9 months ago) by skrll
Branch: MAIN
Changes since 1.35: +3 -3 lines
Diff to previous 1.35 (colored)

Pass the VA of start (and not VM_MIN_KERNEL_ADDRESS) when mapping the
kernel at its KVA address.  Previously the last 64 bytes of the .bss might
not be mapped if _end was within 64 bytes of a L2_SIZE boundary

Revision 1.35 / (download) - annotate - [select for diffs], Thu Jul 11 10:53:39 2019 UTC (4 years, 9 months ago) by skrll
Branch: MAIN
Changes since 1.34: +3 -3 lines
Diff to previous 1.34 (colored)

Typo in comment

Revision 1.34 / (download) - annotate - [select for diffs], Thu Jul 11 09:03:41 2019 UTC (4 years, 9 months ago) by skrll
Branch: MAIN
Changes since 1.33: +2 -3 lines
Diff to previous 1.33 (colored)

Remove unnecessary #include

Revision 1.33 / (download) - annotate - [select for diffs], Sun Jan 27 02:08:36 2019 UTC (5 years, 2 months ago) by pgoyette
Branch: MAIN
CVS Tags: phil-wifi-20190609, isaki-audio2-base, isaki-audio2
Changes since 1.32: +2 -3 lines
Diff to previous 1.32 (colored)

Merge the [pgoyette-compat] branch

Revision 1.32 / (download) - annotate - [select for diffs], Thu Dec 13 10:44:25 2018 UTC (5 years, 4 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-20190127, pgoyette-compat-20190118, pgoyette-compat-1226
Changes since 1.31: +11 -4 lines
Diff to previous 1.31 (colored)

add support PT_STEP

Revision 1.31 / (download) - annotate - [select for diffs], Thu Nov 8 08:28:07 2018 UTC (5 years, 5 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-1126
Changes since 1.30: +7 -2 lines
Diff to previous 1.30 (colored)

Track the stack with kASan on aarch64. Same principle as on amd64. Illegal
accesses occurring there are now detected.

Originally written by me, but reworked by ryo@, thanks.

Revision 1.30 / (download) - annotate - [select for diffs], Thu Oct 18 09:01:51 2018 UTC (5 years, 6 months ago) by skrll
Branch: MAIN
CVS Tags: pgoyette-compat-1020
Changes since 1.29: +10 -7 lines
Diff to previous 1.29 (colored)

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors.  AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested.  Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Revision 1.29 / (download) - annotate - [select for diffs], Fri Oct 12 01:28:57 2018 UTC (5 years, 6 months ago) by ryo
Branch: MAIN
Changes since 1.28: +5 -2 lines
Diff to previous 1.28 (colored)

add initial support of COMPAT_NETBSD32 on AArch64.
arm ELF32 EABI binaries could be execute in AArch32 state on AArch64. A32 THUMB mode is not supported yet.

Revision 1.28 / (download) - annotate - [select for diffs], Thu Oct 4 23:53:13 2018 UTC (5 years, 6 months ago) by ryo
Branch: MAIN
Changes since 1.27: +611 -686 lines
Diff to previous 1.27 (colored)

cleanup locore, and changed the way to map memories during boot.
- add functions bootpage_enter() and bootpage_alloc() to adapt various layout
  of physical memory map. especially for 64bit physical memory layout.
  pmapboot_alloc() allocates pagetable pages from _end[].
- changed to map only the required amount for PA=VA identity mapping
  (kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte).
- changing page permission for kernel image, and making KSEG mapping are done
  at cpu_kernel_vm_init() instead of at locore.
- optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.

reviewed by skrll@, thanks.

Revision 1.27 / (download) - annotate - [select for diffs], Thu Oct 4 09:09:29 2018 UTC (5 years, 6 months ago) by ryo
Branch: MAIN
Changes since 1.26: +5 -11 lines
Diff to previous 1.26 (colored)

* define LX_BLKPAG_{OS,ATTR}_* for OS dependent PTE attributes in pmap.h
* cleanup macros

Revision 1.26 / (download) - annotate - [select for diffs], Mon Oct 1 19:45:00 2018 UTC (5 years, 6 months ago) by skrll
Branch: MAIN
Changes since 1.25: +4 -2 lines
Diff to previous 1.25 (colored)

Comment out printing L2CTLR_EL1 as it is implementation specific.

OK ryo

Revision 1.25 / (download) - annotate - [select for diffs], Mon Sep 10 11:05:12 2018 UTC (5 years, 7 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-0930
Changes since 1.24: +19 -7 lines
Diff to previous 1.24 (colored)

cleanup aarch64 mpstart and fdt bootstrap
 * arm_cpu_hatch_arg is a bad idea. avoid serializing CPU startup, and eliminate arm_cpu_hatch_arg.
   in mpstart, resolve own cpu index using array of cpu_mpidr[] (aarch64)
 * add support fdt enable-method "spin-table"
 * add support fdt enable-method "brcm,bcm2836-smp" (for 32bit RaspberryPi)
 * use arm_fdt_cpu_bootstrap() instead of psci_fdt_bootstrap()
 * rename "arm/fdt/psci_fdt.h" to "arm/fdt/psci_fdtvar.h" because of conflict of include file for needs-flag
 * add devmap for cpu spin-table of raspberrypi3/aarch64
 * no need to force hatch APs for raspberrypi3/arm32 ifndef MULTIPROCESSOR.
 * fix to work pmap_extract(kerneltext/data/bss) even if before calling pmap_bootstrap

idea to use cpu_mpidr[] by jmcneill@. reviewd by skrll@. thanks.

Revision 1.24 / (download) - annotate - [select for diffs], Mon Sep 10 07:30:33 2018 UTC (5 years, 7 months ago) by skrll
Branch: MAIN
Changes since 1.23: +6 -2 lines
Diff to previous 1.23 (colored)

Don't use printx before setting up stack.

Revision 1.23 / (download) - annotate - [select for diffs], Mon Sep 10 05:14:42 2018 UTC (5 years, 7 months ago) by skrll
Branch: MAIN
Changes since 1.22: +7 -7 lines
Diff to previous 1.22 (colored)

Fix typos and DEBUG_MMU output.  From Rin Okuyama.

Revision 1.22 / (download) - annotate - [select for diffs], Tue Sep 4 15:50:25 2018 UTC (5 years, 7 months ago) by skrll
Branch: MAIN
CVS Tags: pgoyette-compat-0906
Changes since 1.21: +79 -51 lines
Diff to previous 1.21 (colored)

Adjust register usage a bit and unbreak DEBUG_MMU as a result.

The change moves to using callee-saved registers more so that any call
into C will have them preserved (if they're used or not).  It's safe
to use stack as it's setup very early for BP/APs.

Discussed with ryo@

Revision 1.21 / (download) - annotate - [select for diffs], Thu Aug 30 10:38:01 2018 UTC (5 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.20: +30 -23 lines
Diff to previous 1.20 (colored)

Use ASM markers for functions, it makes the code easier to understand and
eliminates raw symbols. No functional change (tested on RPI3B+).

Revision 1.20 / (download) - annotate - [select for diffs], Sun Aug 26 18:15:49 2018 UTC (5 years, 7 months ago) by ryo
Branch: MAIN
Changes since 1.19: +34 -30 lines
Diff to previous 1.19 (colored)

add support multiple cpu clusters.
* pass cpu index as an argument to secondary processors when hatching.
* keep cpu cache confituration per cpu clusters.

Hello big.LITTLE!

Revision 1.19 / (download) - annotate - [select for diffs], Fri Aug 24 19:06:30 2018 UTC (5 years, 7 months ago) by ryo
Branch: MAIN
Changes since 1.18: +6 -6 lines
Diff to previous 1.18 (colored)

set correctly TCR_EL1 for inner shareable when MULTIPROCESSOR

Revision 1.18 / (download) - annotate - [select for diffs], Fri Aug 10 21:06:42 2018 UTC (5 years, 8 months ago) by ryo
Branch: MAIN
Changes since 1.17: +3 -3 lines
Diff to previous 1.17 (colored)

treat kernel-exec attr and user-exec attr separately.
kernel cannot execute userland exec page, and user cannot execute kernel page.

Revision 1.17 / (download) - annotate - [select for diffs], Fri Aug 10 17:46:06 2018 UTC (5 years, 8 months ago) by maxv
Branch: MAIN
Changes since 1.16: +15 -12 lines
Diff to previous 1.16 (colored)

Enlighten a little.

Revision 1.16 / (download) - annotate - [select for diffs], Mon Aug 6 20:05:26 2018 UTC (5 years, 8 months ago) by ryo
Branch: MAIN
Changes since 1.15: +34 -2 lines
Diff to previous 1.15 (colored)

set kernel rodata/data non-executable.
set rodata section on 2Mbytes aligned. (kernel image is mapped with 2Mbytes L2 block)

Revision 1.15 / (download) - annotate - [select for diffs], Mon Aug 6 12:50:56 2018 UTC (5 years, 8 months ago) by ryo
Branch: MAIN
Changes since 1.14: +2 -4 lines
Diff to previous 1.14 (colored)

set kernel text/rodata readonly by default.
add function db_write_text() for setting ddb breakpoint.

Revision 1.14 / (download) - annotate - [select for diffs], Fri Aug 3 16:32:55 2018 UTC (5 years, 8 months ago) by ryo
Branch: MAIN
Changes since 1.13: +38 -3 lines
Diff to previous 1.13 (colored)

set kernel text/rodata readonly when not defined DDB.
set readonly segment on 2Mbytes aligned. (kernel image is mapped with 2Mbytes L2 block)

Revision 1.13 / (download) - annotate - [select for diffs], Tue Jul 17 18:08:36 2018 UTC (5 years, 9 months ago) by christos
Branch: MAIN
CVS Tags: pgoyette-compat-0728
Changes since 1.12: +2 -5 lines
Diff to previous 1.12 (colored)

centralize fp,lr definitions

Revision 1.12 / (download) - annotate - [select for diffs], Tue Jul 17 10:01:59 2018 UTC (5 years, 9 months ago) by ryo
Branch: MAIN
Changes since 1.11: +9 -7 lines
Diff to previous 1.11 (colored)

fix build with aarch64 gcc/gas

Revision 1.11 / (download) - annotate - [select for diffs], Tue Jul 17 00:32:28 2018 UTC (5 years, 9 months ago) by christos
Branch: MAIN
Changes since 1.10: +23 -21 lines
Diff to previous 1.10 (colored)

use c comments instead of #, consistently

Revision 1.10 / (download) - annotate - [select for diffs], Tue Jul 10 08:35:58 2018 UTC (5 years, 9 months ago) by ryo
Branch: MAIN
Changes since 1.9: +7 -2 lines
Diff to previous 1.9 (colored)

allow to read CNTVCT_EL0 and CNTFRQ_EL0 from EL0

Revision 1.9 / (download) - annotate - [select for diffs], Tue Jul 10 08:20:29 2018 UTC (5 years, 9 months ago) by ryo
Branch: MAIN
Changes since 1.8: +4 -4 lines
Diff to previous 1.8 (colored)

allow to execute wfi/wfe instruction on EL0. some userland program use them.

Revision 1.8 / (download) - annotate - [select for diffs], Mon Jul 9 06:19:53 2018 UTC (5 years, 9 months ago) by ryo
Branch: MAIN
Changes since 1.7: +303 -71 lines
Diff to previous 1.7 (colored)

add MULTIPROCESSOR support

Revision 1.7 / (download) - annotate - [select for diffs], Thu Jun 21 11:57:05 2018 UTC (5 years, 10 months ago) by ryo
Branch: MAIN
CVS Tags: phil-wifi-base, pgoyette-compat-0625
Branch point for: phil-wifi
Changes since 1.6: +3 -3 lines
Diff to previous 1.6 (colored)

* make to work printf() and panic() even before consinit().
* tidy up output for VERBOSE_INIT_ARM.

Revision 1.6 / (download) - annotate - [select for diffs], Thu May 17 08:24:28 2018 UTC (5 years, 11 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-0521
Changes since 1.5: +3 -3 lines
Diff to previous 1.5 (colored)

allow to execute cache operation (DC CVAU,DC CIVAC, DC CVAC, IC IVAU) from userland.

Revision 1.5 / (download) - annotate - [select for diffs], Sun Apr 1 04:35:03 2018 UTC (6 years ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-0502, pgoyette-compat-0422, pgoyette-compat-0415, pgoyette-compat-0407
Changes since 1.4: +696 -283 lines
Diff to previous 1.4 (colored)

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

Revision 1.4 / (download) - annotate - [select for diffs], Fri Aug 25 22:23:59 2017 UTC (6 years, 7 months ago) by nisimura
Branch: MAIN
CVS Tags: tls-maxphys-base-20171202, pgoyette-compat-base, pgoyette-compat-0330, pgoyette-compat-0322, pgoyette-compat-0315
Branch point for: pgoyette-compat
Changes since 1.3: +6 -6 lines
Diff to previous 1.3 (colored)


- reorder faultbuf member.
- introduce trap() and interrupt(). now brk insn work.
-

Revision 1.3 / (download) - annotate - [select for diffs], Fri Aug 25 21:43:49 2017 UTC (6 years, 7 months ago) by nisimura
Branch: MAIN
Changes since 1.2: +131 -42 lines
Diff to previous 1.2 (colored)

make them better shape

Revision 1.2 / (download) - annotate - [select for diffs], Wed Aug 16 22:49:05 2017 UTC (6 years, 8 months ago) by nisimura
Branch: MAIN
CVS Tags: nick-nhusb-base-20170825
Changes since 1.1: +40 -2 lines
Diff to previous 1.1 (colored)

add cpu_set_onfault glue

Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.

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