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CVS log for src/sys/arch/aarch64/aarch64/genassym.cf

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Request diff between arbitrary revisions


Default branch: MAIN


Revision 1.39 / (download) - annotate - [select for diffs], Sun Apr 16 14:01:51 2023 UTC (7 weeks, 5 days ago) by skrll
Branch: MAIN
CVS Tags: HEAD
Changes since 1.38: +2 -2 lines
Diff to previous 1.38 (colored)

Rename VM_KERNEL_IO_ADDRESS to VM_KERNEL_IO_BASE to match RISC-V

It's less letters, matches other similar variables and will help with
sharing code between the two architectures.

NFCI.

Revision 1.38 / (download) - annotate - [select for diffs], Sat Jun 25 13:24:34 2022 UTC (11 months, 2 weeks ago) by jmcneill
Branch: MAIN
CVS Tags: netbsd-10-base, netbsd-10, bouyer-sunxi-drm-base, bouyer-sunxi-drm
Changes since 1.37: +1 -4 lines
Diff to previous 1.37 (colored)

Remove GIC_SPLFUNCS.

Revision 1.37 / (download) - annotate - [select for diffs], Sat Oct 30 20:23:11 2021 UTC (19 months, 1 week ago) by jmcneill
Branch: MAIN
Changes since 1.36: +2 -1 lines
Diff to previous 1.36 (colored)

Add __HAVE_PREEMPTION support to gic_splfuncs asm funcs.

"looks right to me" - thorpej

Revision 1.36 / (download) - annotate - [select for diffs], Sat Oct 30 18:49:47 2021 UTC (19 months, 1 week ago) by jmcneill
Branch: MAIN
Changes since 1.35: +3 -1 lines
Diff to previous 1.35 (colored)

Add CI_SPLX_SAVEDIPL and CI_HWPL

Revision 1.35 / (download) - annotate - [select for diffs], Thu Sep 30 21:19:16 2021 UTC (20 months, 1 week ago) by skrll
Branch: MAIN
Changes since 1.34: +2 -1 lines
Diff to previous 1.34 (colored)

Ensure TCR_EPD0 is set on entry to pmap_activate and ensure it is set as
early as possible for APs.

Revision 1.34 / (download) - annotate - [select for diffs], Sat Sep 18 12:25:06 2021 UTC (20 months, 3 weeks ago) by jmcneill
Branch: MAIN
Changes since 1.33: +2 -1 lines
Diff to previous 1.33 (colored)

gic_splx: performance optimizations

Avoid any kind of register access (DAIF, PMR, etc), barriers, and atomic
operations in the common case where no interrupt fires between spl being
raised and lowered.

This introduces a per-CPU return address (ci_splx_restart) used by the
vector handler to restart a sequence in splx that compares the new ipl
with the per-CPU hardware priority state stored in ci_hwpl.

Revision 1.31.2.1 / (download) - annotate - [select for diffs], Mon Dec 14 14:37:44 2020 UTC (2 years, 5 months ago) by thorpej
Branch: thorpej-futex
Changes since 1.31: +5 -4 lines
Diff to previous 1.31 (colored) next main 1.32 (colored)

Sync w/ HEAD.

Revision 1.33 / (download) - annotate - [select for diffs], Fri Dec 11 18:03:33 2020 UTC (2 years, 5 months ago) by skrll
Branch: MAIN
CVS Tags: thorpej-i2c-spi-conf2-base, thorpej-i2c-spi-conf2, thorpej-i2c-spi-conf-base, thorpej-i2c-spi-conf, thorpej-futex2-base, thorpej-futex2, thorpej-futex-base, thorpej-cfargs2-base, thorpej-cfargs2, thorpej-cfargs-base, thorpej-cfargs, cjep_sun2x-base1, cjep_sun2x-base, cjep_sun2x, cjep_staticlib_x-base1, cjep_staticlib_x-base, cjep_staticlib_x
Changes since 1.32: +3 -2 lines
Diff to previous 1.32 (colored)

s:aarch64/cpufunc.h:arm/cpufunc.h:

a baby step in the grand arm header unification challenge

Revision 1.32 / (download) - annotate - [select for diffs], Tue Nov 10 07:51:19 2020 UTC (2 years, 6 months ago) by skrll
Branch: MAIN
Changes since 1.31: +3 -3 lines
Diff to previous 1.31 (colored)

AA64 is not MIPS.

Change all KSEG references to directmap

Revision 1.31 / (download) - annotate - [select for diffs], Tue Sep 15 09:28:20 2020 UTC (2 years, 8 months ago) by ryo
Branch: MAIN
Branch point for: thorpej-futex
Changes since 1.30: +2 -2 lines
Diff to previous 1.30 (colored)

fix typo

Revision 1.30 / (download) - annotate - [select for diffs], Wed Aug 12 13:19:35 2020 UTC (2 years, 9 months ago) by skrll
Branch: MAIN
Changes since 1.29: +2 -2 lines
Diff to previous 1.29 (colored)

Part II of ad's aarch64 performance improvements (cpu_switch.S bugs are
all mine)

- Use tpidr_el1 to hold curlwp and not curcpu, because curlwp is accessed
  much more often by MI code.  It also makes curlwp preemption safe and
  allows aarch64_curlwp() to be a const function (curcpu must be volatile).

- Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs
  can see spurious ASTs (which doesn't cause a problem, it just means some
  time may be wasted).

- Use plain stores to set/clear ASTs.  Make sure ASTs are always set on the
  same CPU as the target LWP, and delivered via IPI if posted from a remote
  CPU so that they are resolved quickly.

- Add some cache line padding to struct cpu_info, to match x86.

- Add a memory barrier in a couple of places where ci_curlwp is set.  This
  is needed whenever an LWP that is resuming on the CPU could hold an
  adaptive mutex.  The barrier needs to drain the CPU's store buffer, so
  that the update to ci_curlwp becomes globally visible before the LWP can
  resume and call mutex_exit().  By my reading of the ARM docs it looks like
  the instruction I used will do the right thing, but I'm not 100% sure.

Revision 1.29 / (download) - annotate - [select for diffs], Thu Aug 6 06:49:55 2020 UTC (2 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.28: +15 -16 lines
Diff to previous 1.28 (colored)

revert the changes of http://mail-index.netbsd.org/source-changes/2020/08/03/msg120183.html

This change is overengineered.
bus_space_{peek,poke}_N does not have to be reentrant nor available for interrupt context.

requested by skrll@

Revision 1.28 / (download) - annotate - [select for diffs], Mon Aug 3 06:29:59 2020 UTC (2 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.27: +4 -1 lines
Diff to previous 1.27 (colored)

Implement MD ucas(9) (__HAVE_UCAS_FULL)

Revision 1.27 / (download) - annotate - [select for diffs], Mon Aug 3 05:56:50 2020 UTC (2 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.26: +16 -15 lines
Diff to previous 1.26 (colored)

Fix a problem in which a fault occured in an interrupt handler during copyin/copyout was erroneously detected as being occured by copyin.

- keep idepth in faultbuf and compare it to avoid unnecessary fault recovery
- make cpu_set_onfault() nestable to use bus_space_{peek,poke}()
  in hardware interrupt handlers during copyin & copyout.

Revision 1.26 / (download) - annotate - [select for diffs], Thu May 28 04:51:44 2020 UTC (3 years ago) by ryo
Branch: MAIN
Changes since 1.25: +4 -1 lines
Diff to previous 1.25 (colored)

- make AP{IB,DA,DB}Key are also enabled when ARMV83_PAC.
- If no ARMV83_PAC, clearly disable SCTLR_En{IA,IB,DA,DB}

Revision 1.25 / (download) - annotate - [select for diffs], Sat May 23 18:08:59 2020 UTC (3 years ago) by ryo
Branch: MAIN
Changes since 1.24: +9 -5 lines
Diff to previous 1.24 (colored)

Not only the kernel thread, but also the userland PAC keys
(APIA,APIB,APDA,APDB,APGA) are now randomly initialized at exec, and switched
when context switch.
userland programs are able to perform pointer authentication on ARMv8.3+PAC cpu.

reviewd by maxv@, thanks.

Revision 1.24 / (download) - annotate - [select for diffs], Fri May 15 04:55:40 2020 UTC (3 years ago) by ryo
Branch: MAIN
Changes since 1.23: +2 -1 lines
Diff to previous 1.23 (colored)

SCTLR_EnIA should be enabled in the caller(locore).

For some reason, gcc make aarch64_pac_init() function non-leaf, and it uses paciasp/autiasp.

Revision 1.2.2.4 / (download) - annotate - [select for diffs], Tue Apr 21 18:42:02 2020 UTC (3 years, 1 month ago) by martin
Branch: phil-wifi
Changes since 1.2.2.3: +4 -0 lines
Diff to previous 1.2.2.3 (colored) to branchpoint 1.2 (colored) next main 1.3 (colored)

Sync with HEAD

Revision 1.22.4.1 / (download) - annotate - [select for diffs], Mon Apr 20 11:28:50 2020 UTC (3 years, 1 month ago) by bouyer
Branch: bouyer-xenpvh
Changes since 1.22: +5 -1 lines
Diff to previous 1.22 (colored) next main 1.23 (colored)

Sync with HEAD

Revision 1.2.2.3 / (download) - annotate - [select for diffs], Mon Apr 13 08:03:27 2020 UTC (3 years, 1 month ago) by martin
Branch: phil-wifi
Changes since 1.2.2.2: +1 -29 lines
Diff to previous 1.2.2.2 (colored) to branchpoint 1.2 (colored)

Mostly merge changes from HEAD upto 20200411

Revision 1.23 / (download) - annotate - [select for diffs], Sun Apr 12 07:49:58 2020 UTC (3 years, 1 month ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20200421, bouyer-xenpvh-base2, bouyer-xenpvh-base1
Changes since 1.22: +5 -1 lines
Diff to previous 1.22 (colored)

Add support for Pointer Authentication (PAC).

We use the "pac-ret" option, to sign the return instruction pointer on
function entry, and authenticate it on function exit. This acts as a
mitigation against ROP.

The authentication uses a per-lwp (secret) I-A key stored in the 128bit
APIAKey register and part of the lwp context. During lwp creation, the
kernel generates a random key, and during context switches, it installs
the key of the target lwp on the CPU.

Userland cannot read the APIAKey register directly. However, it can sign
its pointers with it, because the register is architecturally shared
between userland and the kernel. Although part of the CPU design, it is
a bit of an undesired behavior, because it allows to forge valid kernel
pointers from userland. To avoid that, we don't share the key with
userland, and rather switch it in EL0<->EL1 transitions. This means that
when userland executes, a different key is loaded in APIAKey than the one
the kernel uses. For now the userland key is a fixed 128bit zero value.

The DDB stack unwinder is changed to strip the authentication code from
the pointers in lr.

Two problems are known:

 * Currently the idlelwps' keys are not really secret. This is because
   the RNG is not yet available when we spawn these lwps. Not overly
   important, but would be nice to fix with UEFI RNG.
 * The key switching in EL0<->EL1 transitions is not the most optimized
   code on the planet. Instead of checking aarch64_pac_enabled, it would
   be better to hot-patch the code at boot time, but there currently is
   no hot-patch support on aarch64.

Tested on Qemu.

Revision 1.2.2.2 / (download) - annotate - [select for diffs], Wed Apr 8 14:07:23 2020 UTC (3 years, 2 months ago) by martin
Branch: phil-wifi
Changes since 1.2.2.1: +10 -15 lines
Diff to previous 1.2.2.1 (colored) to branchpoint 1.2 (colored)

Merge changes from current as of 20200406

Revision 1.17.2.2 / (download) - annotate - [select for diffs], Sat Feb 29 20:18:15 2020 UTC (3 years, 3 months ago) by ad
Branch: ad-namecache
Changes since 1.17.2.1: +2 -8 lines
Diff to previous 1.17.2.1 (colored) to branchpoint 1.17 (colored) next main 1.18 (colored)

Sync with head.

Revision 1.22 / (download) - annotate - [select for diffs], Thu Feb 20 08:27:38 2020 UTC (3 years, 3 months ago) by skrll
Branch: MAIN
CVS Tags: phil-wifi-20200411, phil-wifi-20200406, is-mlppp-base, is-mlppp, bouyer-xenpvh-base, ad-namecache-base3
Branch point for: bouyer-xenpvh
Changes since 1.21: +1 -4 lines
Diff to previous 1.21 (colored)

G/C

Revision 1.21 / (download) - annotate - [select for diffs], Wed Jan 29 19:29:23 2020 UTC (3 years, 4 months ago) by skrll
Branch: MAIN
Changes since 1.20: +1 -3 lines
Diff to previous 1.20 (colored)

G/C some more

Revision 1.20 / (download) - annotate - [select for diffs], Wed Jan 29 19:21:51 2020 UTC (3 years, 4 months ago) by skrll
Branch: MAIN
Changes since 1.19: +1 -2 lines
Diff to previous 1.19 (colored)

G/C

Revision 1.19 / (download) - annotate - [select for diffs], Tue Jan 28 17:33:07 2020 UTC (3 years, 4 months ago) by maxv
Branch: MAIN
Changes since 1.18: +2 -2 lines
Diff to previous 1.18 (colored)

Jazelle and T32EE are not part of ARMv8, fix the bits to their real
meanings. No functional change.

Revision 1.17.2.1 / (download) - annotate - [select for diffs], Fri Jan 17 21:47:22 2020 UTC (3 years, 4 months ago) by ad
Branch: ad-namecache
Changes since 1.17: +1 -2 lines
Diff to previous 1.17 (colored)

Sync with head.

Revision 1.18 / (download) - annotate - [select for diffs], Wed Jan 8 17:38:41 2020 UTC (3 years, 5 months ago) by ad
Branch: MAIN
CVS Tags: ad-namecache-base2, ad-namecache-base1
Changes since 1.17: +1 -2 lines
Diff to previous 1.17 (colored)

Hopefully fix some problems seen with MP support on non-x86, in particular
where curcpu() is defined as curlwp->l_cpu:

- mi_switch(): undo the ~2007ish optimisation to unlock curlwp before
  calling cpu_switchto().  It's not safe to let other actors mess with the
  LWP (in particular l->l_cpu) while it's still context switching.  This
  removes l->l_ctxswtch.

- Move the LP_RUNNING flag into l->l_flag and rename to LW_RUNNING since
  it's now covered by the LWP's lock.

- Ditch lwp_exit_switchaway() and just call mi_switch() instead.  Everything
  is in cache anyway so it wasn't buying much by trying to avoid saving old
  state.  This means cpu_switchto() will never be called with prevlwp ==
  NULL.

- Remove some KERNEL_LOCK handling which hasn't been needed for years.

Revision 1.13.2.1 / (download) - annotate - [select for diffs], Sun Dec 29 09:27:09 2019 UTC (3 years, 5 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-3-RELEASE, netbsd-9-2-RELEASE, netbsd-9-1-RELEASE, netbsd-9-0-RELEASE, netbsd-9-0-RC2
Changes since 1.13: +3 -1 lines
Diff to previous 1.13 (colored) next main 1.14 (colored)

Pull up following revision(s) (requested by jmcneill in ticket #586):

	sys/arch/arm/nvidia/tegra_pcie.c: revision 1.27
	sys/arch/aarch64/aarch64/pmap.c: revision 1.57
	sys/arch/aarch64/aarch64/locore.S: revision 1.48
	sys/arch/aarch64/include/armreg.h: revision 1.29
	sys/arch/aarch64/aarch64/pmap.c: revision 1.58
	sys/arch/aarch64/aarch64/locore.S: revision 1.49
	sys/arch/arm/acpi/acpipchb.c: revision 1.14
	sys/arch/aarch64/aarch64/genassym.cf: revision 1.16
	sys/arch/arm/acpi/acpi_machdep.c: revision 1.13
	sys/arch/aarch64/include/pmap.h: revision 1.27
	sys/arch/aarch64/aarch64/genassym.cf: revision 1.17
	sys/arch/aarch64/include/pmap.h: revision 1.28
	sys/arch/arm/fdt/pcihost_fdtvar.h: revision 1.3
	sys/arch/arm/include/bus_defs.h: revision 1.14
	sys/arch/aarch64/aarch64/bus_space.c: revision 1.9
	sys/arch/arm/fdt/pcihost_fdt.c: revision 1.12
	sys/arch/aarch64/conf/files.aarch64: revision 1.15
	sys/arch/aarch64/conf/files.aarch64: revision 1.16
	sys/arch/arm/rockchip/rk3399_pcie.c: revision 1.9

Enable early write acknowledge for device memory mappings.

Do not use Early Write Acknowledge for PCIe I/O and config space.

Revision 1.17 / (download) - annotate - [select for diffs], Sat Dec 28 17:19:43 2019 UTC (3 years, 5 months ago) by jmcneill
Branch: MAIN
CVS Tags: ad-namecache-base
Branch point for: ad-namecache
Changes since 1.16: +2 -1 lines
Diff to previous 1.16 (colored)

Do not use Early Write Acknowledge for PCIe I/O and config space.

Revision 1.16 / (download) - annotate - [select for diffs], Fri Dec 27 18:56:47 2019 UTC (3 years, 5 months ago) by jmcneill
Branch: MAIN
Changes since 1.15: +2 -1 lines
Diff to previous 1.15 (colored)

Enable early write acknowledge for device memory mappings.

Revision 1.15 / (download) - annotate - [select for diffs], Sun Nov 24 11:23:16 2019 UTC (3 years, 6 months ago) by skrll
Branch: MAIN
Changes since 1.14: +7 -7 lines
Diff to previous 1.14 (colored)

corect #include order

Revision 1.14 / (download) - annotate - [select for diffs], Sat Sep 7 11:15:25 2019 UTC (3 years, 9 months ago) by ryo
Branch: MAIN
CVS Tags: phil-wifi-20191119
Changes since 1.13: +2 -1 lines
Diff to previous 1.13 (colored)

add AARCH64_KSEG_MASK. pmap_page.S refer it. (but no functional changed)

Revision 1.13 / (download) - annotate - [select for diffs], Sat Jul 13 09:47:14 2019 UTC (3 years, 10 months ago) by skrll
Branch: MAIN
CVS Tags: netbsd-9-base, netbsd-9-0-RC1
Branch point for: netbsd-9
Changes since 1.12: +1 -30 lines
Diff to previous 1.12 (colored)

G/C

Revision 1.2.2.1 / (download) - annotate - [select for diffs], Mon Jun 10 22:05:43 2019 UTC (4 years ago) by christos
Branch: phil-wifi
Changes since 1.2: +79 -2 lines
Diff to previous 1.2 (colored)

Sync with HEAD

Revision 1.1.28.7 / (download) - annotate - [select for diffs], Fri Jan 18 08:50:13 2019 UTC (4 years, 4 months ago) by pgoyette
Branch: pgoyette-compat
CVS Tags: pgoyette-compat-merge-20190127
Changes since 1.1.28.6: +3 -2 lines
Diff to previous 1.1.28.6 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored)

Synch with HEAD

Revision 1.12 / (download) - annotate - [select for diffs], Thu Dec 27 09:55:27 2018 UTC (4 years, 5 months ago) by mrg
Branch: MAIN
CVS Tags: phil-wifi-20190609, pgoyette-compat-20190127, pgoyette-compat-20190118, isaki-audio2-base, isaki-audio2
Changes since 1.11: +3 -2 lines
Diff to previous 1.11 (colored)

make savecore for arm64 basically work.

- move MD lwp "md_ktf" member into struct pcb.  the pcb is used by
  the gdb "bsd-kvm" target code to find the stack of each thread
  and needs to be available in a well known location.
- implement aarch64_nbsd_supply_pcb() in GDB.  makes basic gdb work
  on a crash dump.
- remove '#if L_MD_KTF + 8 == L_MD_CPACR' conditional code, as there
  is no more L_MD_KTF.

with this gdb has minimal working functionality with "target kvm",
and crash can at least "ps" on a crash dump.

ok skrll.

Revision 1.1.28.6 / (download) - annotate - [select for diffs], Wed Dec 26 14:01:30 2018 UTC (4 years, 5 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.28.5: +9 -1 lines
Diff to previous 1.1.28.5 (colored) to branchpoint 1.1 (colored)

Sync with HEAD, resolve a few conflicts

Revision 1.11 / (download) - annotate - [select for diffs], Thu Dec 13 10:44:25 2018 UTC (4 years, 5 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-1226
Changes since 1.10: +7 -1 lines
Diff to previous 1.10 (colored)

add support PT_STEP

Revision 1.10 / (download) - annotate - [select for diffs], Tue Dec 11 05:46:14 2018 UTC (4 years, 5 months ago) by ryo
Branch: MAIN
Changes since 1.9: +3 -1 lines
Diff to previous 1.9 (colored)

fix build failure without options MULTIPROCESSOR

Revision 1.1.28.5 / (download) - annotate - [select for diffs], Mon Nov 26 01:52:16 2018 UTC (4 years, 6 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.28.4: +3 -3 lines
Diff to previous 1.1.28.4 (colored) to branchpoint 1.1 (colored)

Sync with HEAD, resolve a couple of conflicts

Revision 1.9 / (download) - annotate - [select for diffs], Tue Nov 20 01:59:51 2018 UTC (4 years, 6 months ago) by mrg
Branch: MAIN
CVS Tags: pgoyette-compat-1126
Changes since 1.8: +3 -3 lines
Diff to previous 1.8 (colored)

rewrite the CPU identification on arm64:

- publish per-cpu data
- publish a whole bunch of info in struct aarch64_sysctl_cpu_id
  instead of various individual nodes (there are 16 total.)
- add MIDR extractor bits
- define ARMv8.2-A id_aa64mmfr2_el1 and id_aa64zfr0_el1 regs,
  but avoid using them until we make sure they exist.  (these
  members are added to aarch64_sysctl_cpu_id to avoid future
  compat issues.)

the arm32 and aarch32 version of these need to be adjusted as
well (and aarch32 data published at all.)  still trying to
work out how to make the same userland binary running on a
real arm32 or an aarch32 system can work sanely here.

ok ryo@.

Revision 1.1.28.4 / (download) - annotate - [select for diffs], Sat Oct 20 06:58:23 2018 UTC (4 years, 7 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.28.3: +6 -5 lines
Diff to previous 1.1.28.3 (colored) to branchpoint 1.1 (colored)

Sync with head

Revision 1.8 / (download) - annotate - [select for diffs], Thu Oct 4 09:09:29 2018 UTC (4 years, 8 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-1020
Changes since 1.7: +6 -5 lines
Diff to previous 1.7 (colored)

* define LX_BLKPAG_{OS,ATTR}_* for OS dependent PTE attributes in pmap.h
* cleanup macros

Revision 1.1.28.3 / (download) - annotate - [select for diffs], Thu Sep 6 06:55:22 2018 UTC (4 years, 9 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.28.2: +6 -1 lines
Diff to previous 1.1.28.2 (colored) to branchpoint 1.1 (colored)

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

Revision 1.7 / (download) - annotate - [select for diffs], Sun Aug 26 18:15:49 2018 UTC (4 years, 9 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-0930, pgoyette-compat-0906
Changes since 1.6: +4 -1 lines
Diff to previous 1.6 (colored)

add support multiple cpu clusters.
* pass cpu index as an argument to secondary processors when hatching.
* keep cpu cache confituration per cpu clusters.

Hello big.LITTLE!

Revision 1.6 / (download) - annotate - [select for diffs], Fri Aug 3 16:32:55 2018 UTC (4 years, 10 months ago) by ryo
Branch: MAIN
Changes since 1.5: +3 -1 lines
Diff to previous 1.5 (colored)

set kernel text/rodata readonly when not defined DDB.
set readonly segment on 2Mbytes aligned. (kernel image is mapped with 2Mbytes L2 block)

Revision 1.1.28.2 / (download) - annotate - [select for diffs], Sat Jul 28 04:37:25 2018 UTC (4 years, 10 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.28.1: +63 -1 lines
Diff to previous 1.1.28.1 (colored) to branchpoint 1.1 (colored)

Sync with HEAD

Revision 1.5 / (download) - annotate - [select for diffs], Tue Jul 17 10:01:59 2018 UTC (4 years, 10 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-0728
Changes since 1.4: +57 -1 lines
Diff to previous 1.4 (colored)

fix build with aarch64 gcc/gas

Revision 1.4 / (download) - annotate - [select for diffs], Tue Jul 10 08:35:58 2018 UTC (4 years, 11 months ago) by ryo
Branch: MAIN
Changes since 1.3: +2 -1 lines
Diff to previous 1.3 (colored)

allow to read CNTVCT_EL0 and CNTFRQ_EL0 from EL0

Revision 1.3 / (download) - annotate - [select for diffs], Mon Jul 9 06:19:53 2018 UTC (4 years, 11 months ago) by ryo
Branch: MAIN
Changes since 1.2: +6 -1 lines
Diff to previous 1.2 (colored)

add MULTIPROCESSOR support

Revision 1.1.28.1 / (download) - annotate - [select for diffs], Sat Apr 7 04:12:10 2018 UTC (5 years, 2 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1: +143 -10 lines
Diff to previous 1.1 (colored)

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Revision 1.2 / (download) - annotate - [select for diffs], Sun Apr 1 04:35:03 2018 UTC (5 years, 2 months ago) by ryo
Branch: MAIN
CVS Tags: phil-wifi-base, pgoyette-compat-0625, pgoyette-compat-0521, pgoyette-compat-0502, pgoyette-compat-0422, pgoyette-compat-0415, pgoyette-compat-0407
Branch point for: phil-wifi
Changes since 1.1: +143 -10 lines
Diff to previous 1.1 (colored)

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

Revision 1.1.4.2 / (download) - annotate - [select for diffs], Wed Aug 20 00:02:39 2014 UTC (8 years, 9 months ago) by tls
Branch: tls-maxphys
Changes since 1.1.4.1: +198 -0 lines
Diff to previous 1.1.4.1 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored)

Rebase to HEAD as of a few days ago.

Revision 1.1.4.1, Sun Aug 10 05:47:37 2014 UTC (8 years, 10 months ago) by tls
Branch: tls-maxphys
Changes since 1.1: +0 -198 lines
FILE REMOVED

file genassym.cf was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000

Revision 1.1 / (download) - annotate - [select for diffs], Sun Aug 10 05:47:37 2014 UTC (8 years, 10 months ago) by matt
Branch: MAIN
CVS Tags: tls-maxphys-base-20171202, tls-maxphys-base, prg-localcount2-base3, prg-localcount2-base2, prg-localcount2-base1, prg-localcount2-base, prg-localcount2, pgoyette-localcount-base, pgoyette-localcount-20170426, pgoyette-localcount-20170320, pgoyette-localcount-20170107, pgoyette-localcount-20161104, pgoyette-localcount-20160806, pgoyette-localcount-20160726, pgoyette-localcount, pgoyette-compat-base, pgoyette-compat-0330, pgoyette-compat-0322, pgoyette-compat-0315, perseant-stdc-iso10646-base, perseant-stdc-iso10646, nick-nhusb-base-20170825, nick-nhusb-base-20170204, nick-nhusb-base-20161204, nick-nhusb-base-20161004, nick-nhusb-base-20160907, nick-nhusb-base-20160529, nick-nhusb-base-20160422, nick-nhusb-base-20160319, nick-nhusb-base-20151226, nick-nhusb-base-20150921, nick-nhusb-base-20150606, nick-nhusb-base-20150406, nick-nhusb-base, nick-nhusb, netbsd-8-base, netbsd-8-2-RELEASE, netbsd-8-1-RELEASE, netbsd-8-1-RC1, netbsd-8-0-RELEASE, netbsd-8-0-RC2, netbsd-8-0-RC1, netbsd-8, netbsd-7-nhusb-base-20170116, netbsd-7-nhusb-base, netbsd-7-nhusb, netbsd-7-base, netbsd-7-2-RELEASE, netbsd-7-1-RELEASE, netbsd-7-1-RC2, netbsd-7-1-RC1, netbsd-7-1-2-RELEASE, netbsd-7-1-1-RELEASE, netbsd-7-1, netbsd-7-0-RELEASE, netbsd-7-0-RC3, netbsd-7-0-RC2, netbsd-7-0-RC1, netbsd-7-0-2-RELEASE, netbsd-7-0-1-RELEASE, netbsd-7-0, netbsd-7, matt-nb8-mediatek-base, matt-nb8-mediatek, localcount-20160914, jdolecek-ncq-base, jdolecek-ncq, bouyer-socketcan-base1, bouyer-socketcan-base, bouyer-socketcan
Branch point for: tls-maxphys, pgoyette-compat

Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.

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