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CVS log for src/sys/arch/aarch64/aarch64/fpu.c

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Default branch: MAIN


Revision 1.13 / (download) - annotate - [select for diffs], Sat Aug 20 11:34:08 2022 UTC (5 months, 2 weeks ago) by riastradh
Branch: MAIN
CVS Tags: netbsd-10-base, netbsd-10, bouyer-sunxi-drm-base, bouyer-sunxi-drm, HEAD
Changes since 1.12: +16 -2 lines
Diff to previous 1.12 (colored)

fpu_kern_enter/leave: Disable IPL assertions.

These don't work because mutex_enter/exit on a spin lock may raise an
IPL but not lower it, if another spin lock was already held.  For
example,

	mutex_enter(some_lock_at_IPL_VM);
	printf("foo\n");
	fpu_kern_enter();
	...
	fpu_kern_leave();
	mutex_exit(some_lock_at_IPL_VM);

will trigger the panic, because printf takes a lock at IPL_HIGH where
the IPL wil remain until the mutex_exit.  (This was a nightmare to
track down before I remembered that detail of spin lock IPL
semantics...)

Revision 1.12 / (download) - annotate - [select for diffs], Fri Apr 1 19:57:22 2022 UTC (10 months ago) by riastradh
Branch: MAIN
Changes since 1.11: +5 -4 lines
Diff to previous 1.11 (colored)

x86, arm: Allow fpu_kern_enter/leave while cold.

Normally these are forbidden above IPL_VM, so that FPU usage doesn't
block IPL_SCHED or IPL_HIGH interrupts.  But while cold, e.g. during
builtin module initialization at boot, all interrupts are blocked
anyway so it's a moot point.

Also initialize x86 cpu_info_primary.ci_kfpu_spl to -1 so we don't
trip over an assertion about it while cold -- the assertion is meant
to detect reentrance into fpu_kern_enter/leave, which is prohibited.

Also initialize cpu0's ci_kfpu_spl.

Revision 1.10.2.1 / (download) - annotate - [select for diffs], Mon Dec 14 14:37:44 2020 UTC (2 years, 1 month ago) by thorpej
Branch: thorpej-futex
Changes since 1.10: +3 -2 lines
Diff to previous 1.10 (colored) next main 1.11 (colored)

Sync w/ HEAD.

Revision 1.11 / (download) - annotate - [select for diffs], Fri Dec 11 18:03:33 2020 UTC (2 years, 1 month ago) by skrll
Branch: MAIN
CVS Tags: thorpej-i2c-spi-conf2-base, thorpej-i2c-spi-conf2, thorpej-i2c-spi-conf-base, thorpej-i2c-spi-conf, thorpej-futex2-base, thorpej-futex2, thorpej-futex-base, thorpej-cfargs2-base, thorpej-cfargs2, thorpej-cfargs-base, thorpej-cfargs, cjep_sun2x-base1, cjep_sun2x-base, cjep_sun2x, cjep_staticlib_x-base1, cjep_staticlib_x-base, cjep_staticlib_x
Changes since 1.10: +3 -2 lines
Diff to previous 1.10 (colored)

s:aarch64/cpufunc.h:arm/cpufunc.h:

a baby step in the grand arm header unification challenge

Revision 1.10 / (download) - annotate - [select for diffs], Thu Oct 22 07:31:15 2020 UTC (2 years, 3 months ago) by skrll
Branch: MAIN
Branch point for: thorpej-futex
Changes since 1.9: +8 -8 lines
Diff to previous 1.9 (colored)

Use the dmb/dsb/isb macros... if nothing else they're all now consistent
about the "memory" assembler contraint.

No binary change

Revision 1.9 / (download) - annotate - [select for diffs], Thu Oct 22 07:23:24 2020 UTC (2 years, 3 months ago) by skrll
Branch: MAIN
Changes since 1.8: +3 -2 lines
Diff to previous 1.8 (colored)

Simplify the cpufunc.h header, i.e. always use #include <arm/cpufunc.h>

Revision 1.8 / (download) - annotate - [select for diffs], Sat Aug 1 02:06:59 2020 UTC (2 years, 6 months ago) by riastradh
Branch: MAIN
Changes since 1.7: +46 -4 lines
Diff to previous 1.7 (colored)

Add kthread_fpu_enter/exit support to aarch64.

Revision 1.7 / (download) - annotate - [select for diffs], Mon Jul 13 16:54:03 2020 UTC (2 years, 6 months ago) by riastradh
Branch: MAIN
Changes since 1.6: +4 -11 lines
Diff to previous 1.6 (colored)

Use pcu_save_all_on_cpu, not pcu_save.

We don't care what curlwp is here; we care whose state is in the fpu
registers.

Revision 1.6 / (download) - annotate - [select for diffs], Mon Jul 13 16:52:23 2020 UTC (2 years, 6 months ago) by riastradh
Branch: MAIN
Changes since 1.5: +10 -9 lines
Diff to previous 1.5 (colored)

Limit aarch64 fpu_kern_enter/leave to IPL_VM or below.

Revision 1.5 / (download) - annotate - [select for diffs], Mon Jun 29 23:53:12 2020 UTC (2 years, 7 months ago) by riastradh
Branch: MAIN
Changes since 1.4: +4 -3 lines
Diff to previous 1.4 (colored)

Move aarch64/fpu.h to arm/fpu.h.

Revision 1.4 / (download) - annotate - [select for diffs], Mon Jun 29 23:22:27 2020 UTC (2 years, 7 months ago) by riastradh
Branch: MAIN
Changes since 1.3: +69 -2 lines
Diff to previous 1.3 (colored)

Draft fpu_kern_enter/leave on aarch64.

Revision 1.2.2.1 / (download) - annotate - [select for diffs], Mon Jun 10 22:05:43 2019 UTC (3 years, 7 months ago) by christos
Branch: phil-wifi
Changes since 1.2: +56 -4 lines
Diff to previous 1.2 (colored) next main 1.3 (colored)

Sync with HEAD

Revision 1.1.28.2 / (download) - annotate - [select for diffs], Mon Nov 26 01:52:16 2018 UTC (4 years, 2 months ago) by pgoyette
Branch: pgoyette-compat
CVS Tags: pgoyette-compat-merge-20190127
Changes since 1.1.28.1: +56 -4 lines
Diff to previous 1.1.28.1 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored)

Sync with HEAD, resolve a couple of conflicts

Revision 1.3 / (download) - annotate - [select for diffs], Wed Nov 7 06:47:38 2018 UTC (4 years, 3 months ago) by riastradh
Branch: MAIN
CVS Tags: phil-wifi-20200421, phil-wifi-20200411, phil-wifi-20200406, phil-wifi-20191119, phil-wifi-20190609, pgoyette-compat-20190127, pgoyette-compat-20190118, pgoyette-compat-1226, pgoyette-compat-1126, netbsd-9-base, netbsd-9-3-RELEASE, netbsd-9-2-RELEASE, netbsd-9-1-RELEASE, netbsd-9-0-RELEASE, netbsd-9-0-RC2, netbsd-9-0-RC1, netbsd-9, isaki-audio2-base, isaki-audio2, is-mlppp-base, is-mlppp, bouyer-xenpvh-base2, bouyer-xenpvh-base1, bouyer-xenpvh-base, bouyer-xenpvh, ad-namecache-base3, ad-namecache-base2, ad-namecache-base1, ad-namecache-base, ad-namecache
Changes since 1.2: +56 -4 lines
Diff to previous 1.2 (colored)

When hardware subnormal support is available, disable flush-to-zero.

Similarly, when hardware NaN propagation is available, disable
default-NaN substitution.

This enables IEEE 754 semantics on any hardware that supports it by
default.  Programs that want flush-to-zero or default-NaN substitution
can enable them explicitly.

ok ryo@

Revision 1.1.28.1 / (download) - annotate - [select for diffs], Sat Apr 7 04:12:10 2018 UTC (4 years, 10 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1: +65 -12 lines
Diff to previous 1.1 (colored)

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Revision 1.2 / (download) - annotate - [select for diffs], Sun Apr 1 04:35:03 2018 UTC (4 years, 10 months ago) by ryo
Branch: MAIN
CVS Tags: phil-wifi-base, pgoyette-compat-1020, pgoyette-compat-0930, pgoyette-compat-0906, pgoyette-compat-0728, pgoyette-compat-0625, pgoyette-compat-0521, pgoyette-compat-0502, pgoyette-compat-0422, pgoyette-compat-0415, pgoyette-compat-0407
Branch point for: phil-wifi
Changes since 1.1: +65 -12 lines
Diff to previous 1.1 (colored)

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

Revision 1.1.4.2 / (download) - annotate - [select for diffs], Wed Aug 20 00:02:39 2014 UTC (8 years, 5 months ago) by tls
Branch: tls-maxphys
Changes since 1.1.4.1: +69 -0 lines
Diff to previous 1.1.4.1 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored)

Rebase to HEAD as of a few days ago.

Revision 1.1.4.1, Sun Aug 10 05:47:37 2014 UTC (8 years, 6 months ago) by tls
Branch: tls-maxphys
Changes since 1.1: +0 -69 lines
FILE REMOVED

file fpu.c was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000

Revision 1.1 / (download) - annotate - [select for diffs], Sun Aug 10 05:47:37 2014 UTC (8 years, 6 months ago) by matt
Branch: MAIN
CVS Tags: tls-maxphys-base-20171202, tls-maxphys-base, prg-localcount2-base3, prg-localcount2-base2, prg-localcount2-base1, prg-localcount2-base, prg-localcount2, pgoyette-localcount-base, pgoyette-localcount-20170426, pgoyette-localcount-20170320, pgoyette-localcount-20170107, pgoyette-localcount-20161104, pgoyette-localcount-20160806, pgoyette-localcount-20160726, pgoyette-localcount, pgoyette-compat-base, pgoyette-compat-0330, pgoyette-compat-0322, pgoyette-compat-0315, perseant-stdc-iso10646-base, perseant-stdc-iso10646, nick-nhusb-base-20170825, nick-nhusb-base-20170204, nick-nhusb-base-20161204, nick-nhusb-base-20161004, nick-nhusb-base-20160907, nick-nhusb-base-20160529, nick-nhusb-base-20160422, nick-nhusb-base-20160319, nick-nhusb-base-20151226, nick-nhusb-base-20150921, nick-nhusb-base-20150606, nick-nhusb-base-20150406, nick-nhusb-base, nick-nhusb, netbsd-8-base, netbsd-8-2-RELEASE, netbsd-8-1-RELEASE, netbsd-8-1-RC1, netbsd-8-0-RELEASE, netbsd-8-0-RC2, netbsd-8-0-RC1, netbsd-8, netbsd-7-nhusb-base-20170116, netbsd-7-nhusb-base, netbsd-7-nhusb, netbsd-7-base, netbsd-7-2-RELEASE, netbsd-7-1-RELEASE, netbsd-7-1-RC2, netbsd-7-1-RC1, netbsd-7-1-2-RELEASE, netbsd-7-1-1-RELEASE, netbsd-7-1, netbsd-7-0-RELEASE, netbsd-7-0-RC3, netbsd-7-0-RC2, netbsd-7-0-RC1, netbsd-7-0-2-RELEASE, netbsd-7-0-1-RELEASE, netbsd-7-0, netbsd-7, matt-nb8-mediatek-base, matt-nb8-mediatek, localcount-20160914, jdolecek-ncq-base, jdolecek-ncq, bouyer-socketcan-base1, bouyer-socketcan-base, bouyer-socketcan
Branch point for: tls-maxphys, pgoyette-compat

Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.

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