CVS log for src/sys/arch/aarch64/aarch64/db_machdep.c

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ddb/db_active.h: New home for extern db_active.

This can be included unconditionally, and db_active can then be
queried unconditionally; if DDB is not in the kernel, then db_active
is a constant zero.  Reduces need for #include opt_ddb.h, #ifdef DDB.

- Display "cpu[<CPUINDEX>]" instead of "cpu[<CPUID>]".
- Also add cpu_info->ci_onproc to display.

Only print the appropriate PAR fields for PAR.F={0,1}

Group the fields in the header.

Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
   diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3

When booted with "boot netbsd -1" (disable multiprocessor boot),
"ddb>continue" didn't work when ddb was started by breakpoint trap.

Sync with HEAD.

Make the ddb for pmap / pte information pmap agnostic

Sync with HEAD.

Numeric modifiers conflict with the syntax interpretation of ddb, so use 'b', 'w', 'l', 'q' instead.
Also, change load/store('l','s') to 'r','w' like the other arch.

 >db{0}> machine watch/1 hostname
 >Bad modifier

 >db{0}> machine watch/s1 hostname
 >add watchpoint 0 as ffffc00001087848

- fixed a problem where hardware {break,watch}points other than #0 could not be cleared
- hardware {break,watch}point addresses are now strictly checked

Add support hardware breakpoint and watchpoint again.

Limited support for hardware watchpoint has been available for some time, but it
has not been working properly. In addition, it stopped working at the time of
the PTRACE support commit on 2018-12-13. This has been fixed to work correctly,
and also fixed to be practical by sharing hardware watchpoints and breakpoints
between CPUs on MULTIPROCESSOR.

Also fixed a bug that causes a malfunction when switching CPUs with
"machine cpu N" when entering ddb mode from other than cpu_Debugger().

I have confirmed that the CPU can be switched by "machine cpu N" and return from
ddb properly in each case where ddb is called triggered by ddb break/watchpoint,
hardware break/watchpoint, and cpu_Debugger().

"machine cpu" command shows pc of trapframe and the symbol

match the macro name to the order of the arguments. NFC.

introduce DDB_END_CMD and replace more than 20 copies of the same
list of NULLs and 0.  idea from rillig@.

all touched ports built, several booted.

Avoid duplicate definition of ddb_regs in crash(8).

Fix build as crash(8); Protect db_md_meminfo_cmd() by defined(_KERNEL).

add a command to dump the bootconfig passed meminfo.

Sync w/ HEAD.

s:aarch64/cpufunc.h:arm/cpufunc.h:

a baby step in the grand arm header unification challenge

Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.

Use the dmb/dsb/isb macros... if nothing else they're all now consistent
about the "memory" assembler contraint.

No binary change

Simplify the cpufunc.h header, i.e. always use #include <arm/cpufunc.h>

Part II of ad's aarch64 performance improvements (cpu_switch.S bugs are
all mine)

- Use tpidr_el1 to hold curlwp and not curcpu, because curlwp is accessed
  much more often by MI code.  It also makes curlwp preemption safe and
  allows aarch64_curlwp() to be a const function (curcpu must be volatile).

- Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs
  can see spurious ASTs (which doesn't cause a problem, it just means some
  time may be wasted).

- Use plain stores to set/clear ASTs.  Make sure ASTs are always set on the
  same CPU as the target LWP, and delivered via IPI if posted from a remote
  CPU so that they are resolved quickly.

- Add some cache line padding to struct cpu_info, to match x86.

- Add a memory barrier in a couple of places where ci_curlwp is set.  This
  is needed whenever an LWP that is resuming on the CPU could hold an
  adaptive mutex.  The barrier needs to drain the CPU's store buffer, so
  that the update to ci_curlwp becomes globally visible before the LWP can
  resume and call mutex_exit().  By my reading of the ARM docs it looks like
  the instruction I used will do the right thing, but I'm not 100% sure.

Add ddb "mach reset" command for Arm ports.

fix to do backtrace properly for running LWPs and cpu_lwp_fork().
when dump of pcb_tf, only the switchframe part is now displayed instead of the whole trapframe.

instead of reading memory directly, db_read_bytes() is used to avoid faults in ddb.

for "mach cpuinfo", print ci_biglock_count too.

Sync with HEAD

Sync with HEAD

add the case of kdb_trap(-1) called from pic_ipi_ddb().
it depended on the update timing of 'db_recover'.

Mostly merge changes from HEAD upto 20200411

Merge changes from current as of 20200406

use macro

prevent switching to CPUs that are not responding to IPI_DDB.

add "machine cpuinfo/a" to show cpuinfo[] of all cpus

Align output from db_md_cpuinfo_cmd

Sync with HEAD

- add reg_{s1e0r,s1e0w,s1e1r,s1e1w}_write() macro.
- show the result of AT insn at ddb "machine pte" command.

- add ddb command "machine ttbr" to dump MMU tables.
- tidy up descriptions, usages and messages.

Merge the [pgoyette-compat] branch

Synch with HEAD

make savecore for arm64 basically work.

- move MD lwp "md_ktf" member into struct pcb.  the pcb is used by
  the gdb "bsd-kvm" target code to find the stack of each thread
  and needs to be available in a well known location.
- implement aarch64_nbsd_supply_pcb() in GDB.  makes basic gdb work
  on a crash dump.
- remove '#if L_MD_KTF + 8 == L_MD_CPACR' conditional code, as there
  is no more L_MD_KTF.

with this gdb has minimal working functionality with "target kvm",
and crash can at least "ps" on a crash dump.

ok skrll.

Sync with HEAD, resolve a few conflicts

add support PT_STEP

Comment out implementation specific registers to avoid illegal instruction trap on ThunderX

don't pass illegal cpu index to cpu_lookup(). it may cause KASSERT.

Sync with head

add initial support of COMPAT_NETBSD32 on AArch64.
arm ELF32 EABI binaries could be execute in AArch32 state on AArch64. A32 THUMB mode is not supported yet.

Ssync with HEAD

make kernel-groveling crash(8) work on aarch64

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

no need machine local ddb command pmaphist any more.

use DDB_EXPR_FMT. fix typo.

Sync with HEAD

add missing casts; use PRI?64 instead of ll?

fix compile error

add MULTIPROCESSOR support

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

Rebase to HEAD as of a few days ago.

file db_machdep.c was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000

Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.